ethoc.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Opencore 10/100 ethernet mac driver
  4. *
  5. * Copyright (C) 2007-2008 Avionic Design Development GmbH
  6. * Copyright (C) 2008-2009 Avionic Design GmbH
  7. * Thierry Reding <thierry.reding@avionic-design.de>
  8. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  9. * Copyright (C) 2016 Cadence Design Systems Inc.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <dm.h>
  14. #include <log.h>
  15. #include <dm/platform_data/net_ethoc.h>
  16. #include <linux/io.h>
  17. #include <malloc.h>
  18. #include <net.h>
  19. #include <miiphy.h>
  20. #include <asm/cache.h>
  21. #include <wait_bit.h>
  22. /* register offsets */
  23. #define MODER 0x00
  24. #define INT_SOURCE 0x04
  25. #define INT_MASK 0x08
  26. #define IPGT 0x0c
  27. #define IPGR1 0x10
  28. #define IPGR2 0x14
  29. #define PACKETLEN 0x18
  30. #define COLLCONF 0x1c
  31. #define TX_BD_NUM 0x20
  32. #define CTRLMODER 0x24
  33. #define MIIMODER 0x28
  34. #define MIICOMMAND 0x2c
  35. #define MIIADDRESS 0x30
  36. #define MIITX_DATA 0x34
  37. #define MIIRX_DATA 0x38
  38. #define MIISTATUS 0x3c
  39. #define MAC_ADDR0 0x40
  40. #define MAC_ADDR1 0x44
  41. #define ETH_HASH0 0x48
  42. #define ETH_HASH1 0x4c
  43. #define ETH_TXCTRL 0x50
  44. /* mode register */
  45. #define MODER_RXEN (1 << 0) /* receive enable */
  46. #define MODER_TXEN (1 << 1) /* transmit enable */
  47. #define MODER_NOPRE (1 << 2) /* no preamble */
  48. #define MODER_BRO (1 << 3) /* broadcast address */
  49. #define MODER_IAM (1 << 4) /* individual address mode */
  50. #define MODER_PRO (1 << 5) /* promiscuous mode */
  51. #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
  52. #define MODER_LOOP (1 << 7) /* loopback */
  53. #define MODER_NBO (1 << 8) /* no back-off */
  54. #define MODER_EDE (1 << 9) /* excess defer enable */
  55. #define MODER_FULLD (1 << 10) /* full duplex */
  56. #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
  57. #define MODER_DCRC (1 << 12) /* delayed CRC enable */
  58. #define MODER_CRC (1 << 13) /* CRC enable */
  59. #define MODER_HUGE (1 << 14) /* huge packets enable */
  60. #define MODER_PAD (1 << 15) /* padding enabled */
  61. #define MODER_RSM (1 << 16) /* receive small packets */
  62. /* interrupt source and mask registers */
  63. #define INT_MASK_TXF (1 << 0) /* transmit frame */
  64. #define INT_MASK_TXE (1 << 1) /* transmit error */
  65. #define INT_MASK_RXF (1 << 2) /* receive frame */
  66. #define INT_MASK_RXE (1 << 3) /* receive error */
  67. #define INT_MASK_BUSY (1 << 4)
  68. #define INT_MASK_TXC (1 << 5) /* transmit control frame */
  69. #define INT_MASK_RXC (1 << 6) /* receive control frame */
  70. #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
  71. #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
  72. #define INT_MASK_ALL ( \
  73. INT_MASK_TXF | INT_MASK_TXE | \
  74. INT_MASK_RXF | INT_MASK_RXE | \
  75. INT_MASK_TXC | INT_MASK_RXC | \
  76. INT_MASK_BUSY \
  77. )
  78. /* packet length register */
  79. #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
  80. #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
  81. #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
  82. PACKETLEN_MAX(max))
  83. /* transmit buffer number register */
  84. #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
  85. /* control module mode register */
  86. #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
  87. #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
  88. #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
  89. /* MII mode register */
  90. #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
  91. #define MIIMODER_NOPRE (1 << 8) /* no preamble */
  92. /* MII command register */
  93. #define MIICOMMAND_SCAN (1 << 0) /* scan status */
  94. #define MIICOMMAND_READ (1 << 1) /* read status */
  95. #define MIICOMMAND_WRITE (1 << 2) /* write control data */
  96. /* MII address register */
  97. #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
  98. #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
  99. #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
  100. MIIADDRESS_RGAD(reg))
  101. /* MII transmit data register */
  102. #define MIITX_DATA_VAL(x) ((x) & 0xffff)
  103. /* MII receive data register */
  104. #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
  105. /* MII status register */
  106. #define MIISTATUS_LINKFAIL (1 << 0)
  107. #define MIISTATUS_BUSY (1 << 1)
  108. #define MIISTATUS_INVALID (1 << 2)
  109. /* TX buffer descriptor */
  110. #define TX_BD_CS (1 << 0) /* carrier sense lost */
  111. #define TX_BD_DF (1 << 1) /* defer indication */
  112. #define TX_BD_LC (1 << 2) /* late collision */
  113. #define TX_BD_RL (1 << 3) /* retransmission limit */
  114. #define TX_BD_RETRY_MASK (0x00f0)
  115. #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
  116. #define TX_BD_UR (1 << 8) /* transmitter underrun */
  117. #define TX_BD_CRC (1 << 11) /* TX CRC enable */
  118. #define TX_BD_PAD (1 << 12) /* pad enable */
  119. #define TX_BD_WRAP (1 << 13)
  120. #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
  121. #define TX_BD_READY (1 << 15) /* TX buffer ready */
  122. #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
  123. #define TX_BD_LEN_MASK (0xffff << 16)
  124. #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
  125. TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
  126. /* RX buffer descriptor */
  127. #define RX_BD_LC (1 << 0) /* late collision */
  128. #define RX_BD_CRC (1 << 1) /* RX CRC error */
  129. #define RX_BD_SF (1 << 2) /* short frame */
  130. #define RX_BD_TL (1 << 3) /* too long */
  131. #define RX_BD_DN (1 << 4) /* dribble nibble */
  132. #define RX_BD_IS (1 << 5) /* invalid symbol */
  133. #define RX_BD_OR (1 << 6) /* receiver overrun */
  134. #define RX_BD_MISS (1 << 7)
  135. #define RX_BD_CF (1 << 8) /* control frame */
  136. #define RX_BD_WRAP (1 << 13)
  137. #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
  138. #define RX_BD_EMPTY (1 << 15)
  139. #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
  140. #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
  141. RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
  142. #define ETHOC_BUFSIZ 1536
  143. #define ETHOC_ZLEN 64
  144. #define ETHOC_BD_BASE 0x400
  145. #define ETHOC_TIMEOUT (HZ / 2)
  146. #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
  147. #define ETHOC_IOSIZE 0x54
  148. /**
  149. * struct ethoc - driver-private device structure
  150. * @num_tx: number of send buffers
  151. * @cur_tx: last send buffer written
  152. * @dty_tx: last buffer actually sent
  153. * @num_rx: number of receive buffers
  154. * @cur_rx: current receive buffer
  155. */
  156. struct ethoc {
  157. u32 num_tx;
  158. u32 cur_tx;
  159. u32 dty_tx;
  160. u32 num_rx;
  161. u32 cur_rx;
  162. void __iomem *iobase;
  163. void __iomem *packet;
  164. phys_addr_t packet_phys;
  165. #ifdef CONFIG_PHYLIB
  166. struct mii_dev *bus;
  167. struct phy_device *phydev;
  168. #endif
  169. };
  170. /**
  171. * struct ethoc_bd - buffer descriptor
  172. * @stat: buffer statistics
  173. * @addr: physical memory address
  174. */
  175. struct ethoc_bd {
  176. u32 stat;
  177. u32 addr;
  178. };
  179. static inline u32 *ethoc_reg(struct ethoc *priv, size_t offset)
  180. {
  181. return priv->iobase + offset;
  182. }
  183. static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
  184. {
  185. return readl(ethoc_reg(priv, offset));
  186. }
  187. static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
  188. {
  189. writel(data, ethoc_reg(priv, offset));
  190. }
  191. static inline void ethoc_read_bd(struct ethoc *priv, int index,
  192. struct ethoc_bd *bd)
  193. {
  194. size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  195. bd->stat = ethoc_read(priv, offset + 0);
  196. bd->addr = ethoc_read(priv, offset + 4);
  197. }
  198. static inline void ethoc_write_bd(struct ethoc *priv, int index,
  199. const struct ethoc_bd *bd)
  200. {
  201. size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  202. ethoc_write(priv, offset + 0, bd->stat);
  203. ethoc_write(priv, offset + 4, bd->addr);
  204. }
  205. static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac)
  206. {
  207. ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
  208. (mac[4] << 8) | (mac[5] << 0));
  209. ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
  210. return 0;
  211. }
  212. static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
  213. {
  214. ethoc_write(priv, INT_SOURCE, mask);
  215. }
  216. static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
  217. {
  218. u32 mode = ethoc_read(priv, MODER);
  219. mode |= MODER_RXEN | MODER_TXEN;
  220. ethoc_write(priv, MODER, mode);
  221. }
  222. static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
  223. {
  224. u32 mode = ethoc_read(priv, MODER);
  225. mode &= ~(MODER_RXEN | MODER_TXEN);
  226. ethoc_write(priv, MODER, mode);
  227. }
  228. static int ethoc_init_ring(struct ethoc *priv)
  229. {
  230. struct ethoc_bd bd;
  231. phys_addr_t addr = priv->packet_phys;
  232. int i;
  233. priv->cur_tx = 0;
  234. priv->dty_tx = 0;
  235. priv->cur_rx = 0;
  236. /* setup transmission buffers */
  237. bd.stat = TX_BD_IRQ | TX_BD_CRC;
  238. bd.addr = 0;
  239. for (i = 0; i < priv->num_tx; i++) {
  240. if (addr) {
  241. bd.addr = addr;
  242. addr += PKTSIZE_ALIGN;
  243. }
  244. if (i == priv->num_tx - 1)
  245. bd.stat |= TX_BD_WRAP;
  246. ethoc_write_bd(priv, i, &bd);
  247. }
  248. bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
  249. for (i = 0; i < priv->num_rx; i++) {
  250. if (addr) {
  251. bd.addr = addr;
  252. addr += PKTSIZE_ALIGN;
  253. } else {
  254. bd.addr = virt_to_phys(net_rx_packets[i]);
  255. }
  256. if (i == priv->num_rx - 1)
  257. bd.stat |= RX_BD_WRAP;
  258. flush_dcache_range((ulong)net_rx_packets[i],
  259. (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
  260. ethoc_write_bd(priv, priv->num_tx + i, &bd);
  261. }
  262. return 0;
  263. }
  264. static int ethoc_reset(struct ethoc *priv)
  265. {
  266. u32 mode;
  267. /* TODO: reset controller? */
  268. ethoc_disable_rx_and_tx(priv);
  269. /* TODO: setup registers */
  270. /* enable FCS generation and automatic padding */
  271. mode = ethoc_read(priv, MODER);
  272. mode |= MODER_CRC | MODER_PAD;
  273. ethoc_write(priv, MODER, mode);
  274. /* set full-duplex mode */
  275. mode = ethoc_read(priv, MODER);
  276. mode |= MODER_FULLD;
  277. ethoc_write(priv, MODER, mode);
  278. ethoc_write(priv, IPGT, 0x15);
  279. ethoc_ack_irq(priv, INT_MASK_ALL);
  280. ethoc_enable_rx_and_tx(priv);
  281. return 0;
  282. }
  283. static int ethoc_init_common(struct ethoc *priv)
  284. {
  285. int ret = 0;
  286. priv->num_tx = 1;
  287. priv->num_rx = PKTBUFSRX;
  288. ethoc_write(priv, TX_BD_NUM, priv->num_tx);
  289. ethoc_init_ring(priv);
  290. ethoc_reset(priv);
  291. #ifdef CONFIG_PHYLIB
  292. ret = phy_startup(priv->phydev);
  293. if (ret) {
  294. printf("Could not initialize PHY %s\n",
  295. priv->phydev->dev->name);
  296. return ret;
  297. }
  298. #endif
  299. return ret;
  300. }
  301. static void ethoc_stop_common(struct ethoc *priv)
  302. {
  303. ethoc_disable_rx_and_tx(priv);
  304. #ifdef CONFIG_PHYLIB
  305. phy_shutdown(priv->phydev);
  306. #endif
  307. }
  308. static int ethoc_update_rx_stats(struct ethoc_bd *bd)
  309. {
  310. int ret = 0;
  311. if (bd->stat & RX_BD_TL) {
  312. debug("ETHOC: " "RX: frame too long\n");
  313. ret++;
  314. }
  315. if (bd->stat & RX_BD_SF) {
  316. debug("ETHOC: " "RX: frame too short\n");
  317. ret++;
  318. }
  319. if (bd->stat & RX_BD_DN)
  320. debug("ETHOC: " "RX: dribble nibble\n");
  321. if (bd->stat & RX_BD_CRC) {
  322. debug("ETHOC: " "RX: wrong CRC\n");
  323. ret++;
  324. }
  325. if (bd->stat & RX_BD_OR) {
  326. debug("ETHOC: " "RX: overrun\n");
  327. ret++;
  328. }
  329. if (bd->stat & RX_BD_LC) {
  330. debug("ETHOC: " "RX: late collision\n");
  331. ret++;
  332. }
  333. return ret;
  334. }
  335. static int ethoc_rx_common(struct ethoc *priv, uchar **packetp)
  336. {
  337. struct ethoc_bd bd;
  338. u32 i = priv->cur_rx % priv->num_rx;
  339. u32 entry = priv->num_tx + i;
  340. ethoc_read_bd(priv, entry, &bd);
  341. if (bd.stat & RX_BD_EMPTY)
  342. return -EAGAIN;
  343. debug("%s(): RX buffer %d, %x received\n",
  344. __func__, priv->cur_rx, bd.stat);
  345. if (ethoc_update_rx_stats(&bd) == 0) {
  346. int size = bd.stat >> 16;
  347. size -= 4; /* strip the CRC */
  348. if (priv->packet)
  349. *packetp = priv->packet + entry * PKTSIZE_ALIGN;
  350. else
  351. *packetp = net_rx_packets[i];
  352. return size;
  353. } else {
  354. return 0;
  355. }
  356. }
  357. static int ethoc_is_new_packet_received(struct ethoc *priv)
  358. {
  359. u32 pending;
  360. pending = ethoc_read(priv, INT_SOURCE);
  361. ethoc_ack_irq(priv, pending);
  362. if (pending & INT_MASK_BUSY)
  363. debug("%s(): packet dropped\n", __func__);
  364. if (pending & INT_MASK_RX) {
  365. debug("%s(): rx irq\n", __func__);
  366. return 1;
  367. }
  368. return 0;
  369. }
  370. static int ethoc_update_tx_stats(struct ethoc_bd *bd)
  371. {
  372. if (bd->stat & TX_BD_LC)
  373. debug("ETHOC: " "TX: late collision\n");
  374. if (bd->stat & TX_BD_RL)
  375. debug("ETHOC: " "TX: retransmit limit\n");
  376. if (bd->stat & TX_BD_UR)
  377. debug("ETHOC: " "TX: underrun\n");
  378. if (bd->stat & TX_BD_CS)
  379. debug("ETHOC: " "TX: carrier sense lost\n");
  380. return 0;
  381. }
  382. static void ethoc_tx(struct ethoc *priv)
  383. {
  384. u32 entry = priv->dty_tx % priv->num_tx;
  385. struct ethoc_bd bd;
  386. ethoc_read_bd(priv, entry, &bd);
  387. if ((bd.stat & TX_BD_READY) == 0)
  388. (void)ethoc_update_tx_stats(&bd);
  389. }
  390. static int ethoc_send_common(struct ethoc *priv, void *packet, int length)
  391. {
  392. struct ethoc_bd bd;
  393. u32 entry;
  394. u32 pending;
  395. int tmo;
  396. entry = priv->cur_tx % priv->num_tx;
  397. ethoc_read_bd(priv, entry, &bd);
  398. if (unlikely(length < ETHOC_ZLEN))
  399. bd.stat |= TX_BD_PAD;
  400. else
  401. bd.stat &= ~TX_BD_PAD;
  402. if (priv->packet) {
  403. void *p = priv->packet + entry * PKTSIZE_ALIGN;
  404. memcpy(p, packet, length);
  405. packet = p;
  406. } else {
  407. bd.addr = virt_to_phys(packet);
  408. }
  409. flush_dcache_range((ulong)packet, (ulong)packet + length);
  410. bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
  411. bd.stat |= TX_BD_LEN(length);
  412. ethoc_write_bd(priv, entry, &bd);
  413. /* start transmit */
  414. bd.stat |= TX_BD_READY;
  415. ethoc_write_bd(priv, entry, &bd);
  416. /* wait for transfer to succeed */
  417. tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
  418. while (1) {
  419. pending = ethoc_read(priv, INT_SOURCE);
  420. ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
  421. if (pending & INT_MASK_BUSY)
  422. debug("%s(): packet dropped\n", __func__);
  423. if (pending & INT_MASK_TX) {
  424. ethoc_tx(priv);
  425. break;
  426. }
  427. if (get_timer(0) >= tmo) {
  428. debug("%s(): timed out\n", __func__);
  429. return -1;
  430. }
  431. }
  432. debug("%s(): packet sent\n", __func__);
  433. return 0;
  434. }
  435. static int ethoc_free_pkt_common(struct ethoc *priv)
  436. {
  437. struct ethoc_bd bd;
  438. u32 i = priv->cur_rx % priv->num_rx;
  439. u32 entry = priv->num_tx + i;
  440. void *src;
  441. ethoc_read_bd(priv, entry, &bd);
  442. if (priv->packet)
  443. src = priv->packet + entry * PKTSIZE_ALIGN;
  444. else
  445. src = net_rx_packets[i];
  446. /* clear the buffer descriptor so it can be reused */
  447. flush_dcache_range((ulong)src,
  448. (ulong)src + PKTSIZE_ALIGN);
  449. bd.stat &= ~RX_BD_STATS;
  450. bd.stat |= RX_BD_EMPTY;
  451. ethoc_write_bd(priv, entry, &bd);
  452. priv->cur_rx++;
  453. return 0;
  454. }
  455. #ifdef CONFIG_PHYLIB
  456. static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  457. {
  458. struct ethoc *priv = bus->priv;
  459. int rc;
  460. ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
  461. ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
  462. rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
  463. MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
  464. if (rc == 0) {
  465. u32 data = ethoc_read(priv, MIIRX_DATA);
  466. /* reset MII command register */
  467. ethoc_write(priv, MIICOMMAND, 0);
  468. return data;
  469. }
  470. return rc;
  471. }
  472. static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  473. u16 val)
  474. {
  475. struct ethoc *priv = bus->priv;
  476. int rc;
  477. ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
  478. ethoc_write(priv, MIITX_DATA, val);
  479. ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
  480. rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
  481. MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
  482. if (rc == 0) {
  483. /* reset MII command register */
  484. ethoc_write(priv, MIICOMMAND, 0);
  485. }
  486. return rc;
  487. }
  488. static int ethoc_mdio_init(const char *name, struct ethoc *priv)
  489. {
  490. struct mii_dev *bus = mdio_alloc();
  491. int ret;
  492. if (!bus) {
  493. printf("Failed to allocate MDIO bus\n");
  494. return -ENOMEM;
  495. }
  496. bus->read = ethoc_mdio_read;
  497. bus->write = ethoc_mdio_write;
  498. snprintf(bus->name, sizeof(bus->name), "%s", name);
  499. bus->priv = priv;
  500. ret = mdio_register(bus);
  501. if (ret < 0)
  502. return ret;
  503. priv->bus = miiphy_get_dev_by_name(name);
  504. return 0;
  505. }
  506. static int ethoc_phy_init(struct ethoc *priv, void *dev)
  507. {
  508. struct phy_device *phydev;
  509. int mask = 0xffffffff;
  510. #ifdef CONFIG_PHY_ADDR
  511. mask = 1 << CONFIG_PHY_ADDR;
  512. #endif
  513. phydev = phy_find_by_mask(priv->bus, mask, PHY_INTERFACE_MODE_MII);
  514. if (!phydev)
  515. return -ENODEV;
  516. phy_connect_dev(phydev, dev);
  517. phydev->supported &= PHY_BASIC_FEATURES;
  518. phydev->advertising = phydev->supported;
  519. priv->phydev = phydev;
  520. phy_config(phydev);
  521. return 0;
  522. }
  523. #else
  524. static inline int ethoc_mdio_init(const char *name, struct ethoc *priv)
  525. {
  526. return 0;
  527. }
  528. static inline int ethoc_phy_init(struct ethoc *priv, void *dev)
  529. {
  530. return 0;
  531. }
  532. #endif
  533. #ifdef CONFIG_DM_ETH
  534. static int ethoc_write_hwaddr(struct udevice *dev)
  535. {
  536. struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
  537. struct ethoc *priv = dev_get_priv(dev);
  538. u8 *mac = pdata->eth_pdata.enetaddr;
  539. return ethoc_write_hwaddr_common(priv, mac);
  540. }
  541. static int ethoc_send(struct udevice *dev, void *packet, int length)
  542. {
  543. return ethoc_send_common(dev_get_priv(dev), packet, length);
  544. }
  545. static int ethoc_free_pkt(struct udevice *dev, uchar *packet, int length)
  546. {
  547. return ethoc_free_pkt_common(dev_get_priv(dev));
  548. }
  549. static int ethoc_recv(struct udevice *dev, int flags, uchar **packetp)
  550. {
  551. struct ethoc *priv = dev_get_priv(dev);
  552. if (flags & ETH_RECV_CHECK_DEVICE)
  553. if (!ethoc_is_new_packet_received(priv))
  554. return -EAGAIN;
  555. return ethoc_rx_common(priv, packetp);
  556. }
  557. static int ethoc_start(struct udevice *dev)
  558. {
  559. return ethoc_init_common(dev_get_priv(dev));
  560. }
  561. static void ethoc_stop(struct udevice *dev)
  562. {
  563. ethoc_stop_common(dev_get_priv(dev));
  564. }
  565. static int ethoc_ofdata_to_platdata(struct udevice *dev)
  566. {
  567. struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
  568. fdt_addr_t addr;
  569. pdata->eth_pdata.iobase = dev_read_addr(dev);
  570. addr = devfdt_get_addr_index(dev, 1);
  571. if (addr != FDT_ADDR_T_NONE)
  572. pdata->packet_base = addr;
  573. return 0;
  574. }
  575. static int ethoc_probe(struct udevice *dev)
  576. {
  577. struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
  578. struct ethoc *priv = dev_get_priv(dev);
  579. priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
  580. if (pdata->packet_base) {
  581. priv->packet_phys = pdata->packet_base;
  582. priv->packet = ioremap(pdata->packet_base,
  583. (1 + PKTBUFSRX) * PKTSIZE_ALIGN);
  584. }
  585. ethoc_mdio_init(dev->name, priv);
  586. ethoc_phy_init(priv, dev);
  587. return 0;
  588. }
  589. static int ethoc_remove(struct udevice *dev)
  590. {
  591. struct ethoc *priv = dev_get_priv(dev);
  592. #ifdef CONFIG_PHYLIB
  593. free(priv->phydev);
  594. mdio_unregister(priv->bus);
  595. mdio_free(priv->bus);
  596. #endif
  597. iounmap(priv->iobase);
  598. return 0;
  599. }
  600. static const struct eth_ops ethoc_ops = {
  601. .start = ethoc_start,
  602. .stop = ethoc_stop,
  603. .send = ethoc_send,
  604. .recv = ethoc_recv,
  605. .free_pkt = ethoc_free_pkt,
  606. .write_hwaddr = ethoc_write_hwaddr,
  607. };
  608. static const struct udevice_id ethoc_ids[] = {
  609. { .compatible = "opencores,ethoc" },
  610. { }
  611. };
  612. U_BOOT_DRIVER(ethoc) = {
  613. .name = "ethoc",
  614. .id = UCLASS_ETH,
  615. .of_match = ethoc_ids,
  616. .ofdata_to_platdata = ethoc_ofdata_to_platdata,
  617. .probe = ethoc_probe,
  618. .remove = ethoc_remove,
  619. .ops = &ethoc_ops,
  620. .priv_auto_alloc_size = sizeof(struct ethoc),
  621. .platdata_auto_alloc_size = sizeof(struct ethoc_eth_pdata),
  622. };
  623. #else
  624. static int ethoc_init(struct eth_device *dev, struct bd_info *bd)
  625. {
  626. struct ethoc *priv = (struct ethoc *)dev->priv;
  627. return ethoc_init_common(priv);
  628. }
  629. static int ethoc_write_hwaddr(struct eth_device *dev)
  630. {
  631. struct ethoc *priv = (struct ethoc *)dev->priv;
  632. u8 *mac = dev->enetaddr;
  633. return ethoc_write_hwaddr_common(priv, mac);
  634. }
  635. static int ethoc_send(struct eth_device *dev, void *packet, int length)
  636. {
  637. return ethoc_send_common(dev->priv, packet, length);
  638. }
  639. static void ethoc_halt(struct eth_device *dev)
  640. {
  641. ethoc_disable_rx_and_tx(dev->priv);
  642. }
  643. static int ethoc_recv(struct eth_device *dev)
  644. {
  645. struct ethoc *priv = (struct ethoc *)dev->priv;
  646. int count;
  647. if (!ethoc_is_new_packet_received(priv))
  648. return 0;
  649. for (count = 0; count < PKTBUFSRX; ++count) {
  650. uchar *packetp;
  651. int size = ethoc_rx_common(priv, &packetp);
  652. if (size < 0)
  653. break;
  654. if (size > 0)
  655. net_process_received_packet(packetp, size);
  656. ethoc_free_pkt_common(priv);
  657. }
  658. return 0;
  659. }
  660. int ethoc_initialize(u8 dev_num, int base_addr)
  661. {
  662. struct ethoc *priv;
  663. struct eth_device *dev;
  664. priv = malloc(sizeof(*priv));
  665. if (!priv)
  666. return 0;
  667. dev = malloc(sizeof(*dev));
  668. if (!dev) {
  669. free(priv);
  670. return 0;
  671. }
  672. memset(dev, 0, sizeof(*dev));
  673. dev->priv = priv;
  674. dev->iobase = base_addr;
  675. dev->init = ethoc_init;
  676. dev->halt = ethoc_halt;
  677. dev->send = ethoc_send;
  678. dev->recv = ethoc_recv;
  679. dev->write_hwaddr = ethoc_write_hwaddr;
  680. sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
  681. priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
  682. eth_register(dev);
  683. ethoc_mdio_init(dev->name, priv);
  684. ethoc_phy_init(priv, dev);
  685. return 1;
  686. }
  687. #endif