eepro100.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <cpu_func.h>
  9. #include <malloc.h>
  10. #include <miiphy.h>
  11. #include <net.h>
  12. #include <netdev.h>
  13. #include <pci.h>
  14. #include <linux/delay.h>
  15. /* Ethernet chip registers. */
  16. #define SCB_STATUS 0 /* Rx/Command Unit Status *Word* */
  17. #define SCB_INT_ACK_BYTE 1 /* Rx/Command Unit STAT/ACK byte */
  18. #define SCB_CMD 2 /* Rx/Command Unit Command *Word* */
  19. #define SCB_INTR_CTL_BYTE 3 /* Rx/Command Unit Intr.Control Byte */
  20. #define SCB_POINTER 4 /* General purpose pointer. */
  21. #define SCB_PORT 8 /* Misc. commands and operands. */
  22. #define SCB_FLASH 12 /* Flash memory control. */
  23. #define SCB_EEPROM 14 /* EEPROM memory control. */
  24. #define SCB_CTRL_MDI 16 /* MDI interface control. */
  25. #define SCB_EARLY_RX 20 /* Early receive byte count. */
  26. #define SCB_GEN_CONTROL 28 /* 82559 General Control Register */
  27. #define SCB_GEN_STATUS 29 /* 82559 General Status register */
  28. /* 82559 SCB status word defnitions */
  29. #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
  30. #define SCB_STATUS_FR 0x4000 /* frame received */
  31. #define SCB_STATUS_CNA 0x2000 /* CU left active state */
  32. #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
  33. #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
  34. #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
  35. #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
  36. #define SCB_INTACK_MASK 0xFD00 /* all the above */
  37. #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
  38. #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
  39. /* System control block commands */
  40. /* CU Commands */
  41. #define CU_NOP 0x0000
  42. #define CU_START 0x0010
  43. #define CU_RESUME 0x0020
  44. #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
  45. #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
  46. #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
  47. #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
  48. /* RUC Commands */
  49. #define RUC_NOP 0x0000
  50. #define RUC_START 0x0001
  51. #define RUC_RESUME 0x0002
  52. #define RUC_ABORT 0x0004
  53. #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
  54. #define RUC_RESUMENR 0x0007
  55. #define CU_CMD_MASK 0x00f0
  56. #define RU_CMD_MASK 0x0007
  57. #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
  58. #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
  59. #define CU_STATUS_MASK 0x00C0
  60. #define RU_STATUS_MASK 0x003C
  61. #define RU_STATUS_IDLE (0 << 2)
  62. #define RU_STATUS_SUS (1 << 2)
  63. #define RU_STATUS_NORES (2 << 2)
  64. #define RU_STATUS_READY (4 << 2)
  65. #define RU_STATUS_NO_RBDS_SUS ((1 << 2) | (8 << 2))
  66. #define RU_STATUS_NO_RBDS_NORES ((2 << 2) | (8 << 2))
  67. #define RU_STATUS_NO_RBDS_READY ((4 << 2) | (8 << 2))
  68. /* 82559 Port interface commands. */
  69. #define I82559_RESET 0x00000000 /* Software reset */
  70. #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
  71. #define I82559_SELECTIVE_RESET 0x00000002
  72. #define I82559_DUMP 0x00000003
  73. #define I82559_DUMP_WAKEUP 0x00000007
  74. /* 82559 Eeprom interface. */
  75. #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
  76. #define EE_CS 0x02 /* EEPROM chip select. */
  77. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  78. #define EE_WRITE_0 0x01
  79. #define EE_WRITE_1 0x05
  80. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  81. #define EE_ENB (0x4800 | EE_CS)
  82. #define EE_CMD_BITS 3
  83. #define EE_DATA_BITS 16
  84. /* The EEPROM commands include the alway-set leading bit. */
  85. #define EE_EWENB_CMD(addr_len) (4 << (addr_len))
  86. #define EE_WRITE_CMD(addr_len) (5 << (addr_len))
  87. #define EE_READ_CMD(addr_len) (6 << (addr_len))
  88. #define EE_ERASE_CMD(addr_len) (7 << (addr_len))
  89. /* Receive frame descriptors. */
  90. struct eepro100_rxfd {
  91. u16 status;
  92. u16 control;
  93. u32 link; /* struct eepro100_rxfd * */
  94. u32 rx_buf_addr; /* void * */
  95. u32 count;
  96. u8 data[PKTSIZE_ALIGN];
  97. };
  98. #define RFD_STATUS_C 0x8000 /* completion of received frame */
  99. #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
  100. #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
  101. #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
  102. #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
  103. #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
  104. #define RFD_COUNT_MASK 0x3fff
  105. #define RFD_COUNT_F 0x4000
  106. #define RFD_COUNT_EOF 0x8000
  107. #define RFD_RX_CRC 0x0800 /* crc error */
  108. #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
  109. #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
  110. #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
  111. #define RFD_RX_SHORT 0x0080 /* short frame error */
  112. #define RFD_RX_LENGTH 0x0020
  113. #define RFD_RX_ERROR 0x0010 /* receive error */
  114. #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
  115. #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
  116. #define RFD_RX_TCO 0x0001 /* TCO indication */
  117. /* Transmit frame descriptors */
  118. struct eepro100_txfd { /* Transmit frame descriptor set. */
  119. u16 status;
  120. u16 command;
  121. u32 link; /* void * */
  122. u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
  123. s32 count;
  124. u32 tx_buf_addr0; /* void *, frame to be transmitted. */
  125. s32 tx_buf_size0; /* Length of Tx frame. */
  126. u32 tx_buf_addr1; /* void *, frame to be transmitted. */
  127. s32 tx_buf_size1; /* Length of Tx frame. */
  128. };
  129. #define TXCB_CMD_TRANSMIT 0x0004 /* transmit command */
  130. #define TXCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
  131. #define TXCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
  132. #define TXCB_CMD_I 0x2000 /* generate interrupt on completion */
  133. #define TXCB_CMD_S 0x4000 /* suspend on completion */
  134. #define TXCB_CMD_EL 0x8000 /* last command block in CBL */
  135. #define TXCB_COUNT_MASK 0x3fff
  136. #define TXCB_COUNT_EOF 0x8000
  137. /* The Speedo3 Rx and Tx frame/buffer descriptors. */
  138. struct descriptor { /* A generic descriptor. */
  139. u16 status;
  140. u16 command;
  141. u32 link; /* struct descriptor * */
  142. unsigned char params[0];
  143. };
  144. #define CONFIG_SYS_CMD_EL 0x8000
  145. #define CONFIG_SYS_CMD_SUSPEND 0x4000
  146. #define CONFIG_SYS_CMD_INT 0x2000
  147. #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
  148. #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
  149. #define CONFIG_SYS_STATUS_C 0x8000
  150. #define CONFIG_SYS_STATUS_OK 0x2000
  151. /* Misc. */
  152. #define NUM_RX_DESC PKTBUFSRX
  153. #define NUM_TX_DESC 1 /* Number of TX descriptors */
  154. #define TOUT_LOOP 1000000
  155. /*
  156. * The parameters for a CmdConfigure operation.
  157. * There are so many options that it would be difficult to document
  158. * each bit. We mostly use the default or recommended settings.
  159. */
  160. static const char i82558_config_cmd[] = {
  161. 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
  162. 0, 0x2E, 0, 0x60, 0x08, 0x88,
  163. 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
  164. 0x31, 0x05,
  165. };
  166. struct eepro100_priv {
  167. /* RX descriptor ring */
  168. struct eepro100_rxfd rx_ring[NUM_RX_DESC];
  169. /* TX descriptor ring */
  170. struct eepro100_txfd tx_ring[NUM_TX_DESC];
  171. /* RX descriptor ring pointer */
  172. int rx_next;
  173. u16 rx_stat;
  174. /* TX descriptor ring pointer */
  175. int tx_next;
  176. int tx_threshold;
  177. #ifdef CONFIG_DM_ETH
  178. struct udevice *devno;
  179. #else
  180. struct eth_device dev;
  181. pci_dev_t devno;
  182. #endif
  183. char *name;
  184. void __iomem *iobase;
  185. u8 *enetaddr;
  186. };
  187. #if defined(CONFIG_DM_ETH)
  188. #define bus_to_phys(dev, a) dm_pci_mem_to_phys((dev), (a))
  189. #define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
  190. #elif defined(CONFIG_E500)
  191. #define bus_to_phys(dev, a) (a)
  192. #define phys_to_bus(dev, a) (a)
  193. #else
  194. #define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a))
  195. #define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
  196. #endif
  197. static int INW(struct eepro100_priv *priv, u_long addr)
  198. {
  199. return le16_to_cpu(readw(addr + priv->iobase));
  200. }
  201. static void OUTW(struct eepro100_priv *priv, int command, u_long addr)
  202. {
  203. writew(cpu_to_le16(command), addr + priv->iobase);
  204. }
  205. static void OUTL(struct eepro100_priv *priv, int command, u_long addr)
  206. {
  207. writel(cpu_to_le32(command), addr + priv->iobase);
  208. }
  209. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  210. static int INL(struct eepro100_priv *priv, u_long addr)
  211. {
  212. return le32_to_cpu(readl(addr + priv->iobase));
  213. }
  214. static int get_phyreg(struct eepro100_priv *priv, unsigned char addr,
  215. unsigned char reg, unsigned short *value)
  216. {
  217. int timeout = 50;
  218. int cmd;
  219. /* read requested data */
  220. cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
  221. OUTL(priv, cmd, SCB_CTRL_MDI);
  222. do {
  223. udelay(1000);
  224. cmd = INL(priv, SCB_CTRL_MDI);
  225. } while (!(cmd & (1 << 28)) && (--timeout));
  226. if (timeout == 0)
  227. return -1;
  228. *value = (unsigned short)(cmd & 0xffff);
  229. return 0;
  230. }
  231. static int set_phyreg(struct eepro100_priv *priv, unsigned char addr,
  232. unsigned char reg, unsigned short value)
  233. {
  234. int timeout = 50;
  235. int cmd;
  236. /* write requested data */
  237. cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
  238. OUTL(priv, cmd | value, SCB_CTRL_MDI);
  239. while (!(INL(priv, SCB_CTRL_MDI) & (1 << 28)) && (--timeout))
  240. udelay(1000);
  241. if (timeout == 0)
  242. return -1;
  243. return 0;
  244. }
  245. /*
  246. * Check if given phyaddr is valid, i.e. there is a PHY connected.
  247. * Do this by checking model value field from ID2 register.
  248. */
  249. static int verify_phyaddr(struct eepro100_priv *priv, unsigned char addr)
  250. {
  251. unsigned short value, model;
  252. int ret;
  253. /* read id2 register */
  254. ret = get_phyreg(priv, addr, MII_PHYSID2, &value);
  255. if (ret) {
  256. printf("%s: mii read timeout!\n", priv->name);
  257. return ret;
  258. }
  259. /* get model */
  260. model = (value >> 4) & 0x003f;
  261. if (!model) {
  262. printf("%s: no PHY at address %d\n", priv->name, addr);
  263. return -EINVAL;
  264. }
  265. return 0;
  266. }
  267. static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
  268. int reg)
  269. {
  270. struct eepro100_priv *priv = bus->priv;
  271. unsigned short value = 0;
  272. int ret;
  273. ret = verify_phyaddr(priv, addr);
  274. if (ret)
  275. return ret;
  276. ret = get_phyreg(priv, addr, reg, &value);
  277. if (ret) {
  278. printf("%s: mii read timeout!\n", bus->name);
  279. return ret;
  280. }
  281. return value;
  282. }
  283. static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
  284. int reg, u16 value)
  285. {
  286. struct eepro100_priv *priv = bus->priv;
  287. int ret;
  288. ret = verify_phyaddr(priv, addr);
  289. if (ret)
  290. return ret;
  291. ret = set_phyreg(priv, addr, reg, value);
  292. if (ret) {
  293. printf("%s: mii write timeout!\n", bus->name);
  294. return ret;
  295. }
  296. return 0;
  297. }
  298. #endif
  299. static void init_rx_ring(struct eepro100_priv *priv)
  300. {
  301. struct eepro100_rxfd *rx_ring = priv->rx_ring;
  302. int i;
  303. for (i = 0; i < NUM_RX_DESC; i++) {
  304. rx_ring[i].status = 0;
  305. rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
  306. cpu_to_le16 (RFD_CONTROL_S) : 0;
  307. rx_ring[i].link =
  308. cpu_to_le32(phys_to_bus(priv->devno,
  309. (u32)&rx_ring[(i + 1) %
  310. NUM_RX_DESC]));
  311. rx_ring[i].rx_buf_addr = 0xffffffff;
  312. rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
  313. }
  314. flush_dcache_range((unsigned long)rx_ring,
  315. (unsigned long)rx_ring +
  316. (sizeof(*rx_ring) * NUM_RX_DESC));
  317. priv->rx_next = 0;
  318. }
  319. static void purge_tx_ring(struct eepro100_priv *priv)
  320. {
  321. struct eepro100_txfd *tx_ring = priv->tx_ring;
  322. priv->tx_next = 0;
  323. priv->tx_threshold = 0x01208000;
  324. memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
  325. flush_dcache_range((unsigned long)tx_ring,
  326. (unsigned long)tx_ring +
  327. (sizeof(*tx_ring) * NUM_TX_DESC));
  328. }
  329. /* Wait for the chip get the command. */
  330. static int wait_for_eepro100(struct eepro100_priv *priv)
  331. {
  332. int i;
  333. for (i = 0; INW(priv, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
  334. if (i >= TOUT_LOOP)
  335. return 0;
  336. }
  337. return 1;
  338. }
  339. static int eepro100_txcmd_send(struct eepro100_priv *priv,
  340. struct eepro100_txfd *desc)
  341. {
  342. u16 rstat;
  343. int i = 0;
  344. flush_dcache_range((unsigned long)desc,
  345. (unsigned long)desc + sizeof(*desc));
  346. if (!wait_for_eepro100(priv))
  347. return -ETIMEDOUT;
  348. OUTL(priv, phys_to_bus(priv->devno, (u32)desc), SCB_POINTER);
  349. OUTW(priv, SCB_M | CU_START, SCB_CMD);
  350. while (true) {
  351. invalidate_dcache_range((unsigned long)desc,
  352. (unsigned long)desc + sizeof(*desc));
  353. rstat = le16_to_cpu(desc->status);
  354. if (rstat & CONFIG_SYS_STATUS_C)
  355. break;
  356. if (i++ >= TOUT_LOOP) {
  357. printf("%s: Tx error buffer not ready\n", priv->name);
  358. return -EINVAL;
  359. }
  360. }
  361. invalidate_dcache_range((unsigned long)desc,
  362. (unsigned long)desc + sizeof(*desc));
  363. rstat = le16_to_cpu(desc->status);
  364. if (!(rstat & CONFIG_SYS_STATUS_OK)) {
  365. printf("TX error status = 0x%08X\n", rstat);
  366. return -EIO;
  367. }
  368. return 0;
  369. }
  370. /* SROM Read. */
  371. static int read_eeprom(struct eepro100_priv *priv, int location, int addr_len)
  372. {
  373. unsigned short retval = 0;
  374. int read_cmd = location | EE_READ_CMD(addr_len);
  375. int i;
  376. OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
  377. OUTW(priv, EE_ENB, SCB_EEPROM);
  378. /* Shift the read command bits out. */
  379. for (i = 12; i >= 0; i--) {
  380. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  381. OUTW(priv, EE_ENB | dataval, SCB_EEPROM);
  382. udelay(1);
  383. OUTW(priv, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
  384. udelay(1);
  385. }
  386. OUTW(priv, EE_ENB, SCB_EEPROM);
  387. for (i = 15; i >= 0; i--) {
  388. OUTW(priv, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
  389. udelay(1);
  390. retval = (retval << 1) |
  391. !!(INW(priv, SCB_EEPROM) & EE_DATA_READ);
  392. OUTW(priv, EE_ENB, SCB_EEPROM);
  393. udelay(1);
  394. }
  395. /* Terminate the EEPROM access. */
  396. OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
  397. return retval;
  398. }
  399. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  400. static int eepro100_initialize_mii(struct eepro100_priv *priv)
  401. {
  402. /* register mii command access routines */
  403. struct mii_dev *mdiodev;
  404. int ret;
  405. mdiodev = mdio_alloc();
  406. if (!mdiodev)
  407. return -ENOMEM;
  408. strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
  409. mdiodev->read = eepro100_miiphy_read;
  410. mdiodev->write = eepro100_miiphy_write;
  411. mdiodev->priv = priv;
  412. ret = mdio_register(mdiodev);
  413. if (ret < 0) {
  414. mdio_free(mdiodev);
  415. return ret;
  416. }
  417. return 0;
  418. }
  419. #else
  420. static int eepro100_initialize_mii(struct eepro100_priv *priv)
  421. {
  422. return 0;
  423. }
  424. #endif
  425. static struct pci_device_id supported[] = {
  426. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557) },
  427. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559) },
  428. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER) },
  429. { }
  430. };
  431. static void eepro100_get_hwaddr(struct eepro100_priv *priv)
  432. {
  433. u16 sum = 0;
  434. int i, j;
  435. int addr_len = read_eeprom(priv, 0, 6) == 0xffff ? 8 : 6;
  436. for (j = 0, i = 0; i < 0x40; i++) {
  437. u16 value = read_eeprom(priv, i, addr_len);
  438. sum += value;
  439. if (i < 3) {
  440. priv->enetaddr[j++] = value;
  441. priv->enetaddr[j++] = value >> 8;
  442. }
  443. }
  444. if (sum != 0xBABA) {
  445. memset(priv->enetaddr, 0, ETH_ALEN);
  446. debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
  447. priv->name, sum);
  448. }
  449. }
  450. static int eepro100_init_common(struct eepro100_priv *priv)
  451. {
  452. struct eepro100_rxfd *rx_ring = priv->rx_ring;
  453. struct eepro100_txfd *tx_ring = priv->tx_ring;
  454. struct eepro100_txfd *ias_cmd, *cfg_cmd;
  455. int ret, status = -1;
  456. int tx_cur;
  457. /* Reset the ethernet controller */
  458. OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
  459. udelay(20);
  460. OUTL(priv, I82559_RESET, SCB_PORT);
  461. udelay(20);
  462. if (!wait_for_eepro100(priv)) {
  463. printf("Error: Can not reset ethernet controller.\n");
  464. goto done;
  465. }
  466. OUTL(priv, 0, SCB_POINTER);
  467. OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
  468. if (!wait_for_eepro100(priv)) {
  469. printf("Error: Can not reset ethernet controller.\n");
  470. goto done;
  471. }
  472. OUTL(priv, 0, SCB_POINTER);
  473. OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
  474. /* Initialize Rx and Tx rings. */
  475. init_rx_ring(priv);
  476. purge_tx_ring(priv);
  477. /* Tell the adapter where the RX ring is located. */
  478. if (!wait_for_eepro100(priv)) {
  479. printf("Error: Can not reset ethernet controller.\n");
  480. goto done;
  481. }
  482. /* RX ring cache was already flushed in init_rx_ring() */
  483. OUTL(priv, phys_to_bus(priv->devno, (u32)&rx_ring[priv->rx_next]),
  484. SCB_POINTER);
  485. OUTW(priv, SCB_M | RUC_START, SCB_CMD);
  486. /* Send the Configure frame */
  487. tx_cur = priv->tx_next;
  488. priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
  489. cfg_cmd = &tx_ring[tx_cur];
  490. cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
  491. CONFIG_SYS_CMD_CONFIGURE);
  492. cfg_cmd->status = 0;
  493. cfg_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
  494. (u32)&tx_ring[priv->tx_next]));
  495. memcpy(((struct descriptor *)cfg_cmd)->params, i82558_config_cmd,
  496. sizeof(i82558_config_cmd));
  497. ret = eepro100_txcmd_send(priv, cfg_cmd);
  498. if (ret) {
  499. if (ret == -ETIMEDOUT)
  500. printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
  501. goto done;
  502. }
  503. /* Send the Individual Address Setup frame */
  504. tx_cur = priv->tx_next;
  505. priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
  506. ias_cmd = &tx_ring[tx_cur];
  507. ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
  508. CONFIG_SYS_CMD_IAS);
  509. ias_cmd->status = 0;
  510. ias_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
  511. (u32)&tx_ring[priv->tx_next]));
  512. memcpy(((struct descriptor *)ias_cmd)->params, priv->enetaddr, 6);
  513. ret = eepro100_txcmd_send(priv, ias_cmd);
  514. if (ret) {
  515. if (ret == -ETIMEDOUT)
  516. printf("Error: Can not reset ethernet controller.\n");
  517. goto done;
  518. }
  519. status = 0;
  520. done:
  521. return status;
  522. }
  523. static int eepro100_send_common(struct eepro100_priv *priv,
  524. void *packet, int length)
  525. {
  526. struct eepro100_txfd *tx_ring = priv->tx_ring;
  527. struct eepro100_txfd *desc;
  528. int ret, status = -1;
  529. int tx_cur;
  530. if (length <= 0) {
  531. printf("%s: bad packet size: %d\n", priv->name, length);
  532. goto done;
  533. }
  534. tx_cur = priv->tx_next;
  535. priv->tx_next = (priv->tx_next + 1) % NUM_TX_DESC;
  536. desc = &tx_ring[tx_cur];
  537. desc->command = cpu_to_le16(TXCB_CMD_TRANSMIT | TXCB_CMD_SF |
  538. TXCB_CMD_S | TXCB_CMD_EL);
  539. desc->status = 0;
  540. desc->count = cpu_to_le32(priv->tx_threshold);
  541. desc->link = cpu_to_le32(phys_to_bus(priv->devno,
  542. (u32)&tx_ring[priv->tx_next]));
  543. desc->tx_desc_addr = cpu_to_le32(phys_to_bus(priv->devno,
  544. (u32)&desc->tx_buf_addr0));
  545. desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus(priv->devno,
  546. (u_long)packet));
  547. desc->tx_buf_size0 = cpu_to_le32(length);
  548. ret = eepro100_txcmd_send(priv, &tx_ring[tx_cur]);
  549. if (ret) {
  550. if (ret == -ETIMEDOUT)
  551. printf("%s: Tx error ethernet controller not ready.\n",
  552. priv->name);
  553. goto done;
  554. }
  555. status = length;
  556. done:
  557. return status;
  558. }
  559. static int eepro100_recv_common(struct eepro100_priv *priv, uchar **packetp)
  560. {
  561. struct eepro100_rxfd *rx_ring = priv->rx_ring;
  562. struct eepro100_rxfd *desc;
  563. int length;
  564. u16 status;
  565. priv->rx_stat = INW(priv, SCB_STATUS);
  566. OUTW(priv, priv->rx_stat & SCB_STATUS_RNR, SCB_STATUS);
  567. desc = &rx_ring[priv->rx_next];
  568. invalidate_dcache_range((unsigned long)desc,
  569. (unsigned long)desc + sizeof(*desc));
  570. status = le16_to_cpu(desc->status);
  571. if (!(status & RFD_STATUS_C))
  572. return 0;
  573. /* Valid frame status. */
  574. if (status & RFD_STATUS_OK) {
  575. /* A valid frame received. */
  576. length = le32_to_cpu(desc->count) & 0x3fff;
  577. /* Pass the packet up to the protocol layers. */
  578. *packetp = desc->data;
  579. return length;
  580. }
  581. /* There was an error. */
  582. printf("RX error status = 0x%08X\n", status);
  583. return -EINVAL;
  584. }
  585. static void eepro100_free_pkt_common(struct eepro100_priv *priv)
  586. {
  587. struct eepro100_rxfd *rx_ring = priv->rx_ring;
  588. struct eepro100_rxfd *desc;
  589. int rx_prev;
  590. desc = &rx_ring[priv->rx_next];
  591. desc->control = cpu_to_le16(RFD_CONTROL_S);
  592. desc->status = 0;
  593. desc->count = cpu_to_le32(PKTSIZE_ALIGN << 16);
  594. flush_dcache_range((unsigned long)desc,
  595. (unsigned long)desc + sizeof(*desc));
  596. rx_prev = (priv->rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
  597. desc = &rx_ring[rx_prev];
  598. desc->control = 0;
  599. flush_dcache_range((unsigned long)desc,
  600. (unsigned long)desc + sizeof(*desc));
  601. /* Update entry information. */
  602. priv->rx_next = (priv->rx_next + 1) % NUM_RX_DESC;
  603. if (!(priv->rx_stat & SCB_STATUS_RNR))
  604. return;
  605. printf("%s: Receiver is not ready, restart it !\n", priv->name);
  606. /* Reinitialize Rx ring. */
  607. init_rx_ring(priv);
  608. if (!wait_for_eepro100(priv)) {
  609. printf("Error: Can not restart ethernet controller.\n");
  610. return;
  611. }
  612. /* RX ring cache was already flushed in init_rx_ring() */
  613. OUTL(priv, phys_to_bus(priv->devno, (u32)&rx_ring[priv->rx_next]),
  614. SCB_POINTER);
  615. OUTW(priv, SCB_M | RUC_START, SCB_CMD);
  616. }
  617. static void eepro100_halt_common(struct eepro100_priv *priv)
  618. {
  619. /* Reset the ethernet controller */
  620. OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
  621. udelay(20);
  622. OUTL(priv, I82559_RESET, SCB_PORT);
  623. udelay(20);
  624. if (!wait_for_eepro100(priv)) {
  625. printf("Error: Can not reset ethernet controller.\n");
  626. goto done;
  627. }
  628. OUTL(priv, 0, SCB_POINTER);
  629. OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
  630. if (!wait_for_eepro100(priv)) {
  631. printf("Error: Can not reset ethernet controller.\n");
  632. goto done;
  633. }
  634. OUTL(priv, 0, SCB_POINTER);
  635. OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
  636. done:
  637. return;
  638. }
  639. #ifndef CONFIG_DM_ETH
  640. static int eepro100_init(struct eth_device *dev, struct bd_info *bis)
  641. {
  642. struct eepro100_priv *priv =
  643. container_of(dev, struct eepro100_priv, dev);
  644. return eepro100_init_common(priv);
  645. }
  646. static void eepro100_halt(struct eth_device *dev)
  647. {
  648. struct eepro100_priv *priv =
  649. container_of(dev, struct eepro100_priv, dev);
  650. eepro100_halt_common(priv);
  651. }
  652. static int eepro100_send(struct eth_device *dev, void *packet, int length)
  653. {
  654. struct eepro100_priv *priv =
  655. container_of(dev, struct eepro100_priv, dev);
  656. return eepro100_send_common(priv, packet, length);
  657. }
  658. static int eepro100_recv(struct eth_device *dev)
  659. {
  660. struct eepro100_priv *priv =
  661. container_of(dev, struct eepro100_priv, dev);
  662. uchar *packet;
  663. int ret;
  664. ret = eepro100_recv_common(priv, &packet);
  665. if (ret > 0)
  666. net_process_received_packet(packet, ret);
  667. if (ret)
  668. eepro100_free_pkt_common(priv);
  669. return ret;
  670. }
  671. int eepro100_initialize(struct bd_info *bis)
  672. {
  673. struct eepro100_priv *priv;
  674. struct eth_device *dev;
  675. int card_number = 0;
  676. u32 iobase, status;
  677. pci_dev_t devno;
  678. int idx = 0;
  679. int ret;
  680. while (1) {
  681. /* Find PCI device */
  682. devno = pci_find_devices(supported, idx++);
  683. if (devno < 0)
  684. break;
  685. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
  686. iobase &= ~0xf;
  687. debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
  688. iobase);
  689. pci_write_config_dword(devno, PCI_COMMAND,
  690. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  691. /* Check if I/O accesses and Bus Mastering are enabled. */
  692. pci_read_config_dword(devno, PCI_COMMAND, &status);
  693. if (!(status & PCI_COMMAND_MEMORY)) {
  694. printf("Error: Can not enable MEM access.\n");
  695. continue;
  696. }
  697. if (!(status & PCI_COMMAND_MASTER)) {
  698. printf("Error: Can not enable Bus Mastering.\n");
  699. continue;
  700. }
  701. priv = calloc(1, sizeof(*priv));
  702. if (!priv) {
  703. printf("eepro100: Can not allocate memory\n");
  704. break;
  705. }
  706. dev = &priv->dev;
  707. sprintf(dev->name, "i82559#%d", card_number);
  708. priv->name = dev->name;
  709. /* this have to come before bus_to_phys() */
  710. priv->devno = devno;
  711. priv->iobase = (void __iomem *)bus_to_phys(devno, iobase);
  712. priv->enetaddr = dev->enetaddr;
  713. dev->init = eepro100_init;
  714. dev->halt = eepro100_halt;
  715. dev->send = eepro100_send;
  716. dev->recv = eepro100_recv;
  717. eth_register(dev);
  718. ret = eepro100_initialize_mii(priv);
  719. if (ret) {
  720. eth_unregister(dev);
  721. free(priv);
  722. return ret;
  723. }
  724. card_number++;
  725. /* Set the latency timer for value. */
  726. pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
  727. udelay(10 * 1000);
  728. eepro100_get_hwaddr(priv);
  729. }
  730. return card_number;
  731. }
  732. #else /* DM_ETH */
  733. static int eepro100_start(struct udevice *dev)
  734. {
  735. struct eth_pdata *plat = dev_get_platdata(dev);
  736. struct eepro100_priv *priv = dev_get_priv(dev);
  737. memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
  738. return eepro100_init_common(priv);
  739. }
  740. static void eepro100_stop(struct udevice *dev)
  741. {
  742. struct eepro100_priv *priv = dev_get_priv(dev);
  743. eepro100_halt_common(priv);
  744. }
  745. static int eepro100_send(struct udevice *dev, void *packet, int length)
  746. {
  747. struct eepro100_priv *priv = dev_get_priv(dev);
  748. int ret;
  749. ret = eepro100_send_common(priv, packet, length);
  750. return ret ? 0 : -ETIMEDOUT;
  751. }
  752. static int eepro100_recv(struct udevice *dev, int flags, uchar **packetp)
  753. {
  754. struct eepro100_priv *priv = dev_get_priv(dev);
  755. return eepro100_recv_common(priv, packetp);
  756. }
  757. static int eepro100_free_pkt(struct udevice *dev, uchar *packet, int length)
  758. {
  759. struct eepro100_priv *priv = dev_get_priv(dev);
  760. eepro100_free_pkt_common(priv);
  761. return 0;
  762. }
  763. static int eepro100_read_rom_hwaddr(struct udevice *dev)
  764. {
  765. struct eepro100_priv *priv = dev_get_priv(dev);
  766. eepro100_get_hwaddr(priv);
  767. return 0;
  768. }
  769. static int eepro100_bind(struct udevice *dev)
  770. {
  771. static int card_number;
  772. char name[16];
  773. sprintf(name, "eepro100#%u", card_number++);
  774. return device_set_name(dev, name);
  775. }
  776. static int eepro100_probe(struct udevice *dev)
  777. {
  778. struct eth_pdata *plat = dev_get_platdata(dev);
  779. struct eepro100_priv *priv = dev_get_priv(dev);
  780. u16 command, status;
  781. u32 iobase;
  782. int ret;
  783. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
  784. iobase &= ~0xf;
  785. debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", iobase);
  786. priv->devno = dev;
  787. priv->enetaddr = plat->enetaddr;
  788. priv->iobase = (void __iomem *)bus_to_phys(dev, iobase);
  789. command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  790. dm_pci_write_config16(dev, PCI_COMMAND, command);
  791. dm_pci_read_config16(dev, PCI_COMMAND, &status);
  792. if ((status & command) != command) {
  793. printf("eepro100: Couldn't enable IO access or Bus Mastering\n");
  794. return -EINVAL;
  795. }
  796. ret = eepro100_initialize_mii(priv);
  797. if (ret)
  798. return ret;
  799. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
  800. return 0;
  801. }
  802. static const struct eth_ops eepro100_ops = {
  803. .start = eepro100_start,
  804. .send = eepro100_send,
  805. .recv = eepro100_recv,
  806. .stop = eepro100_stop,
  807. .free_pkt = eepro100_free_pkt,
  808. .read_rom_hwaddr = eepro100_read_rom_hwaddr,
  809. };
  810. U_BOOT_DRIVER(eth_eepro100) = {
  811. .name = "eth_eepro100",
  812. .id = UCLASS_ETH,
  813. .bind = eepro100_bind,
  814. .probe = eepro100_probe,
  815. .ops = &eepro100_ops,
  816. .priv_auto_alloc_size = sizeof(struct eepro100_priv),
  817. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  818. };
  819. U_BOOT_PCI_DEVICE(eth_eepro100, supported);
  820. #endif