e1000.h 107 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*******************************************************************************
  3. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  4. Copyright 2011 Freescale Semiconductor, Inc.
  5. Contact Information:
  6. Linux NICS <linux.nics@intel.com>
  7. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  8. *******************************************************************************/
  9. /* e1000_hw.h
  10. * Structures, enums, and macros for the MAC
  11. */
  12. #ifndef _E1000_HW_H_
  13. #define _E1000_HW_H_
  14. #include <linux/list.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. /* Avoids a compile error since struct eth_device is not defined */
  18. #ifndef CONFIG_DM_ETH
  19. #include <netdev.h>
  20. #endif
  21. #include <asm/io.h>
  22. #include <pci.h>
  23. #ifdef CONFIG_E1000_SPI
  24. #include <spi.h>
  25. #endif
  26. #define E1000_ERR(NIC, fmt, args...) \
  27. printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
  28. #ifdef E1000_DEBUG
  29. #define E1000_DBG(NIC, fmt, args...) \
  30. printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
  31. #define DEBUGOUT(fmt, args...) printf(fmt ,##args)
  32. #define DEBUGFUNC() printf("%s\n", __func__);
  33. #else
  34. #define E1000_DBG(HW, args...) do { } while (0)
  35. #define DEBUGFUNC() do { } while (0)
  36. #define DEBUGOUT(fmt, args...) do { } while (0)
  37. #endif
  38. /* I/O wrapper functions */
  39. #define E1000_WRITE_REG(a, reg, value) \
  40. writel((value), ((a)->hw_addr + E1000_##reg))
  41. #define E1000_READ_REG(a, reg) \
  42. readl((a)->hw_addr + E1000_##reg)
  43. #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
  44. writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
  45. #define E1000_READ_REG_ARRAY(a, reg, offset) \
  46. readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
  47. #define E1000_WRITE_FLUSH(a) \
  48. do { E1000_READ_REG(a, STATUS); } while (0)
  49. /* Forward declarations of structures used by the shared code */
  50. struct e1000_hw;
  51. struct e1000_hw_stats;
  52. /* Internal E1000 helper functions */
  53. struct e1000_hw *e1000_find_card(unsigned int cardnum);
  54. #ifndef CONFIG_E1000_NO_NVM
  55. int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
  56. void e1000_standby_eeprom(struct e1000_hw *hw);
  57. void e1000_release_eeprom(struct e1000_hw *hw);
  58. void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
  59. void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
  60. #endif
  61. #ifdef CONFIG_E1000_SPI
  62. int do_e1000_spi(struct cmd_tbl *cmdtp, struct e1000_hw *hw,
  63. int argc, char *const argv[]);
  64. #endif
  65. /* Enumerated types specific to the e1000 hardware */
  66. /* Media Access Controlers */
  67. typedef enum {
  68. e1000_undefined = 0,
  69. e1000_82542_rev2_0,
  70. e1000_82542_rev2_1,
  71. e1000_82543,
  72. e1000_82544,
  73. e1000_82540,
  74. e1000_82545,
  75. e1000_82545_rev_3,
  76. e1000_82546,
  77. e1000_82546_rev_3,
  78. e1000_82541,
  79. e1000_82541_rev_2,
  80. e1000_82547,
  81. e1000_82547_rev_2,
  82. e1000_82571,
  83. e1000_82572,
  84. e1000_82573,
  85. e1000_82574,
  86. e1000_80003es2lan,
  87. e1000_ich8lan,
  88. e1000_igb,
  89. e1000_num_macs
  90. } e1000_mac_type;
  91. /* Media Types */
  92. typedef enum {
  93. e1000_media_type_copper = 0,
  94. e1000_media_type_fiber = 1,
  95. e1000_media_type_internal_serdes = 2,
  96. e1000_num_media_types
  97. } e1000_media_type;
  98. typedef enum {
  99. e1000_eeprom_uninitialized = 0,
  100. e1000_eeprom_spi,
  101. e1000_eeprom_microwire,
  102. e1000_eeprom_flash,
  103. e1000_eeprom_ich8,
  104. e1000_eeprom_none, /* No NVM support */
  105. e1000_eeprom_invm,
  106. e1000_num_eeprom_types
  107. } e1000_eeprom_type;
  108. typedef enum {
  109. e1000_10_half = 0,
  110. e1000_10_full = 1,
  111. e1000_100_half = 2,
  112. e1000_100_full = 3
  113. } e1000_speed_duplex_type;
  114. /* Flow Control Settings */
  115. typedef enum {
  116. e1000_fc_none = 0,
  117. e1000_fc_rx_pause = 1,
  118. e1000_fc_tx_pause = 2,
  119. e1000_fc_full = 3,
  120. e1000_fc_default = 0xFF
  121. } e1000_fc_type;
  122. /* PCI bus types */
  123. typedef enum {
  124. e1000_bus_type_unknown = 0,
  125. e1000_bus_type_pci,
  126. e1000_bus_type_pcix,
  127. e1000_bus_type_pci_express,
  128. e1000_bus_type_reserved
  129. } e1000_bus_type;
  130. /* PCI bus speeds */
  131. typedef enum {
  132. e1000_bus_speed_unknown = 0,
  133. e1000_bus_speed_33,
  134. e1000_bus_speed_66,
  135. e1000_bus_speed_100,
  136. e1000_bus_speed_133,
  137. e1000_bus_speed_reserved
  138. } e1000_bus_speed;
  139. /* PCI bus widths */
  140. typedef enum {
  141. e1000_bus_width_unknown = 0,
  142. e1000_bus_width_32,
  143. e1000_bus_width_64
  144. } e1000_bus_width;
  145. /* PHY status info structure and supporting enums */
  146. typedef enum {
  147. e1000_cable_length_50 = 0,
  148. e1000_cable_length_50_80,
  149. e1000_cable_length_80_110,
  150. e1000_cable_length_110_140,
  151. e1000_cable_length_140,
  152. e1000_cable_length_undefined = 0xFF
  153. } e1000_cable_length;
  154. typedef enum {
  155. e1000_10bt_ext_dist_enable_normal = 0,
  156. e1000_10bt_ext_dist_enable_lower,
  157. e1000_10bt_ext_dist_enable_undefined = 0xFF
  158. } e1000_10bt_ext_dist_enable;
  159. typedef enum {
  160. e1000_rev_polarity_normal = 0,
  161. e1000_rev_polarity_reversed,
  162. e1000_rev_polarity_undefined = 0xFF
  163. } e1000_rev_polarity;
  164. typedef enum {
  165. e1000_polarity_reversal_enabled = 0,
  166. e1000_polarity_reversal_disabled,
  167. e1000_polarity_reversal_undefined = 0xFF
  168. } e1000_polarity_reversal;
  169. typedef enum {
  170. e1000_auto_x_mode_manual_mdi = 0,
  171. e1000_auto_x_mode_manual_mdix,
  172. e1000_auto_x_mode_auto1,
  173. e1000_auto_x_mode_auto2,
  174. e1000_auto_x_mode_undefined = 0xFF
  175. } e1000_auto_x_mode;
  176. typedef enum {
  177. e1000_1000t_rx_status_not_ok = 0,
  178. e1000_1000t_rx_status_ok,
  179. e1000_1000t_rx_status_undefined = 0xFF
  180. } e1000_1000t_rx_status;
  181. typedef enum {
  182. e1000_phy_m88 = 0,
  183. e1000_phy_igp,
  184. e1000_phy_igp_2,
  185. e1000_phy_gg82563,
  186. e1000_phy_igp_3,
  187. e1000_phy_ife,
  188. e1000_phy_igb,
  189. e1000_phy_bm,
  190. e1000_phy_undefined = 0xFF
  191. } e1000_phy_type;
  192. struct e1000_phy_info {
  193. e1000_cable_length cable_length;
  194. e1000_10bt_ext_dist_enable extended_10bt_distance;
  195. e1000_rev_polarity cable_polarity;
  196. e1000_polarity_reversal polarity_correction;
  197. e1000_auto_x_mode mdix_mode;
  198. e1000_1000t_rx_status local_rx;
  199. e1000_1000t_rx_status remote_rx;
  200. };
  201. struct e1000_phy_stats {
  202. uint32_t idle_errors;
  203. uint32_t receive_errors;
  204. };
  205. /* Error Codes */
  206. #define E1000_SUCCESS 0
  207. #define E1000_ERR_EEPROM 1
  208. #define E1000_ERR_PHY 2
  209. #define E1000_ERR_CONFIG 3
  210. #define E1000_ERR_PARAM 4
  211. #define E1000_ERR_MAC_TYPE 5
  212. #define E1000_ERR_PHY_TYPE 6
  213. #define E1000_ERR_NOLINK 7
  214. #define E1000_ERR_TIMEOUT 8
  215. #define E1000_ERR_RESET 9
  216. #define E1000_ERR_MASTER_REQUESTS_PENDING 10
  217. #define E1000_ERR_HOST_INTERFACE_COMMAND 11
  218. #define E1000_BLK_PHY_RESET 12
  219. #define E1000_ERR_SWFW_SYNC 13
  220. /* PCI Device IDs */
  221. #define E1000_DEV_ID_82542 0x1000
  222. #define E1000_DEV_ID_82543GC_FIBER 0x1001
  223. #define E1000_DEV_ID_82543GC_COPPER 0x1004
  224. #define E1000_DEV_ID_82544EI_COPPER 0x1008
  225. #define E1000_DEV_ID_82544EI_FIBER 0x1009
  226. #define E1000_DEV_ID_82544GC_COPPER 0x100C
  227. #define E1000_DEV_ID_82544GC_LOM 0x100D
  228. #define E1000_DEV_ID_82540EM 0x100E
  229. #define E1000_DEV_ID_82540EM_LOM 0x1015
  230. #define E1000_DEV_ID_82540EP_LOM 0x1016
  231. #define E1000_DEV_ID_82540EP 0x1017
  232. #define E1000_DEV_ID_82540EP_LP 0x101E
  233. #define E1000_DEV_ID_82545EM_COPPER 0x100F
  234. #define E1000_DEV_ID_82545EM_FIBER 0x1011
  235. #define E1000_DEV_ID_82545GM_COPPER 0x1026
  236. #define E1000_DEV_ID_82545GM_FIBER 0x1027
  237. #define E1000_DEV_ID_82545GM_SERDES 0x1028
  238. #define E1000_DEV_ID_82546EB_COPPER 0x1010
  239. #define E1000_DEV_ID_82546EB_FIBER 0x1012
  240. #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
  241. #define E1000_DEV_ID_82541EI 0x1013
  242. #define E1000_DEV_ID_82541EI_MOBILE 0x1018
  243. #define E1000_DEV_ID_82541ER_LOM 0x1014
  244. #define E1000_DEV_ID_82541ER 0x1078
  245. #define E1000_DEV_ID_82547GI 0x1075
  246. #define E1000_DEV_ID_82541GI 0x1076
  247. #define E1000_DEV_ID_82541GI_MOBILE 0x1077
  248. #define E1000_DEV_ID_82541GI_LF 0x107C
  249. #define E1000_DEV_ID_82546GB_COPPER 0x1079
  250. #define E1000_DEV_ID_82546GB_FIBER 0x107A
  251. #define E1000_DEV_ID_82546GB_SERDES 0x107B
  252. #define E1000_DEV_ID_82546GB_PCIE 0x108A
  253. #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
  254. #define E1000_DEV_ID_82547EI 0x1019
  255. #define E1000_DEV_ID_82547EI_MOBILE 0x101A
  256. #define E1000_DEV_ID_82571EB_COPPER 0x105E
  257. #define E1000_DEV_ID_82571EB_FIBER 0x105F
  258. #define E1000_DEV_ID_82571EB_SERDES 0x1060
  259. #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
  260. #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
  261. #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
  262. #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
  263. #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
  264. #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
  265. #define E1000_DEV_ID_82572EI_COPPER 0x107D
  266. #define E1000_DEV_ID_82572EI_FIBER 0x107E
  267. #define E1000_DEV_ID_82572EI_SERDES 0x107F
  268. #define E1000_DEV_ID_82572EI 0x10B9
  269. #define E1000_DEV_ID_82573E 0x108B
  270. #define E1000_DEV_ID_82573E_IAMT 0x108C
  271. #define E1000_DEV_ID_82573L 0x109A
  272. #define E1000_DEV_ID_82574L 0x10D3
  273. #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
  274. #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
  275. #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
  276. #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
  277. #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
  278. #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
  279. #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
  280. #define E1000_DEV_ID_ICH8_IGP_C 0x104B
  281. #define E1000_DEV_ID_ICH8_IFE 0x104C
  282. #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
  283. #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
  284. #define E1000_DEV_ID_ICH8_IGP_M 0x104D
  285. #define IGP03E1000_E_PHY_ID 0x02A80390
  286. #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
  287. #define IFE_PLUS_E_PHY_ID 0x02A80320
  288. #define IFE_C_E_PHY_ID 0x02A80310
  289. #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status,
  290. Control and Address */
  291. #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
  292. control register */
  293. #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false
  294. Carrier Counter */
  295. #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet
  296. Counter */
  297. #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error
  298. Frame Counter */
  299. #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error
  300. Counter */
  301. #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive
  302. Premature End Of Frame
  303. Error Counter */
  304. #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of
  305. Frame Error Counter */
  306. #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber
  307. Detect Counter */
  308. #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and
  309. Status */
  310. #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and
  311. LED configuration */
  312. #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
  313. #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control
  314. (HWI) */
  315. #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto
  316. reduced power down */
  317. #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power
  318. state of 100BASE-TX */
  319. #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power
  320. state of 10BASE-T */
  321. #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T
  322. polarity */
  323. #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY
  324. address */
  325. #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed
  326. result 1=100Mbs, 0=10Mbs */
  327. #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation
  328. duplex result 1=Full, 0=Half */
  329. #define IFE_PESC_POLARITY_REVERSED_SHIFT 8
  330. #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down
  331. disabled */
  332. #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity,
  333. 0=Normal */
  334. #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity
  335. Disabled, 0=Enabled */
  336. #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled,
  337. 0=Normal Jabber Operation */
  338. #define IFE_PSC_FORCE_POLARITY_SHIFT 5
  339. #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
  340. #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X
  341. feature, default 0=disabled */
  342. #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X,
  343. 0=force MDI */
  344. #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
  345. #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm
  346. is completed */
  347. #define IFE_PMC_MDIX_MODE_SHIFT 6
  348. #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
  349. #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI
  350. feature */
  351. #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed,
  352. 0=failed */
  353. #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses
  354. on the wire */
  355. #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
  356. #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
  357. #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication
  358. type of problem on the line */
  359. #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to
  360. the cable problem, in 80cm granularity */
  361. #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
  362. #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
  363. #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2
  364. off */
  365. #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
  366. #define NUM_DEV_IDS 16
  367. #define NODE_ADDRESS_SIZE 6
  368. #define ETH_LENGTH_OF_ADDRESS 6
  369. /* MAC decode size is 128K - This is the size of BAR0 */
  370. #define MAC_DECODE_SIZE (128 * 1024)
  371. #define E1000_82542_2_0_REV_ID 2
  372. #define E1000_82542_2_1_REV_ID 3
  373. #define E1000_REVISION_0 0
  374. #define E1000_REVISION_1 1
  375. #define E1000_REVISION_2 2
  376. #define E1000_REVISION_3 3
  377. #define SPEED_10 10
  378. #define SPEED_100 100
  379. #define SPEED_1000 1000
  380. #define HALF_DUPLEX 1
  381. #define FULL_DUPLEX 2
  382. /* The sizes (in bytes) of a ethernet packet */
  383. #define ENET_HEADER_SIZE 14
  384. #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
  385. #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
  386. #define MAXIMUM_ETHERNET_PACKET_SIZE \
  387. (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
  388. #define MINIMUM_ETHERNET_PACKET_SIZE \
  389. (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
  390. #define CRC_LENGTH ETH_FCS_LEN
  391. #define MAX_JUMBO_FRAME_SIZE 0x3F00
  392. /* 802.1q VLAN Packet Sizes */
  393. #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
  394. /* Ethertype field values */
  395. #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
  396. #define ETHERNET_IP_TYPE 0x0800 /* IP packets */
  397. #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
  398. /* Packet Header defines */
  399. #define IP_PROTOCOL_TCP 6
  400. #define IP_PROTOCOL_UDP 0x11
  401. /* This defines the bits that are set in the Interrupt Mask
  402. * Set/Read Register. Each bit is documented below:
  403. * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  404. * o RXSEQ = Receive Sequence Error
  405. */
  406. #define POLL_IMS_ENABLE_MASK ( \
  407. E1000_IMS_RXDMT0 | \
  408. E1000_IMS_RXSEQ)
  409. /* This defines the bits that are set in the Interrupt Mask
  410. * Set/Read Register. Each bit is documented below:
  411. * o RXT0 = Receiver Timer Interrupt (ring 0)
  412. * o TXDW = Transmit Descriptor Written Back
  413. * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  414. * o RXSEQ = Receive Sequence Error
  415. * o LSC = Link Status Change
  416. */
  417. #define IMS_ENABLE_MASK ( \
  418. E1000_IMS_RXT0 | \
  419. E1000_IMS_TXDW | \
  420. E1000_IMS_RXDMT0 | \
  421. E1000_IMS_RXSEQ | \
  422. E1000_IMS_LSC)
  423. /* The number of high/low register pairs in the RAR. The RAR (Receive Address
  424. * Registers) holds the directed and multicast addresses that we monitor. We
  425. * reserve one of these spots for our directed address, allowing us room for
  426. * E1000_RAR_ENTRIES - 1 multicast addresses.
  427. */
  428. #define E1000_RAR_ENTRIES 16
  429. #define MIN_NUMBER_OF_DESCRIPTORS 8
  430. #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
  431. /* Receive Descriptor */
  432. struct e1000_rx_desc {
  433. uint64_t buffer_addr; /* Address of the descriptor's data buffer */
  434. uint16_t length; /* Length of data DMAed into data buffer */
  435. uint16_t csum; /* Packet checksum */
  436. uint8_t status; /* Descriptor status */
  437. uint8_t errors; /* Descriptor Errors */
  438. uint16_t special;
  439. };
  440. /* Receive Decriptor bit definitions */
  441. #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
  442. #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
  443. #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
  444. #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
  445. #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
  446. #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
  447. #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
  448. #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
  449. #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
  450. #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
  451. #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
  452. #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
  453. #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
  454. #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
  455. #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
  456. #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
  457. #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
  458. #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
  459. #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
  460. /* mask to determine if packets should be dropped due to frame errors */
  461. #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
  462. E1000_RXD_ERR_CE | \
  463. E1000_RXD_ERR_SE | \
  464. E1000_RXD_ERR_SEQ | \
  465. E1000_RXD_ERR_CXE | \
  466. E1000_RXD_ERR_RXE)
  467. /* Transmit Descriptor */
  468. struct e1000_tx_desc {
  469. uint64_t buffer_addr; /* Address of the descriptor's data buffer */
  470. union {
  471. uint32_t data;
  472. struct {
  473. uint16_t length; /* Data buffer length */
  474. uint8_t cso; /* Checksum offset */
  475. uint8_t cmd; /* Descriptor control */
  476. } flags;
  477. } lower;
  478. union {
  479. uint32_t data;
  480. struct {
  481. uint8_t status; /* Descriptor status */
  482. uint8_t css; /* Checksum start */
  483. uint16_t special;
  484. } fields;
  485. } upper;
  486. };
  487. /* Transmit Descriptor bit definitions */
  488. #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
  489. #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
  490. #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
  491. #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
  492. #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
  493. #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
  494. #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
  495. #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
  496. #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
  497. #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
  498. #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
  499. #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
  500. #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
  501. #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
  502. #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
  503. #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
  504. #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
  505. #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
  506. #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
  507. #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
  508. /* Offload Context Descriptor */
  509. struct e1000_context_desc {
  510. union {
  511. uint32_t ip_config;
  512. struct {
  513. uint8_t ipcss; /* IP checksum start */
  514. uint8_t ipcso; /* IP checksum offset */
  515. uint16_t ipcse; /* IP checksum end */
  516. } ip_fields;
  517. } lower_setup;
  518. union {
  519. uint32_t tcp_config;
  520. struct {
  521. uint8_t tucss; /* TCP checksum start */
  522. uint8_t tucso; /* TCP checksum offset */
  523. uint16_t tucse; /* TCP checksum end */
  524. } tcp_fields;
  525. } upper_setup;
  526. uint32_t cmd_and_length; /* */
  527. union {
  528. uint32_t data;
  529. struct {
  530. uint8_t status; /* Descriptor status */
  531. uint8_t hdr_len; /* Header length */
  532. uint16_t mss; /* Maximum segment size */
  533. } fields;
  534. } tcp_seg_setup;
  535. };
  536. /* Offload data descriptor */
  537. struct e1000_data_desc {
  538. uint64_t buffer_addr; /* Address of the descriptor's buffer address */
  539. union {
  540. uint32_t data;
  541. struct {
  542. uint16_t length; /* Data buffer length */
  543. uint8_t typ_len_ext; /* */
  544. uint8_t cmd; /* */
  545. } flags;
  546. } lower;
  547. union {
  548. uint32_t data;
  549. struct {
  550. uint8_t status; /* Descriptor status */
  551. uint8_t popts; /* Packet Options */
  552. uint16_t special; /* */
  553. } fields;
  554. } upper;
  555. };
  556. /* Filters */
  557. #define E1000_NUM_UNICAST 16 /* Unicast filter entries */
  558. #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
  559. #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
  560. /* Receive Address Register */
  561. struct e1000_rar {
  562. volatile uint32_t low; /* receive address low */
  563. volatile uint32_t high; /* receive address high */
  564. };
  565. /* The number of entries in the Multicast Table Array (MTA). */
  566. #define E1000_NUM_MTA_REGISTERS 128
  567. /* IPv4 Address Table Entry */
  568. struct e1000_ipv4_at_entry {
  569. volatile uint32_t ipv4_addr; /* IP Address (RW) */
  570. volatile uint32_t reserved;
  571. };
  572. /* Four wakeup IP addresses are supported */
  573. #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
  574. #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
  575. #define E1000_IP6AT_SIZE 1
  576. /* IPv6 Address Table Entry */
  577. struct e1000_ipv6_at_entry {
  578. volatile uint8_t ipv6_addr[16];
  579. };
  580. /* Flexible Filter Length Table Entry */
  581. struct e1000_fflt_entry {
  582. volatile uint32_t length; /* Flexible Filter Length (RW) */
  583. volatile uint32_t reserved;
  584. };
  585. /* Flexible Filter Mask Table Entry */
  586. struct e1000_ffmt_entry {
  587. volatile uint32_t mask; /* Flexible Filter Mask (RW) */
  588. volatile uint32_t reserved;
  589. };
  590. /* Flexible Filter Value Table Entry */
  591. struct e1000_ffvt_entry {
  592. volatile uint32_t value; /* Flexible Filter Value (RW) */
  593. volatile uint32_t reserved;
  594. };
  595. /* Four Flexible Filters are supported */
  596. #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
  597. /* Each Flexible Filter is at most 128 (0x80) bytes in length */
  598. #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
  599. #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
  600. #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
  601. #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
  602. /* Register Set. (82543, 82544)
  603. *
  604. * Registers are defined to be 32 bits and should be accessed as 32 bit values.
  605. * These registers are physically located on the NIC, but are mapped into the
  606. * host memory address space.
  607. *
  608. * RW - register is both readable and writable
  609. * RO - register is read only
  610. * WO - register is write only
  611. * R/clr - register is read only and is cleared when read
  612. * A - register array
  613. */
  614. #define E1000_CTRL 0x00000 /* Device Control - RW */
  615. #define E1000_STATUS 0x00008 /* Device Status - RO */
  616. #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
  617. #define E1000_I210_EECD 0x12010 /* EEPROM/Flash Control - RW */
  618. #define E1000_EERD 0x00014 /* EEPROM Read - RW */
  619. #define E1000_I210_EERD 0x12014 /* EEPROM Read - RW */
  620. #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
  621. #define E1000_MDIC 0x00020 /* MDI Control - RW */
  622. #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
  623. #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
  624. #define E1000_FCT 0x00030 /* Flow Control Type - RW */
  625. #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
  626. #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
  627. #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
  628. #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
  629. #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
  630. #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
  631. #define E1000_I210_IAM 0x000E0 /* Interrupt Ack Auto Mask - RW */
  632. #define E1000_RCTL 0x00100 /* RX Control - RW */
  633. #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
  634. #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
  635. #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
  636. #define E1000_TCTL 0x00400 /* TX Control - RW */
  637. #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
  638. #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
  639. #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
  640. #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
  641. #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
  642. #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
  643. #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
  644. #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
  645. #define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */
  646. #define FEXTNVM_SW_CONFIG 0x0001
  647. #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
  648. #define E1000_PBS 0x01008 /* Packet Buffer Size */
  649. #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
  650. #define E1000_I210_EEMNGCTL 0x12030 /* MNG EEprom Control */
  651. #define E1000_FLASH_UPDATES 1000
  652. #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
  653. #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
  654. #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
  655. #define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */
  656. #define E1000_FLSWCTL 0x01030 /* FLASH control register */
  657. #define E1000_FLSWDATA 0x01034 /* FLASH data register */
  658. #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
  659. #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
  660. #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
  661. #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
  662. #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
  663. #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
  664. #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
  665. #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
  666. #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
  667. #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
  668. #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
  669. #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
  670. #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
  671. #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
  672. #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
  673. #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
  674. #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
  675. #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
  676. #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
  677. #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
  678. #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
  679. #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
  680. #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
  681. #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
  682. #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
  683. #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
  684. #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
  685. #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
  686. #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
  687. #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
  688. #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
  689. #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
  690. #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
  691. #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
  692. #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
  693. #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
  694. #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
  695. #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
  696. #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
  697. #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
  698. #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
  699. #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
  700. #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
  701. #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
  702. #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
  703. #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
  704. #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
  705. #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
  706. #define E1000_COLC 0x04028 /* Collision Count - R/clr */
  707. #define E1000_DC 0x04030 /* Defer Count - R/clr */
  708. #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
  709. #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
  710. #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
  711. #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
  712. #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
  713. #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
  714. #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
  715. #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
  716. #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
  717. #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
  718. #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
  719. #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
  720. #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
  721. #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
  722. #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
  723. #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
  724. #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
  725. #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
  726. #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
  727. #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
  728. #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
  729. #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
  730. #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
  731. #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
  732. #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
  733. #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
  734. #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
  735. #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
  736. #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
  737. #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
  738. #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
  739. #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
  740. #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
  741. #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
  742. #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
  743. #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
  744. #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
  745. #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
  746. #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
  747. #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
  748. #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
  749. #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
  750. #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
  751. #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
  752. #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
  753. #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
  754. #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
  755. #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
  756. #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
  757. #define E1000_RA 0x05400 /* Receive Address - RW Array */
  758. #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
  759. #define E1000_WUC 0x05800 /* Wakeup Control - RW */
  760. #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
  761. #define E1000_WUS 0x05810 /* Wakeup Status - RO */
  762. #define E1000_MANC 0x05820 /* Management Control - RW */
  763. #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
  764. #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
  765. #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
  766. #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
  767. #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
  768. #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
  769. #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
  770. #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
  771. /* Register Set (82542)
  772. *
  773. * Some of the 82542 registers are located at different offsets than they are
  774. * in more current versions of the 8254x. Despite the difference in location,
  775. * the registers function in the same manner.
  776. */
  777. #define E1000_82542_CTRL E1000_CTRL
  778. #define E1000_82542_STATUS E1000_STATUS
  779. #define E1000_82542_EECD E1000_EECD
  780. #define E1000_82542_EERD E1000_EERD
  781. #define E1000_82542_CTRL_EXT E1000_CTRL_EXT
  782. #define E1000_82542_MDIC E1000_MDIC
  783. #define E1000_82542_FCAL E1000_FCAL
  784. #define E1000_82542_FCAH E1000_FCAH
  785. #define E1000_82542_FCT E1000_FCT
  786. #define E1000_82542_VET E1000_VET
  787. #define E1000_82542_RA 0x00040
  788. #define E1000_82542_ICR E1000_ICR
  789. #define E1000_82542_ITR E1000_ITR
  790. #define E1000_82542_ICS E1000_ICS
  791. #define E1000_82542_IMS E1000_IMS
  792. #define E1000_82542_IMC E1000_IMC
  793. #define E1000_82542_RCTL E1000_RCTL
  794. #define E1000_82542_RDTR 0x00108
  795. #define E1000_82542_RDBAL 0x00110
  796. #define E1000_82542_RDBAH 0x00114
  797. #define E1000_82542_RDLEN 0x00118
  798. #define E1000_82542_RDH 0x00120
  799. #define E1000_82542_RDT 0x00128
  800. #define E1000_82542_FCRTH 0x00160
  801. #define E1000_82542_FCRTL 0x00168
  802. #define E1000_82542_FCTTV E1000_FCTTV
  803. #define E1000_82542_TXCW E1000_TXCW
  804. #define E1000_82542_RXCW E1000_RXCW
  805. #define E1000_82542_MTA 0x00200
  806. #define E1000_82542_TCTL E1000_TCTL
  807. #define E1000_82542_TIPG E1000_TIPG
  808. #define E1000_82542_TDBAL 0x00420
  809. #define E1000_82542_TDBAH 0x00424
  810. #define E1000_82542_TDLEN 0x00428
  811. #define E1000_82542_TDH 0x00430
  812. #define E1000_82542_TDT 0x00438
  813. #define E1000_82542_TIDV 0x00440
  814. #define E1000_82542_TBT E1000_TBT
  815. #define E1000_82542_AIT E1000_AIT
  816. #define E1000_82542_VFTA 0x00600
  817. #define E1000_82542_LEDCTL E1000_LEDCTL
  818. #define E1000_82542_PBA E1000_PBA
  819. #define E1000_82542_RXDCTL E1000_RXDCTL
  820. #define E1000_82542_RADV E1000_RADV
  821. #define E1000_82542_RSRPD E1000_RSRPD
  822. #define E1000_82542_TXDMAC E1000_TXDMAC
  823. #define E1000_82542_TXDCTL E1000_TXDCTL
  824. #define E1000_82542_TADV E1000_TADV
  825. #define E1000_82542_TSPMT E1000_TSPMT
  826. #define E1000_82542_CRCERRS E1000_CRCERRS
  827. #define E1000_82542_ALGNERRC E1000_ALGNERRC
  828. #define E1000_82542_SYMERRS E1000_SYMERRS
  829. #define E1000_82542_RXERRC E1000_RXERRC
  830. #define E1000_82542_MPC E1000_MPC
  831. #define E1000_82542_SCC E1000_SCC
  832. #define E1000_82542_ECOL E1000_ECOL
  833. #define E1000_82542_MCC E1000_MCC
  834. #define E1000_82542_LATECOL E1000_LATECOL
  835. #define E1000_82542_COLC E1000_COLC
  836. #define E1000_82542_DC E1000_DC
  837. #define E1000_82542_TNCRS E1000_TNCRS
  838. #define E1000_82542_SEC E1000_SEC
  839. #define E1000_82542_CEXTERR E1000_CEXTERR
  840. #define E1000_82542_RLEC E1000_RLEC
  841. #define E1000_82542_XONRXC E1000_XONRXC
  842. #define E1000_82542_XONTXC E1000_XONTXC
  843. #define E1000_82542_XOFFRXC E1000_XOFFRXC
  844. #define E1000_82542_XOFFTXC E1000_XOFFTXC
  845. #define E1000_82542_FCRUC E1000_FCRUC
  846. #define E1000_82542_PRC64 E1000_PRC64
  847. #define E1000_82542_PRC127 E1000_PRC127
  848. #define E1000_82542_PRC255 E1000_PRC255
  849. #define E1000_82542_PRC511 E1000_PRC511
  850. #define E1000_82542_PRC1023 E1000_PRC1023
  851. #define E1000_82542_PRC1522 E1000_PRC1522
  852. #define E1000_82542_GPRC E1000_GPRC
  853. #define E1000_82542_BPRC E1000_BPRC
  854. #define E1000_82542_MPRC E1000_MPRC
  855. #define E1000_82542_GPTC E1000_GPTC
  856. #define E1000_82542_GORCL E1000_GORCL
  857. #define E1000_82542_GORCH E1000_GORCH
  858. #define E1000_82542_GOTCL E1000_GOTCL
  859. #define E1000_82542_GOTCH E1000_GOTCH
  860. #define E1000_82542_RNBC E1000_RNBC
  861. #define E1000_82542_RUC E1000_RUC
  862. #define E1000_82542_RFC E1000_RFC
  863. #define E1000_82542_ROC E1000_ROC
  864. #define E1000_82542_RJC E1000_RJC
  865. #define E1000_82542_MGTPRC E1000_MGTPRC
  866. #define E1000_82542_MGTPDC E1000_MGTPDC
  867. #define E1000_82542_MGTPTC E1000_MGTPTC
  868. #define E1000_82542_TORL E1000_TORL
  869. #define E1000_82542_TORH E1000_TORH
  870. #define E1000_82542_TOTL E1000_TOTL
  871. #define E1000_82542_TOTH E1000_TOTH
  872. #define E1000_82542_TPR E1000_TPR
  873. #define E1000_82542_TPT E1000_TPT
  874. #define E1000_82542_PTC64 E1000_PTC64
  875. #define E1000_82542_PTC127 E1000_PTC127
  876. #define E1000_82542_PTC255 E1000_PTC255
  877. #define E1000_82542_PTC511 E1000_PTC511
  878. #define E1000_82542_PTC1023 E1000_PTC1023
  879. #define E1000_82542_PTC1522 E1000_PTC1522
  880. #define E1000_82542_MPTC E1000_MPTC
  881. #define E1000_82542_BPTC E1000_BPTC
  882. #define E1000_82542_TSCTC E1000_TSCTC
  883. #define E1000_82542_TSCTFC E1000_TSCTFC
  884. #define E1000_82542_RXCSUM E1000_RXCSUM
  885. #define E1000_82542_WUC E1000_WUC
  886. #define E1000_82542_WUFC E1000_WUFC
  887. #define E1000_82542_WUS E1000_WUS
  888. #define E1000_82542_MANC E1000_MANC
  889. #define E1000_82542_IPAV E1000_IPAV
  890. #define E1000_82542_IP4AT E1000_IP4AT
  891. #define E1000_82542_IP6AT E1000_IP6AT
  892. #define E1000_82542_WUPL E1000_WUPL
  893. #define E1000_82542_WUPM E1000_WUPM
  894. #define E1000_82542_FFLT E1000_FFLT
  895. #define E1000_82542_FFMT E1000_FFMT
  896. #define E1000_82542_FFVT E1000_FFVT
  897. /* Statistics counters collected by the MAC */
  898. struct e1000_hw_stats {
  899. uint64_t crcerrs;
  900. uint64_t algnerrc;
  901. uint64_t symerrs;
  902. uint64_t rxerrc;
  903. uint64_t mpc;
  904. uint64_t scc;
  905. uint64_t ecol;
  906. uint64_t mcc;
  907. uint64_t latecol;
  908. uint64_t colc;
  909. uint64_t dc;
  910. uint64_t tncrs;
  911. uint64_t sec;
  912. uint64_t cexterr;
  913. uint64_t rlec;
  914. uint64_t xonrxc;
  915. uint64_t xontxc;
  916. uint64_t xoffrxc;
  917. uint64_t xofftxc;
  918. uint64_t fcruc;
  919. uint64_t prc64;
  920. uint64_t prc127;
  921. uint64_t prc255;
  922. uint64_t prc511;
  923. uint64_t prc1023;
  924. uint64_t prc1522;
  925. uint64_t gprc;
  926. uint64_t bprc;
  927. uint64_t mprc;
  928. uint64_t gptc;
  929. uint64_t gorcl;
  930. uint64_t gorch;
  931. uint64_t gotcl;
  932. uint64_t gotch;
  933. uint64_t rnbc;
  934. uint64_t ruc;
  935. uint64_t rfc;
  936. uint64_t roc;
  937. uint64_t rjc;
  938. uint64_t mgprc;
  939. uint64_t mgpdc;
  940. uint64_t mgptc;
  941. uint64_t torl;
  942. uint64_t torh;
  943. uint64_t totl;
  944. uint64_t toth;
  945. uint64_t tpr;
  946. uint64_t tpt;
  947. uint64_t ptc64;
  948. uint64_t ptc127;
  949. uint64_t ptc255;
  950. uint64_t ptc511;
  951. uint64_t ptc1023;
  952. uint64_t ptc1522;
  953. uint64_t mptc;
  954. uint64_t bptc;
  955. uint64_t tsctc;
  956. uint64_t tsctfc;
  957. };
  958. #ifndef CONFIG_E1000_NO_NVM
  959. struct e1000_eeprom_info {
  960. e1000_eeprom_type type;
  961. uint16_t word_size;
  962. uint16_t opcode_bits;
  963. uint16_t address_bits;
  964. uint16_t delay_usec;
  965. uint16_t page_size;
  966. bool use_eerd;
  967. bool use_eewr;
  968. };
  969. #endif
  970. typedef enum {
  971. e1000_smart_speed_default = 0,
  972. e1000_smart_speed_on,
  973. e1000_smart_speed_off
  974. } e1000_smart_speed;
  975. typedef enum {
  976. e1000_dsp_config_disabled = 0,
  977. e1000_dsp_config_enabled,
  978. e1000_dsp_config_activated,
  979. e1000_dsp_config_undefined = 0xFF
  980. } e1000_dsp_config;
  981. typedef enum {
  982. e1000_ms_hw_default = 0,
  983. e1000_ms_force_master,
  984. e1000_ms_force_slave,
  985. e1000_ms_auto
  986. } e1000_ms_type;
  987. typedef enum {
  988. e1000_ffe_config_enabled = 0,
  989. e1000_ffe_config_active,
  990. e1000_ffe_config_blocked
  991. } e1000_ffe_config;
  992. /* Structure containing variables used by the shared code (e1000_hw.c) */
  993. struct e1000_hw {
  994. const char *name;
  995. struct list_head list_node;
  996. #ifndef CONFIG_DM_ETH
  997. struct eth_device *nic;
  998. #endif
  999. #ifdef CONFIG_E1000_SPI
  1000. struct spi_slave spi;
  1001. #endif
  1002. unsigned int cardnum;
  1003. #ifdef CONFIG_DM_ETH
  1004. struct udevice *pdev;
  1005. #else
  1006. pci_dev_t pdev;
  1007. #endif
  1008. uint8_t *hw_addr;
  1009. e1000_mac_type mac_type;
  1010. e1000_phy_type phy_type;
  1011. uint32_t phy_init_script;
  1012. uint32_t txd_cmd;
  1013. e1000_media_type media_type;
  1014. e1000_fc_type fc;
  1015. e1000_bus_type bus_type;
  1016. uint32_t asf_firmware_present;
  1017. #ifndef CONFIG_E1000_NO_NVM
  1018. uint32_t eeprom_semaphore_present;
  1019. #endif
  1020. uint32_t swfw_sync_present;
  1021. uint32_t swfwhw_semaphore_present;
  1022. #ifndef CONFIG_E1000_NO_NVM
  1023. struct e1000_eeprom_info eeprom;
  1024. #endif
  1025. e1000_ms_type master_slave;
  1026. e1000_ms_type original_master_slave;
  1027. e1000_ffe_config ffe_config_state;
  1028. uint32_t phy_id;
  1029. uint32_t phy_revision;
  1030. uint32_t phy_addr;
  1031. uint32_t original_fc;
  1032. uint32_t txcw;
  1033. uint32_t autoneg_failed;
  1034. uint16_t autoneg_advertised;
  1035. uint16_t pci_cmd_word;
  1036. uint16_t fc_high_water;
  1037. uint16_t fc_low_water;
  1038. uint16_t fc_pause_time;
  1039. uint16_t device_id;
  1040. uint16_t vendor_id;
  1041. uint16_t subsystem_id;
  1042. uint16_t subsystem_vendor_id;
  1043. uint8_t revision_id;
  1044. uint8_t autoneg;
  1045. uint8_t mdix;
  1046. uint8_t forced_speed_duplex;
  1047. uint8_t wait_autoneg_complete;
  1048. uint8_t dma_fairness;
  1049. bool disable_polarity_correction;
  1050. bool speed_downgraded;
  1051. bool get_link_status;
  1052. bool tbi_compatibility_en;
  1053. bool tbi_compatibility_on;
  1054. bool fc_strict_ieee;
  1055. bool fc_send_xon;
  1056. bool report_tx_early;
  1057. bool phy_reset_disable;
  1058. bool initialize_hw_bits_disable;
  1059. e1000_smart_speed smart_speed;
  1060. e1000_dsp_config dsp_config_state;
  1061. };
  1062. #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
  1063. #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
  1064. #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM
  1065. read/write registers */
  1066. #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
  1067. #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start
  1068. operation */
  1069. #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
  1070. #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write
  1071. complete */
  1072. #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
  1073. #define EEPROM_RESERVED_WORD 0xFFFF
  1074. /* Register Bit Masks */
  1075. /* Device Control */
  1076. #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
  1077. #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
  1078. #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
  1079. #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
  1080. #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
  1081. #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
  1082. #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
  1083. #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
  1084. #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
  1085. #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
  1086. #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
  1087. #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
  1088. #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
  1089. #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
  1090. #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
  1091. #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
  1092. #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
  1093. #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
  1094. #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
  1095. #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
  1096. #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
  1097. #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
  1098. #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
  1099. #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
  1100. #define E1000_CTRL_RST 0x04000000 /* Global reset */
  1101. #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
  1102. #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
  1103. #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
  1104. #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
  1105. #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
  1106. /* Device Status */
  1107. #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
  1108. #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
  1109. #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
  1110. #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
  1111. #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
  1112. #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
  1113. #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
  1114. #define E1000_STATUS_SPEED_MASK 0x000000C0
  1115. #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
  1116. #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
  1117. #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
  1118. #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
  1119. #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
  1120. #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
  1121. #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
  1122. #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
  1123. #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
  1124. #define E1000_STATUS_PF_RST_DONE 0x00200000 /* PCI-X bus speed */
  1125. /* Constants used to intrepret the masked PCI-X bus speed. */
  1126. #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
  1127. #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
  1128. #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
  1129. /* EEPROM/Flash Control */
  1130. #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
  1131. #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
  1132. #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
  1133. #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
  1134. #define E1000_EECD_FWE_MASK 0x00000030
  1135. #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
  1136. #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
  1137. #define E1000_EECD_FWE_SHIFT 4
  1138. #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
  1139. #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
  1140. #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
  1141. #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
  1142. #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
  1143. * (0-small, 1-large) */
  1144. #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
  1145. #ifndef E1000_EEPROM_GRANT_ATTEMPTS
  1146. #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
  1147. #endif
  1148. #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
  1149. #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
  1150. #define E1000_EECD_SIZE_EX_SHIFT 11
  1151. #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
  1152. #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
  1153. #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
  1154. #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
  1155. #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
  1156. #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
  1157. #define E1000_FLUDONE_ATTEMPTS 20000
  1158. #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
  1159. #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
  1160. #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
  1161. #define E1000_EECD_SECVAL_SHIFT 22
  1162. #define E1000_STM_OPCODE 0xDB00
  1163. #define E1000_HICR_FW_RESET 0xC0
  1164. #define E1000_SHADOW_RAM_WORDS 2048
  1165. #define E1000_ICH_NVM_SIG_WORD 0x13
  1166. #define E1000_ICH_NVM_SIG_MASK 0xC0
  1167. /* EEPROM Read */
  1168. #define E1000_EERD_START 0x00000001 /* Start Read */
  1169. #define E1000_EERD_DONE 0x00000010 /* Read Done */
  1170. #define E1000_EERD_ADDR_SHIFT 8
  1171. #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
  1172. #define E1000_EERD_DATA_SHIFT 16
  1173. #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
  1174. /* EEPROM Commands - Microwire */
  1175. #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
  1176. #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
  1177. #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
  1178. #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
  1179. #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
  1180. /* EEPROM Commands - SPI */
  1181. #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
  1182. #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
  1183. #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
  1184. #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
  1185. #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
  1186. #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
  1187. #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
  1188. #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
  1189. #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
  1190. #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
  1191. #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
  1192. /* EEPROM Size definitions */
  1193. #define EEPROM_WORD_SIZE_SHIFT 6
  1194. #define EEPROM_SIZE_SHIFT 10
  1195. #define EEPROM_SIZE_MASK 0x1C00
  1196. /* EEPROM Word Offsets */
  1197. #define EEPROM_COMPAT 0x0003
  1198. #define EEPROM_ID_LED_SETTINGS 0x0004
  1199. #define EEPROM_VERSION 0x0005
  1200. #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude
  1201. adjustment. */
  1202. #define EEPROM_PHY_CLASS_WORD 0x0007
  1203. #define EEPROM_INIT_CONTROL1_REG 0x000A
  1204. #define EEPROM_INIT_CONTROL2_REG 0x000F
  1205. #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
  1206. #define EEPROM_INIT_CONTROL3_PORT_B 0x0014
  1207. #define EEPROM_INIT_3GIO_3 0x001A
  1208. #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
  1209. #define EEPROM_INIT_CONTROL3_PORT_A 0x0024
  1210. #define EEPROM_CFG 0x0012
  1211. #define EEPROM_FLASH_VERSION 0x0032
  1212. #define EEPROM_CHECKSUM_REG 0x003F
  1213. #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
  1214. #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
  1215. /* Extended Device Control */
  1216. #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
  1217. #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
  1218. #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
  1219. #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
  1220. #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
  1221. #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable
  1222. Pin 4 */
  1223. #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable
  1224. Pin 5 */
  1225. #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
  1226. #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
  1227. #define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */
  1228. #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
  1229. #define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */
  1230. #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
  1231. #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
  1232. #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
  1233. #define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */
  1234. #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
  1235. #define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */
  1236. #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
  1237. #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
  1238. #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
  1239. #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
  1240. #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
  1241. #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
  1242. #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
  1243. #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
  1244. #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
  1245. #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
  1246. #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
  1247. #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
  1248. #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
  1249. /* MDI Control */
  1250. #define E1000_MDIC_DATA_MASK 0x0000FFFF
  1251. #define E1000_MDIC_REG_MASK 0x001F0000
  1252. #define E1000_MDIC_REG_SHIFT 16
  1253. #define E1000_MDIC_PHY_MASK 0x03E00000
  1254. #define E1000_MDIC_PHY_SHIFT 21
  1255. #define E1000_MDIC_OP_WRITE 0x04000000
  1256. #define E1000_MDIC_OP_READ 0x08000000
  1257. #define E1000_MDIC_READY 0x10000000
  1258. #define E1000_MDIC_INT_EN 0x20000000
  1259. #define E1000_MDIC_ERROR 0x40000000
  1260. #define E1000_PHY_CTRL_SPD_EN 0x00000001
  1261. #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
  1262. #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
  1263. #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
  1264. #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
  1265. #define E1000_PHY_CTRL_B2B_EN 0x00000080
  1266. /* LED Control */
  1267. #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
  1268. #define E1000_LEDCTL_LED0_MODE_SHIFT 0
  1269. #define E1000_LEDCTL_LED0_IVRT 0x00000040
  1270. #define E1000_LEDCTL_LED0_BLINK 0x00000080
  1271. #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
  1272. #define E1000_LEDCTL_LED1_MODE_SHIFT 8
  1273. #define E1000_LEDCTL_LED1_IVRT 0x00004000
  1274. #define E1000_LEDCTL_LED1_BLINK 0x00008000
  1275. #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
  1276. #define E1000_LEDCTL_LED2_MODE_SHIFT 16
  1277. #define E1000_LEDCTL_LED2_IVRT 0x00400000
  1278. #define E1000_LEDCTL_LED2_BLINK 0x00800000
  1279. #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
  1280. #define E1000_LEDCTL_LED3_MODE_SHIFT 24
  1281. #define E1000_LEDCTL_LED3_IVRT 0x40000000
  1282. #define E1000_LEDCTL_LED3_BLINK 0x80000000
  1283. #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
  1284. #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
  1285. #define E1000_LEDCTL_MODE_LINK_UP 0x2
  1286. #define E1000_LEDCTL_MODE_ACTIVITY 0x3
  1287. #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
  1288. #define E1000_LEDCTL_MODE_LINK_10 0x5
  1289. #define E1000_LEDCTL_MODE_LINK_100 0x6
  1290. #define E1000_LEDCTL_MODE_LINK_1000 0x7
  1291. #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
  1292. #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
  1293. #define E1000_LEDCTL_MODE_COLLISION 0xA
  1294. #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
  1295. #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
  1296. #define E1000_LEDCTL_MODE_PAUSED 0xD
  1297. #define E1000_LEDCTL_MODE_LED_ON 0xE
  1298. #define E1000_LEDCTL_MODE_LED_OFF 0xF
  1299. /* Receive Address */
  1300. #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
  1301. /* Interrupt Cause Read */
  1302. #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
  1303. #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
  1304. #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
  1305. #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
  1306. #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
  1307. #define E1000_ICR_RXO 0x00000040 /* rx overrun */
  1308. #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
  1309. #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
  1310. #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
  1311. #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
  1312. #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
  1313. #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
  1314. #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
  1315. #define E1000_ICR_TXD_LOW 0x00008000
  1316. #define E1000_ICR_SRPD 0x00010000
  1317. /* Interrupt Cause Set */
  1318. #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
  1319. #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
  1320. #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
  1321. #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
  1322. #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
  1323. #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
  1324. #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
  1325. #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
  1326. #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
  1327. #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
  1328. #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
  1329. #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
  1330. #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
  1331. #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
  1332. #define E1000_ICS_SRPD E1000_ICR_SRPD
  1333. /* Interrupt Mask Set */
  1334. #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
  1335. #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
  1336. #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
  1337. #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
  1338. #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
  1339. #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
  1340. #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
  1341. #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
  1342. #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
  1343. #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
  1344. #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
  1345. #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
  1346. #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
  1347. #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
  1348. #define E1000_IMS_SRPD E1000_ICR_SRPD
  1349. /* Interrupt Mask Clear */
  1350. #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
  1351. #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
  1352. #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
  1353. #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
  1354. #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
  1355. #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
  1356. #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
  1357. #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
  1358. #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
  1359. #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
  1360. #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
  1361. #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
  1362. #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
  1363. #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
  1364. #define E1000_IMC_SRPD E1000_ICR_SRPD
  1365. /* Receive Control */
  1366. #define E1000_RCTL_RST 0x00000001 /* Software reset */
  1367. #define E1000_RCTL_EN 0x00000002 /* enable */
  1368. #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
  1369. #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
  1370. #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
  1371. #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
  1372. #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
  1373. #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
  1374. #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
  1375. #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
  1376. #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
  1377. #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
  1378. #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
  1379. #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
  1380. #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
  1381. #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
  1382. #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
  1383. #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
  1384. #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
  1385. #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
  1386. /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
  1387. #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
  1388. #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
  1389. #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
  1390. #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
  1391. /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
  1392. #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
  1393. #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
  1394. #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
  1395. #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
  1396. #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
  1397. #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
  1398. #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
  1399. #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
  1400. #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
  1401. /* SW_W_SYNC definitions */
  1402. #define E1000_SWFW_EEP_SM 0x0001
  1403. #define E1000_SWFW_PHY0_SM 0x0002
  1404. #define E1000_SWFW_PHY1_SM 0x0004
  1405. #define E1000_SWFW_MAC_CSR_SM 0x0008
  1406. /* Receive Descriptor */
  1407. #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
  1408. #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
  1409. #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
  1410. #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
  1411. #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
  1412. /* Flow Control */
  1413. #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
  1414. #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
  1415. #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
  1416. #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
  1417. /* Receive Descriptor Control */
  1418. #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
  1419. #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
  1420. #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
  1421. #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
  1422. #define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
  1423. /* Transmit Descriptor Control */
  1424. #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
  1425. #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
  1426. #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
  1427. #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
  1428. #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
  1429. #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
  1430. #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
  1431. still to be processed. */
  1432. /* Transmit Configuration Word */
  1433. #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
  1434. #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
  1435. #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
  1436. #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
  1437. #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
  1438. #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
  1439. #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
  1440. #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
  1441. #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
  1442. #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
  1443. /* Receive Configuration Word */
  1444. #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
  1445. #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
  1446. #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
  1447. #define E1000_RXCW_CC 0x10000000 /* Receive config change */
  1448. #define E1000_RXCW_C 0x20000000 /* Receive config */
  1449. #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
  1450. #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
  1451. /* Transmit Control */
  1452. #define E1000_TCTL_RST 0x00000001 /* software reset */
  1453. #define E1000_TCTL_EN 0x00000002 /* enable tx */
  1454. #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
  1455. #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
  1456. #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
  1457. #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
  1458. #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
  1459. #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
  1460. #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
  1461. #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
  1462. #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
  1463. /* Receive Checksum Control */
  1464. #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
  1465. #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
  1466. #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
  1467. #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
  1468. /* Definitions for power management and wakeup registers */
  1469. /* Wake Up Control */
  1470. #define E1000_WUC_APME 0x00000001 /* APM Enable */
  1471. #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
  1472. #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
  1473. #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
  1474. /* Wake Up Filter Control */
  1475. #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  1476. #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
  1477. #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
  1478. #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
  1479. #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
  1480. #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
  1481. #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
  1482. #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
  1483. #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
  1484. #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
  1485. #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
  1486. #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
  1487. #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
  1488. #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
  1489. #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
  1490. /* Wake Up Status */
  1491. #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
  1492. #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
  1493. #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
  1494. #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
  1495. #define E1000_WUS_BC 0x00000010 /* Broadcast Received */
  1496. #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
  1497. #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
  1498. #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
  1499. #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
  1500. #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
  1501. #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
  1502. #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
  1503. #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
  1504. /* Management Control */
  1505. #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
  1506. #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
  1507. #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
  1508. #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
  1509. #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
  1510. #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
  1511. #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
  1512. #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
  1513. #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
  1514. #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
  1515. * Filtering */
  1516. #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
  1517. #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
  1518. #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
  1519. #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
  1520. #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
  1521. #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
  1522. #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
  1523. #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
  1524. #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
  1525. #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
  1526. #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
  1527. /* Wake Up Packet Length */
  1528. #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
  1529. #define E1000_MDALIGN 4096
  1530. /* EEPROM Commands */
  1531. #define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
  1532. #define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
  1533. #define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
  1534. #define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
  1535. #define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
  1536. /* Word definitions for ID LED Settings */
  1537. #define ID_LED_RESERVED_0000 0x0000
  1538. #define ID_LED_RESERVED_FFFF 0xFFFF
  1539. #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
  1540. (ID_LED_OFF1_OFF2 << 8) | \
  1541. (ID_LED_DEF1_DEF2 << 4) | \
  1542. (ID_LED_DEF1_DEF2))
  1543. #define ID_LED_DEF1_DEF2 0x1
  1544. #define ID_LED_DEF1_ON2 0x2
  1545. #define ID_LED_DEF1_OFF2 0x3
  1546. #define ID_LED_ON1_DEF2 0x4
  1547. #define ID_LED_ON1_ON2 0x5
  1548. #define ID_LED_ON1_OFF2 0x6
  1549. #define ID_LED_OFF1_DEF2 0x7
  1550. #define ID_LED_OFF1_ON2 0x8
  1551. #define ID_LED_OFF1_OFF2 0x9
  1552. /* Mask bits for fields in Word 0x03 of the EEPROM */
  1553. #define EEPROM_COMPAT_SERVER 0x0400
  1554. #define EEPROM_COMPAT_CLIENT 0x0200
  1555. /* Mask bits for fields in Word 0x0a of the EEPROM */
  1556. #define EEPROM_WORD0A_ILOS 0x0010
  1557. #define EEPROM_WORD0A_SWDPIO 0x01E0
  1558. #define EEPROM_WORD0A_LRST 0x0200
  1559. #define EEPROM_WORD0A_FD 0x0400
  1560. #define EEPROM_WORD0A_66MHZ 0x0800
  1561. /* Mask bits for fields in Word 0x0f of the EEPROM */
  1562. #define EEPROM_WORD0F_PAUSE_MASK 0x3000
  1563. #define EEPROM_WORD0F_PAUSE 0x1000
  1564. #define EEPROM_WORD0F_ASM_DIR 0x2000
  1565. #define EEPROM_WORD0F_ANE 0x0800
  1566. #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
  1567. /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
  1568. #define EEPROM_SUM 0xBABA
  1569. /* EEPROM Map defines (WORD OFFSETS)*/
  1570. #define EEPROM_NODE_ADDRESS_BYTE_0 0
  1571. #define EEPROM_PBA_BYTE_1 8
  1572. /* EEPROM Map Sizes (Byte Counts) */
  1573. #define PBA_SIZE 4
  1574. /* Collision related configuration parameters */
  1575. #define E1000_COLLISION_THRESHOLD 0xF
  1576. #define E1000_CT_SHIFT 4
  1577. #define E1000_COLLISION_DISTANCE 63
  1578. #define E1000_COLLISION_DISTANCE_82542 64
  1579. #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
  1580. #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
  1581. #define E1000_GB_HDX_COLLISION_DISTANCE 512
  1582. #define E1000_COLD_SHIFT 12
  1583. /* The number of Transmit and Receive Descriptors must be a multiple of 8 */
  1584. #define REQ_TX_DESCRIPTOR_MULTIPLE 8
  1585. #define REQ_RX_DESCRIPTOR_MULTIPLE 8
  1586. /* Default values for the transmit IPG register */
  1587. #define DEFAULT_82542_TIPG_IPGT 10
  1588. #define DEFAULT_82543_TIPG_IPGT_FIBER 9
  1589. #define DEFAULT_82543_TIPG_IPGT_COPPER 8
  1590. #define E1000_TIPG_IPGT_MASK 0x000003FF
  1591. #define E1000_TIPG_IPGR1_MASK 0x000FFC00
  1592. #define E1000_TIPG_IPGR2_MASK 0x3FF00000
  1593. #define DEFAULT_82542_TIPG_IPGR1 2
  1594. #define DEFAULT_82543_TIPG_IPGR1 8
  1595. #define E1000_TIPG_IPGR1_SHIFT 10
  1596. #define DEFAULT_82542_TIPG_IPGR2 10
  1597. #define DEFAULT_82543_TIPG_IPGR2 6
  1598. #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
  1599. #define E1000_TIPG_IPGR2_SHIFT 20
  1600. #define E1000_TXDMAC_DPP 0x00000001
  1601. /* Adaptive IFS defines */
  1602. #define TX_THRESHOLD_START 8
  1603. #define TX_THRESHOLD_INCREMENT 10
  1604. #define TX_THRESHOLD_DECREMENT 1
  1605. #define TX_THRESHOLD_STOP 190
  1606. #define TX_THRESHOLD_DISABLE 0
  1607. #define TX_THRESHOLD_TIMER_MS 10000
  1608. #define MIN_NUM_XMITS 1000
  1609. #define IFS_MAX 80
  1610. #define IFS_STEP 10
  1611. #define IFS_MIN 40
  1612. #define IFS_RATIO 4
  1613. /* PBA constants */
  1614. #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
  1615. #define E1000_PBA_24K 0x0018
  1616. #define E1000_PBA_38K 0x0026
  1617. #define E1000_PBA_40K 0x0028
  1618. #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
  1619. /* Flow Control Constants */
  1620. #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
  1621. #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
  1622. #define FLOW_CONTROL_TYPE 0x8808
  1623. /* The historical defaults for the flow control values are given below. */
  1624. #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
  1625. #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
  1626. #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
  1627. /* Flow Control High-Watermark: 43464 bytes */
  1628. #define E1000_FC_HIGH_THRESH 0xA9C8
  1629. /* Flow Control Low-Watermark: 43456 bytes */
  1630. #define E1000_FC_LOW_THRESH 0xA9C0
  1631. /* Flow Control Pause Time: 858 usec */
  1632. #define E1000_FC_PAUSE_TIME 0x0680
  1633. /* PCIX Config space */
  1634. #define PCIX_COMMAND_REGISTER 0xE6
  1635. #define PCIX_STATUS_REGISTER_LO 0xE8
  1636. #define PCIX_STATUS_REGISTER_HI 0xEA
  1637. #define PCIX_COMMAND_MMRBC_MASK 0x000C
  1638. #define PCIX_COMMAND_MMRBC_SHIFT 0x2
  1639. #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
  1640. #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
  1641. #define PCIX_STATUS_HI_MMRBC_4K 0x3
  1642. #define PCIX_STATUS_HI_MMRBC_2K 0x2
  1643. /* The number of bits that we need to shift right to move the "pause"
  1644. * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
  1645. * in the TXCW register
  1646. */
  1647. #define PAUSE_SHIFT 5
  1648. /* The number of bits that we need to shift left to move the "SWDPIO"
  1649. * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
  1650. * in the CTRL register
  1651. */
  1652. #define SWDPIO_SHIFT 17
  1653. /* The number of bits that we need to shift left to move the "SWDPIO_EXT"
  1654. * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
  1655. * Extended CTRL register.
  1656. * in the CTRL register
  1657. */
  1658. #define SWDPIO__EXT_SHIFT 4
  1659. /* The number of bits that we need to shift left to move the "ILOS"
  1660. * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
  1661. * in the CTRL register
  1662. */
  1663. #define ILOS_SHIFT 3
  1664. #define RECEIVE_BUFFER_ALIGN_SIZE (256)
  1665. /* The number of milliseconds we wait for auto-negotiation to complete */
  1666. #define LINK_UP_TIMEOUT 500
  1667. #define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
  1668. /* The carrier extension symbol, as received by the NIC. */
  1669. #define CARRIER_EXTENSION 0x0F
  1670. /* TBI_ACCEPT macro definition:
  1671. *
  1672. * This macro requires:
  1673. * adapter = a pointer to struct e1000_hw
  1674. * status = the 8 bit status field of the RX descriptor with EOP set
  1675. * error = the 8 bit error field of the RX descriptor with EOP set
  1676. * length = the sum of all the length fields of the RX descriptors that
  1677. * make up the current frame
  1678. * last_byte = the last byte of the frame DMAed by the hardware
  1679. * max_frame_length = the maximum frame length we want to accept.
  1680. * min_frame_length = the minimum frame length we want to accept.
  1681. *
  1682. * This macro is a conditional that should be used in the interrupt
  1683. * handler's Rx processing routine when RxErrors have been detected.
  1684. *
  1685. * Typical use:
  1686. * ...
  1687. * if (TBI_ACCEPT) {
  1688. * accept_frame = true;
  1689. * e1000_tbi_adjust_stats(adapter, MacAddress);
  1690. * frame_length--;
  1691. * } else {
  1692. * accept_frame = false;
  1693. * }
  1694. * ...
  1695. */
  1696. #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
  1697. ((adapter)->tbi_compatibility_on && \
  1698. (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
  1699. ((last_byte) == CARRIER_EXTENSION) && \
  1700. (((status) & E1000_RXD_STAT_VP) ? \
  1701. (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
  1702. ((length) <= ((adapter)->max_frame_size + 1))) : \
  1703. (((length) > (adapter)->min_frame_size) && \
  1704. ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
  1705. /* Structures, enums, and macros for the PHY */
  1706. /* Bit definitions for the Management Data IO (MDIO) and Management Data
  1707. * Clock (MDC) pins in the Device Control Register.
  1708. */
  1709. #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
  1710. #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
  1711. #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
  1712. #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
  1713. #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
  1714. #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
  1715. #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
  1716. #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
  1717. /* PHY 1000 MII Register/Bit Definitions */
  1718. /* PHY Registers defined by IEEE */
  1719. #define PHY_CTRL 0x00 /* Control Register */
  1720. #define PHY_STATUS 0x01 /* Status Regiser */
  1721. #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
  1722. #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
  1723. #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
  1724. #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
  1725. #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
  1726. #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
  1727. #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
  1728. #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
  1729. #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
  1730. #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
  1731. /* M88E1000 Specific Registers */
  1732. #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
  1733. #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
  1734. #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
  1735. #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
  1736. #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
  1737. #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
  1738. #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
  1739. #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
  1740. #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
  1741. /* M88EC018 Rev 2 specific DownShift settings */
  1742. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
  1743. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
  1744. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
  1745. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
  1746. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
  1747. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
  1748. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
  1749. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
  1750. #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
  1751. /* IGP01E1000 specifics */
  1752. #define IGP01E1000_IEEE_REGS_PAGE 0x0000
  1753. #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
  1754. #define IGP01E1000_IEEE_FORCE_GIGA 0x0140
  1755. /* IGP01E1000 Specific Registers */
  1756. #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
  1757. #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
  1758. #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
  1759. #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
  1760. #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
  1761. #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
  1762. #define IGP02E1000_PHY_POWER_MGMT 0x19
  1763. #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
  1764. /* IGP01E1000 AGC Registers - stores the cable length values*/
  1765. #define IGP01E1000_PHY_AGC_A 0x1172
  1766. #define IGP01E1000_PHY_AGC_B 0x1272
  1767. #define IGP01E1000_PHY_AGC_C 0x1472
  1768. #define IGP01E1000_PHY_AGC_D 0x1872
  1769. /* IGP01E1000 Specific Port Config Register - R/W */
  1770. #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
  1771. #define IGP01E1000_PSCFR_PRE_EN 0x0020
  1772. #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
  1773. #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
  1774. #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
  1775. #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
  1776. /* IGP02E1000 AGC Registers for cable length values */
  1777. #define IGP02E1000_PHY_AGC_A 0x11B1
  1778. #define IGP02E1000_PHY_AGC_B 0x12B1
  1779. #define IGP02E1000_PHY_AGC_C 0x14B1
  1780. #define IGP02E1000_PHY_AGC_D 0x18B1
  1781. #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
  1782. #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in
  1783. non-D0a modes */
  1784. #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in
  1785. D0a mode */
  1786. /* IGP01E1000 DSP Reset Register */
  1787. #define IGP01E1000_PHY_DSP_RESET 0x1F33
  1788. #define IGP01E1000_PHY_DSP_SET 0x1F71
  1789. #define IGP01E1000_PHY_DSP_FFE 0x1F35
  1790. #define IGP01E1000_PHY_CHANNEL_NUM 4
  1791. #define IGP02E1000_PHY_CHANNEL_NUM 4
  1792. #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
  1793. #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
  1794. #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
  1795. #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
  1796. #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
  1797. #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
  1798. #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
  1799. #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
  1800. #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
  1801. #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
  1802. #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
  1803. /* IGP01E1000 PCS Initialization register - stores the polarity status when
  1804. * speed = 1000 Mbps. */
  1805. #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
  1806. #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
  1807. #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
  1808. /* IGP01E1000 GMII FIFO Register */
  1809. #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
  1810. * on Link-Up */
  1811. #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
  1812. /* IGP01E1000 Analog Register */
  1813. #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
  1814. #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
  1815. #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
  1816. #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
  1817. #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
  1818. #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
  1819. #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
  1820. #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
  1821. #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
  1822. #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
  1823. #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
  1824. #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
  1825. #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
  1826. /* IGP01E1000 Specific Port Control Register - R/W */
  1827. #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
  1828. #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
  1829. #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
  1830. #define IGP01E1000_PSCR_FLIP_CHIP 0x0800
  1831. #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
  1832. #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
  1833. /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  1834. #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
  1835. #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal
  1836. Disabled */
  1837. #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
  1838. #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter
  1839. Disabled */
  1840. #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
  1841. #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI
  1842. configuration */
  1843. #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX
  1844. configuration */
  1845. #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic
  1846. crossover */
  1847. #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended
  1848. Distance */
  1849. #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
  1850. #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
  1851. #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only
  1852. (Energy Detect) */
  1853. #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
  1854. #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
  1855. #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
  1856. #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
  1857. #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
  1858. /* PHY Specific Status Register (Page 0, Register 17) */
  1859. #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
  1860. #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
  1861. #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
  1862. #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
  1863. #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
  1864. #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
  1865. #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
  1866. #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
  1867. #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
  1868. #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
  1869. #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
  1870. #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
  1871. #define GG82563_PSSR_SPEED_MASK 0xC000
  1872. #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
  1873. #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
  1874. #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
  1875. /* PHY Specific Status Register 2 (Page 0, Register 19) */
  1876. #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
  1877. #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
  1878. #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
  1879. #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
  1880. #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
  1881. #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */
  1882. #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
  1883. #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
  1884. #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
  1885. #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
  1886. #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
  1887. #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
  1888. #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
  1889. /* PHY Specific Control Register 2 (Page 0, Register 26) */
  1890. #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative
  1891. Polarity */
  1892. #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
  1893. #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal
  1894. Operation */
  1895. #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns
  1896. Sequence */
  1897. #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns
  1898. Sequence */
  1899. #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse
  1900. Auto-Negotiation */
  1901. #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable
  1902. 1000BASE-T */
  1903. #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
  1904. #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
  1905. #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
  1906. /* MAC Specific Control Register (Page 2, Register 21) */
  1907. /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  1908. #define GG82563_MSCR_TX_CLK_MASK 0x0007
  1909. #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
  1910. #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
  1911. #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
  1912. #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
  1913. #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
  1914. /* DSP Distance Register (Page 5, Register 26) */
  1915. #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
  1916. 1 = 50-80M;
  1917. 2 = 80-110M;
  1918. 3 = 110-140M;
  1919. 4 = >140M */
  1920. /* Kumeran Mode Control Register (Page 193, Register 16) */
  1921. #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs,
  1922. 0=Kumeran Inband LEDs */
  1923. #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
  1924. #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
  1925. #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
  1926. #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz,
  1927. 0=0.8MHz */
  1928. #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
  1929. /* Power Management Control Register (Page 193, Register 20) */
  1930. #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES
  1931. Electrical Idle */
  1932. #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
  1933. #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
  1934. #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse
  1935. Auto-Negotiation */
  1936. #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps
  1937. Auto-Neg in non D0 */
  1938. #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps
  1939. Auto-Neg Always */
  1940. #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a
  1941. Reverse Auto-Negotiation */
  1942. #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
  1943. #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
  1944. #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
  1945. #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
  1946. #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
  1947. #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
  1948. /* In-Band Control Register (Page 194, Register 18) */
  1949. #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
  1950. /* Bits...
  1951. * 15-5: page
  1952. * 4-0: register offset
  1953. */
  1954. #define GG82563_PAGE_SHIFT 5
  1955. #define GG82563_REG(page, reg) \
  1956. (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
  1957. #define GG82563_MIN_ALT_REG 30
  1958. /* GG82563 Specific Registers */
  1959. #define GG82563_PHY_SPEC_CTRL \
  1960. GG82563_REG(0, 16) /* PHY Specific Control */
  1961. #define GG82563_PHY_SPEC_STATUS \
  1962. GG82563_REG(0, 17) /* PHY Specific Status */
  1963. #define GG82563_PHY_INT_ENABLE \
  1964. GG82563_REG(0, 18) /* Interrupt Enable */
  1965. #define GG82563_PHY_SPEC_STATUS_2 \
  1966. GG82563_REG(0, 19) /* PHY Specific Status 2 */
  1967. #define GG82563_PHY_RX_ERR_CNTR \
  1968. GG82563_REG(0, 21) /* Receive Error Counter */
  1969. #define GG82563_PHY_PAGE_SELECT \
  1970. GG82563_REG(0, 22) /* Page Select */
  1971. #define GG82563_PHY_SPEC_CTRL_2 \
  1972. GG82563_REG(0, 26) /* PHY Specific Control 2 */
  1973. #define GG82563_PHY_PAGE_SELECT_ALT \
  1974. GG82563_REG(0, 29) /* Alternate Page Select */
  1975. #define GG82563_PHY_TEST_CLK_CTRL \
  1976. GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
  1977. #define GG82563_PHY_MAC_SPEC_CTRL \
  1978. GG82563_REG(2, 21) /* MAC Specific Control Register */
  1979. #define GG82563_PHY_MAC_SPEC_CTRL_2 \
  1980. GG82563_REG(2, 26) /* MAC Specific Control 2 */
  1981. #define GG82563_PHY_DSP_DISTANCE \
  1982. GG82563_REG(5, 26) /* DSP Distance */
  1983. /* Page 193 - Port Control Registers */
  1984. #define GG82563_PHY_KMRN_MODE_CTRL \
  1985. GG82563_REG(193, 16) /* Kumeran Mode Control */
  1986. #define GG82563_PHY_PORT_RESET \
  1987. GG82563_REG(193, 17) /* Port Reset */
  1988. #define GG82563_PHY_REVISION_ID \
  1989. GG82563_REG(193, 18) /* Revision ID */
  1990. #define GG82563_PHY_DEVICE_ID \
  1991. GG82563_REG(193, 19) /* Device ID */
  1992. #define GG82563_PHY_PWR_MGMT_CTRL \
  1993. GG82563_REG(193, 20) /* Power Management Control */
  1994. #define GG82563_PHY_RATE_ADAPT_CTRL \
  1995. GG82563_REG(193, 25) /* Rate Adaptation Control */
  1996. /* Page 194 - KMRN Registers */
  1997. #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
  1998. GG82563_REG(194, 16) /* FIFO's Control/Status */
  1999. #define GG82563_PHY_KMRN_CTRL \
  2000. GG82563_REG(194, 17) /* Control */
  2001. #define GG82563_PHY_INBAND_CTRL \
  2002. GG82563_REG(194, 18) /* Inband Control */
  2003. #define GG82563_PHY_KMRN_DIAGNOSTIC \
  2004. GG82563_REG(194, 19) /* Diagnostic */
  2005. #define GG82563_PHY_ACK_TIMEOUTS \
  2006. GG82563_REG(194, 20) /* Acknowledge Timeouts */
  2007. #define GG82563_PHY_ADV_ABILITY \
  2008. GG82563_REG(194, 21) /* Advertised Ability */
  2009. #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
  2010. GG82563_REG(194, 23) /* Link Partner Advertised Ability */
  2011. #define GG82563_PHY_ADV_NEXT_PAGE \
  2012. GG82563_REG(194, 24) /* Advertised Next Page */
  2013. #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
  2014. GG82563_REG(194, 25) /* Link Partner Advertised Next page */
  2015. #define GG82563_PHY_KMRN_MISC \
  2016. GG82563_REG(194, 26) /* Misc. */
  2017. /* PHY Control Register */
  2018. #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
  2019. #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
  2020. #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
  2021. #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
  2022. #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
  2023. #define MII_CR_POWER_DOWN 0x0800 /* Power down */
  2024. #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
  2025. #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
  2026. #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
  2027. #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
  2028. /* PHY Status Register */
  2029. #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
  2030. #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
  2031. #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
  2032. #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
  2033. #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
  2034. #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
  2035. #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
  2036. #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
  2037. #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
  2038. #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
  2039. #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
  2040. #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
  2041. #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
  2042. #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
  2043. #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
  2044. /* Autoneg Advertisement Register */
  2045. #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
  2046. #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
  2047. #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
  2048. #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
  2049. #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
  2050. #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
  2051. #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
  2052. #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
  2053. #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
  2054. #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
  2055. /* Link Partner Ability Register (Base Page) */
  2056. #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
  2057. #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
  2058. #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
  2059. #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
  2060. #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
  2061. #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
  2062. #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
  2063. #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
  2064. #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
  2065. #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
  2066. #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
  2067. /* Autoneg Expansion Register */
  2068. #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
  2069. #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
  2070. #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
  2071. #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
  2072. #define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
  2073. /* Next Page TX Register */
  2074. #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
  2075. #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
  2076. * of different NP
  2077. */
  2078. #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
  2079. * 0 = cannot comply with msg
  2080. */
  2081. #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
  2082. #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
  2083. * 0 = sending last NP
  2084. */
  2085. /* Link Partner Next Page Register */
  2086. #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
  2087. #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
  2088. * of different NP
  2089. */
  2090. #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
  2091. * 0 = cannot comply with msg
  2092. */
  2093. #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
  2094. #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
  2095. #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
  2096. * 0 = sending last NP
  2097. */
  2098. /* 1000BASE-T Control Register */
  2099. #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
  2100. #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
  2101. #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
  2102. #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
  2103. /* 0=DTE device */
  2104. #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
  2105. /* 0=Configure PHY as Slave */
  2106. #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
  2107. /* 0=Automatic Master/Slave config */
  2108. #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
  2109. #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
  2110. #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
  2111. #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
  2112. #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
  2113. /* 1000BASE-T Status Register */
  2114. #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
  2115. #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
  2116. #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
  2117. #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
  2118. #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
  2119. #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
  2120. #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
  2121. #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
  2122. #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
  2123. #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
  2124. /* Extended Status Register */
  2125. #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
  2126. #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
  2127. #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
  2128. #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
  2129. #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
  2130. #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
  2131. #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
  2132. /* (0=enable, 1=disable) */
  2133. /* M88E1000 PHY Specific Control Register */
  2134. #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
  2135. #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
  2136. #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
  2137. #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
  2138. * 0=CLK125 toggling
  2139. */
  2140. #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
  2141. /* Manual MDI configuration */
  2142. #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
  2143. #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
  2144. * 100BASE-TX/10BASE-T:
  2145. * MDI Mode
  2146. */
  2147. #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
  2148. * all speeds.
  2149. */
  2150. #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
  2151. /* 1=Enable Extended 10BASE-T distance
  2152. * (Lower 10BASE-T RX Threshold)
  2153. * 0=Normal 10BASE-T RX Threshold */
  2154. #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
  2155. /* 1=5-Bit interface in 100BASE-TX
  2156. * 0=MII interface in 100BASE-TX */
  2157. #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
  2158. #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
  2159. #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
  2160. #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
  2161. #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
  2162. #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
  2163. /* M88E1000 PHY Specific Status Register */
  2164. #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
  2165. #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
  2166. #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
  2167. #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
  2168. * 3=110-140M;4=>140M */
  2169. #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
  2170. #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
  2171. #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
  2172. #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
  2173. #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
  2174. #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
  2175. #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
  2176. #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
  2177. #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
  2178. #define M88E1000_PSSR_MDIX_SHIFT 6
  2179. #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
  2180. /* M88E1000 Extended PHY Specific Control Register */
  2181. #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
  2182. #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
  2183. * Will assert lost lock and bring
  2184. * link down if idle not seen
  2185. * within 1ms in 1000BASE-T
  2186. */
  2187. /* Number of times we will attempt to autonegotiate before downshifting if we
  2188. * are the master */
  2189. #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
  2190. #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
  2191. #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
  2192. #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
  2193. #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
  2194. /* Number of times we will attempt to autonegotiate before downshifting if we
  2195. * are the slave */
  2196. #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
  2197. #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
  2198. #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
  2199. #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
  2200. #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
  2201. #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
  2202. #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
  2203. #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
  2204. /* Bit definitions for valid PHY IDs. */
  2205. #define M88E1000_E_PHY_ID 0x01410C50
  2206. #define M88E1000_I_PHY_ID 0x01410C30
  2207. #define M88E1011_I_PHY_ID 0x01410C20
  2208. #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
  2209. #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
  2210. #define IGP01E1000_I_PHY_ID 0x02A80380
  2211. #define M88E1011_I_REV_4 0x04
  2212. #define M88E1111_I_PHY_ID 0x01410CC0
  2213. #define L1LXT971A_PHY_ID 0x001378E0
  2214. #define GG82563_E_PHY_ID 0x01410CA0
  2215. #define BME1000_E_PHY_ID 0x01410CB0
  2216. #define I210_I_PHY_ID 0x01410C00
  2217. /* Miscellaneous PHY bit definitions. */
  2218. #define PHY_PREAMBLE 0xFFFFFFFF
  2219. #define PHY_SOF 0x01
  2220. #define PHY_OP_READ 0x02
  2221. #define PHY_OP_WRITE 0x01
  2222. #define PHY_TURNAROUND 0x02
  2223. #define PHY_PREAMBLE_SIZE 32
  2224. #define MII_CR_SPEED_1000 0x0040
  2225. #define MII_CR_SPEED_100 0x2000
  2226. #define MII_CR_SPEED_10 0x0000
  2227. #define E1000_PHY_ADDRESS 0x01
  2228. #define PHY_AUTO_NEG_TIME 80 /* 8.0 Seconds */
  2229. #define PHY_FORCE_TIME 20 /* 2.0 Seconds */
  2230. #define PHY_REVISION_MASK 0xFFFFFFF0
  2231. #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
  2232. #define REG4_SPEED_MASK 0x01E0
  2233. #define REG9_SPEED_MASK 0x0300
  2234. #define ADVERTISE_10_HALF 0x0001
  2235. #define ADVERTISE_10_FULL 0x0002
  2236. #define ADVERTISE_100_HALF 0x0004
  2237. #define ADVERTISE_100_FULL 0x0008
  2238. #define ADVERTISE_1000_HALF 0x0010
  2239. #define ADVERTISE_1000_FULL 0x0020
  2240. #define ICH_FLASH_GFPREG 0x0000
  2241. #define ICH_FLASH_HSFSTS 0x0004
  2242. #define ICH_FLASH_HSFCTL 0x0006
  2243. #define ICH_FLASH_FADDR 0x0008
  2244. #define ICH_FLASH_FDATA0 0x0010
  2245. #define ICH_FLASH_FRACC 0x0050
  2246. #define ICH_FLASH_FREG0 0x0054
  2247. #define ICH_FLASH_FREG1 0x0058
  2248. #define ICH_FLASH_FREG2 0x005C
  2249. #define ICH_FLASH_FREG3 0x0060
  2250. #define ICH_FLASH_FPR0 0x0074
  2251. #define ICH_FLASH_FPR1 0x0078
  2252. #define ICH_FLASH_SSFSTS 0x0090
  2253. #define ICH_FLASH_SSFCTL 0x0092
  2254. #define ICH_FLASH_PREOP 0x0094
  2255. #define ICH_FLASH_OPTYPE 0x0096
  2256. #define ICH_FLASH_OPMENU 0x0098
  2257. #define ICH_FLASH_REG_MAPSIZE 0x00A0
  2258. #define ICH_FLASH_SECTOR_SIZE 4096
  2259. #define ICH_GFPREG_BASE_MASK 0x1FFF
  2260. #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
  2261. #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
  2262. /* SPI EEPROM Status Register */
  2263. #define EEPROM_STATUS_RDY_SPI 0x01
  2264. #define EEPROM_STATUS_WEN_SPI 0x02
  2265. #define EEPROM_STATUS_BP0_SPI 0x04
  2266. #define EEPROM_STATUS_BP1_SPI 0x08
  2267. #define EEPROM_STATUS_WPEN_SPI 0x80
  2268. /* SW Semaphore Register */
  2269. #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
  2270. #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
  2271. #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
  2272. #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
  2273. /* FW Semaphore Register */
  2274. #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
  2275. #define E1000_FWSM_MODE_SHIFT 1
  2276. #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
  2277. #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
  2278. #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
  2279. #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
  2280. #define E1000_FWSM_SKUEL_SHIFT 29
  2281. #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
  2282. #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
  2283. #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
  2284. #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
  2285. #define E1000_GCR 0x05B00 /* PCI-Ex Control */
  2286. #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
  2287. #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
  2288. #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
  2289. #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
  2290. #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
  2291. #define E1000_SWSM 0x05B50 /* SW Semaphore */
  2292. #define E1000_FWSM 0x05B54 /* FW Semaphore */
  2293. #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
  2294. #define E1000_HICR 0x08F00 /* Host Inteface Control */
  2295. #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
  2296. #define IGP_ACTIVITY_LED_ENABLE 0x0300
  2297. #define IGP_LED3_MODE 0x07000000
  2298. /* Mask bit for PHY class in Word 7 of the EEPROM */
  2299. #define EEPROM_PHY_CLASS_A 0x8000
  2300. #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
  2301. #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
  2302. #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
  2303. #define E1000_KUMCTRLSTA_MASK 0x0000FFFF
  2304. #define E1000_KUMCTRLSTA_OFFSET 0x001F0000
  2305. #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
  2306. #define E1000_KUMCTRLSTA_REN 0x00200000
  2307. #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
  2308. #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
  2309. #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
  2310. #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
  2311. #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
  2312. #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
  2313. #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
  2314. #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
  2315. #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
  2316. /* FIFO Control */
  2317. #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
  2318. #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
  2319. /* In-Band Control */
  2320. #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
  2321. #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
  2322. /* Half-Duplex Control */
  2323. #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
  2324. #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
  2325. #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
  2326. #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
  2327. #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
  2328. #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
  2329. #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
  2330. #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
  2331. #define E1000_MNG_ICH_IAMT_MODE 0x2
  2332. #define E1000_MNG_IAMT_MODE 0x3
  2333. #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
  2334. #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
  2335. /* Number of milliseconds we wait for PHY configuration done after MAC reset */
  2336. #define PHY_CFG_TIMEOUT 100
  2337. #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
  2338. #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
  2339. #define AUTO_ALL_MODES 0
  2340. #ifndef E1000_MASTER_SLAVE
  2341. /* Switch to override PHY master/slave setting */
  2342. #define E1000_MASTER_SLAVE e1000_ms_hw_default
  2343. #endif
  2344. /* Extended Transmit Control */
  2345. #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
  2346. #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  2347. #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
  2348. #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
  2349. #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  2350. #define E1000_MC_TBL_SIZE_ICH8LAN 32
  2351. #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers
  2352. after IMS clear */
  2353. #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
  2354. #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
  2355. #endif /* _E1000_HW_H_ */