e1000.c 171 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**************************************************************************
  3. Intel Pro 1000 for ppcboot/das-u-boot
  4. Drivers are port from Intel's Linux driver e1000-4.3.15
  5. and from Etherboot pro 1000 driver by mrakes at vivato dot net
  6. tested on both gig copper and gig fiber boards
  7. ***************************************************************************/
  8. /*******************************************************************************
  9. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  10. Contact Information:
  11. Linux NICS <linux.nics@intel.com>
  12. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  13. *******************************************************************************/
  14. /*
  15. * Copyright (C) Archway Digital Solutions.
  16. *
  17. * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  18. * 2/9/2002
  19. *
  20. * Copyright (C) Linux Networx.
  21. * Massive upgrade to work with the new intel gigabit NICs.
  22. * <ebiederman at lnxi dot com>
  23. *
  24. * Copyright 2011 Freescale Semiconductor, Inc.
  25. */
  26. #include <common.h>
  27. #include <command.h>
  28. #include <cpu_func.h>
  29. #include <dm.h>
  30. #include <errno.h>
  31. #include <log.h>
  32. #include <malloc.h>
  33. #include <memalign.h>
  34. #include <net.h>
  35. #include <pci.h>
  36. #include <linux/delay.h>
  37. #include "e1000.h"
  38. #include <asm/cache.h>
  39. #define TOUT_LOOP 100000
  40. #ifdef CONFIG_DM_ETH
  41. #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
  42. #define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a)
  43. #else
  44. #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
  45. #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
  46. #endif
  47. #define E1000_DEFAULT_PCI_PBA 0x00000030
  48. #define E1000_DEFAULT_PCIE_PBA 0x000a0026
  49. /* NIC specific static variables go here */
  50. /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  51. #define E1000_BUFFER_ALIGN 128
  52. /*
  53. * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  54. * Concurrent receiving on multiple active Ethernet devices will not work.
  55. * Normally U-Boot does not support this anyway. To fix it in this driver,
  56. * move these buffers and the tx/rx pointers to struct e1000_hw.
  57. */
  58. DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  59. DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  60. DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  61. static int tx_tail;
  62. static int rx_tail, rx_last;
  63. #ifdef CONFIG_DM_ETH
  64. static int num_cards; /* Number of E1000 devices seen so far */
  65. #endif
  66. static struct pci_device_id e1000_supported[] = {
  67. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  68. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  69. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  70. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  71. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  73. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  74. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  76. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  77. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  78. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  79. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  80. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  81. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  82. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  83. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  84. /* E1000 PCIe card */
  85. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  86. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
  87. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
  88. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
  89. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
  90. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
  91. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
  92. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
  93. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
  94. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
  95. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
  96. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
  97. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
  98. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
  99. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
  100. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
  101. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
  102. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
  103. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
  104. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
  105. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
  106. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
  107. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
  108. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
  109. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
  110. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
  111. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
  112. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
  113. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
  114. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
  115. {}
  116. };
  117. /* Function forward declarations */
  118. static int e1000_setup_link(struct e1000_hw *hw);
  119. static int e1000_setup_fiber_link(struct e1000_hw *hw);
  120. static int e1000_setup_copper_link(struct e1000_hw *hw);
  121. static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
  122. static void e1000_config_collision_dist(struct e1000_hw *hw);
  123. static int e1000_config_mac_to_phy(struct e1000_hw *hw);
  124. static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
  125. static int e1000_check_for_link(struct e1000_hw *hw);
  126. static int e1000_wait_autoneg(struct e1000_hw *hw);
  127. static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
  128. uint16_t * duplex);
  129. static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  130. uint16_t * phy_data);
  131. static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  132. uint16_t phy_data);
  133. static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
  134. static int e1000_phy_reset(struct e1000_hw *hw);
  135. static int e1000_detect_gig_phy(struct e1000_hw *hw);
  136. static void e1000_set_media_type(struct e1000_hw *hw);
  137. static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
  138. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
  139. static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
  140. #ifndef CONFIG_E1000_NO_NVM
  141. static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
  142. static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
  143. static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  144. uint16_t words,
  145. uint16_t *data);
  146. /******************************************************************************
  147. * Raises the EEPROM's clock input.
  148. *
  149. * hw - Struct containing variables accessed by shared code
  150. * eecd - EECD's current value
  151. *****************************************************************************/
  152. void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  153. {
  154. /* Raise the clock input to the EEPROM (by setting the SK bit), and then
  155. * wait 50 microseconds.
  156. */
  157. *eecd = *eecd | E1000_EECD_SK;
  158. E1000_WRITE_REG(hw, EECD, *eecd);
  159. E1000_WRITE_FLUSH(hw);
  160. udelay(50);
  161. }
  162. /******************************************************************************
  163. * Lowers the EEPROM's clock input.
  164. *
  165. * hw - Struct containing variables accessed by shared code
  166. * eecd - EECD's current value
  167. *****************************************************************************/
  168. void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  169. {
  170. /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
  171. * wait 50 microseconds.
  172. */
  173. *eecd = *eecd & ~E1000_EECD_SK;
  174. E1000_WRITE_REG(hw, EECD, *eecd);
  175. E1000_WRITE_FLUSH(hw);
  176. udelay(50);
  177. }
  178. /******************************************************************************
  179. * Shift data bits out to the EEPROM.
  180. *
  181. * hw - Struct containing variables accessed by shared code
  182. * data - data to send to the EEPROM
  183. * count - number of bits to shift out
  184. *****************************************************************************/
  185. static void
  186. e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
  187. {
  188. uint32_t eecd;
  189. uint32_t mask;
  190. /* We need to shift "count" bits out to the EEPROM. So, value in the
  191. * "data" parameter will be shifted out to the EEPROM one bit at a time.
  192. * In order to do this, "data" must be broken down into bits.
  193. */
  194. mask = 0x01 << (count - 1);
  195. eecd = E1000_READ_REG(hw, EECD);
  196. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  197. do {
  198. /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  199. * and then raising and then lowering the clock (the SK bit controls
  200. * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
  201. * by setting "DI" to "0" and then raising and then lowering the clock.
  202. */
  203. eecd &= ~E1000_EECD_DI;
  204. if (data & mask)
  205. eecd |= E1000_EECD_DI;
  206. E1000_WRITE_REG(hw, EECD, eecd);
  207. E1000_WRITE_FLUSH(hw);
  208. udelay(50);
  209. e1000_raise_ee_clk(hw, &eecd);
  210. e1000_lower_ee_clk(hw, &eecd);
  211. mask = mask >> 1;
  212. } while (mask);
  213. /* We leave the "DI" bit set to "0" when we leave this routine. */
  214. eecd &= ~E1000_EECD_DI;
  215. E1000_WRITE_REG(hw, EECD, eecd);
  216. }
  217. /******************************************************************************
  218. * Shift data bits in from the EEPROM
  219. *
  220. * hw - Struct containing variables accessed by shared code
  221. *****************************************************************************/
  222. static uint16_t
  223. e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
  224. {
  225. uint32_t eecd;
  226. uint32_t i;
  227. uint16_t data;
  228. /* In order to read a register from the EEPROM, we need to shift 'count'
  229. * bits in from the EEPROM. Bits are "shifted in" by raising the clock
  230. * input to the EEPROM (setting the SK bit), and then reading the
  231. * value of the "DO" bit. During this "shifting in" process the
  232. * "DI" bit should always be clear.
  233. */
  234. eecd = E1000_READ_REG(hw, EECD);
  235. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  236. data = 0;
  237. for (i = 0; i < count; i++) {
  238. data = data << 1;
  239. e1000_raise_ee_clk(hw, &eecd);
  240. eecd = E1000_READ_REG(hw, EECD);
  241. eecd &= ~(E1000_EECD_DI);
  242. if (eecd & E1000_EECD_DO)
  243. data |= 1;
  244. e1000_lower_ee_clk(hw, &eecd);
  245. }
  246. return data;
  247. }
  248. /******************************************************************************
  249. * Returns EEPROM to a "standby" state
  250. *
  251. * hw - Struct containing variables accessed by shared code
  252. *****************************************************************************/
  253. void e1000_standby_eeprom(struct e1000_hw *hw)
  254. {
  255. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  256. uint32_t eecd;
  257. eecd = E1000_READ_REG(hw, EECD);
  258. if (eeprom->type == e1000_eeprom_microwire) {
  259. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  260. E1000_WRITE_REG(hw, EECD, eecd);
  261. E1000_WRITE_FLUSH(hw);
  262. udelay(eeprom->delay_usec);
  263. /* Clock high */
  264. eecd |= E1000_EECD_SK;
  265. E1000_WRITE_REG(hw, EECD, eecd);
  266. E1000_WRITE_FLUSH(hw);
  267. udelay(eeprom->delay_usec);
  268. /* Select EEPROM */
  269. eecd |= E1000_EECD_CS;
  270. E1000_WRITE_REG(hw, EECD, eecd);
  271. E1000_WRITE_FLUSH(hw);
  272. udelay(eeprom->delay_usec);
  273. /* Clock low */
  274. eecd &= ~E1000_EECD_SK;
  275. E1000_WRITE_REG(hw, EECD, eecd);
  276. E1000_WRITE_FLUSH(hw);
  277. udelay(eeprom->delay_usec);
  278. } else if (eeprom->type == e1000_eeprom_spi) {
  279. /* Toggle CS to flush commands */
  280. eecd |= E1000_EECD_CS;
  281. E1000_WRITE_REG(hw, EECD, eecd);
  282. E1000_WRITE_FLUSH(hw);
  283. udelay(eeprom->delay_usec);
  284. eecd &= ~E1000_EECD_CS;
  285. E1000_WRITE_REG(hw, EECD, eecd);
  286. E1000_WRITE_FLUSH(hw);
  287. udelay(eeprom->delay_usec);
  288. }
  289. }
  290. /***************************************************************************
  291. * Description: Determines if the onboard NVM is FLASH or EEPROM.
  292. *
  293. * hw - Struct containing variables accessed by shared code
  294. ****************************************************************************/
  295. static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
  296. {
  297. uint32_t eecd = 0;
  298. DEBUGFUNC();
  299. if (hw->mac_type == e1000_ich8lan)
  300. return false;
  301. if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
  302. eecd = E1000_READ_REG(hw, EECD);
  303. /* Isolate bits 15 & 16 */
  304. eecd = ((eecd >> 15) & 0x03);
  305. /* If both bits are set, device is Flash type */
  306. if (eecd == 0x03)
  307. return false;
  308. }
  309. return true;
  310. }
  311. /******************************************************************************
  312. * Prepares EEPROM for access
  313. *
  314. * hw - Struct containing variables accessed by shared code
  315. *
  316. * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  317. * function should be called before issuing a command to the EEPROM.
  318. *****************************************************************************/
  319. int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
  320. {
  321. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  322. uint32_t eecd, i = 0;
  323. DEBUGFUNC();
  324. if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
  325. return -E1000_ERR_SWFW_SYNC;
  326. eecd = E1000_READ_REG(hw, EECD);
  327. if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
  328. /* Request EEPROM Access */
  329. if (hw->mac_type > e1000_82544) {
  330. eecd |= E1000_EECD_REQ;
  331. E1000_WRITE_REG(hw, EECD, eecd);
  332. eecd = E1000_READ_REG(hw, EECD);
  333. while ((!(eecd & E1000_EECD_GNT)) &&
  334. (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
  335. i++;
  336. udelay(5);
  337. eecd = E1000_READ_REG(hw, EECD);
  338. }
  339. if (!(eecd & E1000_EECD_GNT)) {
  340. eecd &= ~E1000_EECD_REQ;
  341. E1000_WRITE_REG(hw, EECD, eecd);
  342. DEBUGOUT("Could not acquire EEPROM grant\n");
  343. return -E1000_ERR_EEPROM;
  344. }
  345. }
  346. }
  347. /* Setup EEPROM for Read/Write */
  348. if (eeprom->type == e1000_eeprom_microwire) {
  349. /* Clear SK and DI */
  350. eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  351. E1000_WRITE_REG(hw, EECD, eecd);
  352. /* Set CS */
  353. eecd |= E1000_EECD_CS;
  354. E1000_WRITE_REG(hw, EECD, eecd);
  355. } else if (eeprom->type == e1000_eeprom_spi) {
  356. /* Clear SK and CS */
  357. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  358. E1000_WRITE_REG(hw, EECD, eecd);
  359. udelay(1);
  360. }
  361. return E1000_SUCCESS;
  362. }
  363. /******************************************************************************
  364. * Sets up eeprom variables in the hw struct. Must be called after mac_type
  365. * is configured. Additionally, if this is ICH8, the flash controller GbE
  366. * registers must be mapped, or this will crash.
  367. *
  368. * hw - Struct containing variables accessed by shared code
  369. *****************************************************************************/
  370. static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
  371. {
  372. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  373. uint32_t eecd;
  374. int32_t ret_val = E1000_SUCCESS;
  375. uint16_t eeprom_size;
  376. if (hw->mac_type == e1000_igb)
  377. eecd = E1000_READ_REG(hw, I210_EECD);
  378. else
  379. eecd = E1000_READ_REG(hw, EECD);
  380. DEBUGFUNC();
  381. switch (hw->mac_type) {
  382. case e1000_82542_rev2_0:
  383. case e1000_82542_rev2_1:
  384. case e1000_82543:
  385. case e1000_82544:
  386. eeprom->type = e1000_eeprom_microwire;
  387. eeprom->word_size = 64;
  388. eeprom->opcode_bits = 3;
  389. eeprom->address_bits = 6;
  390. eeprom->delay_usec = 50;
  391. eeprom->use_eerd = false;
  392. eeprom->use_eewr = false;
  393. break;
  394. case e1000_82540:
  395. case e1000_82545:
  396. case e1000_82545_rev_3:
  397. case e1000_82546:
  398. case e1000_82546_rev_3:
  399. eeprom->type = e1000_eeprom_microwire;
  400. eeprom->opcode_bits = 3;
  401. eeprom->delay_usec = 50;
  402. if (eecd & E1000_EECD_SIZE) {
  403. eeprom->word_size = 256;
  404. eeprom->address_bits = 8;
  405. } else {
  406. eeprom->word_size = 64;
  407. eeprom->address_bits = 6;
  408. }
  409. eeprom->use_eerd = false;
  410. eeprom->use_eewr = false;
  411. break;
  412. case e1000_82541:
  413. case e1000_82541_rev_2:
  414. case e1000_82547:
  415. case e1000_82547_rev_2:
  416. if (eecd & E1000_EECD_TYPE) {
  417. eeprom->type = e1000_eeprom_spi;
  418. eeprom->opcode_bits = 8;
  419. eeprom->delay_usec = 1;
  420. if (eecd & E1000_EECD_ADDR_BITS) {
  421. eeprom->page_size = 32;
  422. eeprom->address_bits = 16;
  423. } else {
  424. eeprom->page_size = 8;
  425. eeprom->address_bits = 8;
  426. }
  427. } else {
  428. eeprom->type = e1000_eeprom_microwire;
  429. eeprom->opcode_bits = 3;
  430. eeprom->delay_usec = 50;
  431. if (eecd & E1000_EECD_ADDR_BITS) {
  432. eeprom->word_size = 256;
  433. eeprom->address_bits = 8;
  434. } else {
  435. eeprom->word_size = 64;
  436. eeprom->address_bits = 6;
  437. }
  438. }
  439. eeprom->use_eerd = false;
  440. eeprom->use_eewr = false;
  441. break;
  442. case e1000_82571:
  443. case e1000_82572:
  444. eeprom->type = e1000_eeprom_spi;
  445. eeprom->opcode_bits = 8;
  446. eeprom->delay_usec = 1;
  447. if (eecd & E1000_EECD_ADDR_BITS) {
  448. eeprom->page_size = 32;
  449. eeprom->address_bits = 16;
  450. } else {
  451. eeprom->page_size = 8;
  452. eeprom->address_bits = 8;
  453. }
  454. eeprom->use_eerd = false;
  455. eeprom->use_eewr = false;
  456. break;
  457. case e1000_82573:
  458. case e1000_82574:
  459. eeprom->type = e1000_eeprom_spi;
  460. eeprom->opcode_bits = 8;
  461. eeprom->delay_usec = 1;
  462. if (eecd & E1000_EECD_ADDR_BITS) {
  463. eeprom->page_size = 32;
  464. eeprom->address_bits = 16;
  465. } else {
  466. eeprom->page_size = 8;
  467. eeprom->address_bits = 8;
  468. }
  469. if (e1000_is_onboard_nvm_eeprom(hw) == false) {
  470. eeprom->use_eerd = true;
  471. eeprom->use_eewr = true;
  472. eeprom->type = e1000_eeprom_flash;
  473. eeprom->word_size = 2048;
  474. /* Ensure that the Autonomous FLASH update bit is cleared due to
  475. * Flash update issue on parts which use a FLASH for NVM. */
  476. eecd &= ~E1000_EECD_AUPDEN;
  477. E1000_WRITE_REG(hw, EECD, eecd);
  478. }
  479. break;
  480. case e1000_80003es2lan:
  481. eeprom->type = e1000_eeprom_spi;
  482. eeprom->opcode_bits = 8;
  483. eeprom->delay_usec = 1;
  484. if (eecd & E1000_EECD_ADDR_BITS) {
  485. eeprom->page_size = 32;
  486. eeprom->address_bits = 16;
  487. } else {
  488. eeprom->page_size = 8;
  489. eeprom->address_bits = 8;
  490. }
  491. eeprom->use_eerd = true;
  492. eeprom->use_eewr = false;
  493. break;
  494. case e1000_igb:
  495. /* i210 has 4k of iNVM mapped as EEPROM */
  496. eeprom->type = e1000_eeprom_invm;
  497. eeprom->opcode_bits = 8;
  498. eeprom->delay_usec = 1;
  499. eeprom->page_size = 32;
  500. eeprom->address_bits = 16;
  501. eeprom->use_eerd = true;
  502. eeprom->use_eewr = false;
  503. break;
  504. default:
  505. break;
  506. }
  507. if (eeprom->type == e1000_eeprom_spi ||
  508. eeprom->type == e1000_eeprom_invm) {
  509. /* eeprom_size will be an enum [0..8] that maps
  510. * to eeprom sizes 128B to
  511. * 32KB (incremented by powers of 2).
  512. */
  513. if (hw->mac_type <= e1000_82547_rev_2) {
  514. /* Set to default value for initial eeprom read. */
  515. eeprom->word_size = 64;
  516. ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
  517. &eeprom_size);
  518. if (ret_val)
  519. return ret_val;
  520. eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
  521. >> EEPROM_SIZE_SHIFT;
  522. /* 256B eeprom size was not supported in earlier
  523. * hardware, so we bump eeprom_size up one to
  524. * ensure that "1" (which maps to 256B) is never
  525. * the result used in the shifting logic below. */
  526. if (eeprom_size)
  527. eeprom_size++;
  528. } else {
  529. eeprom_size = (uint16_t)((eecd &
  530. E1000_EECD_SIZE_EX_MASK) >>
  531. E1000_EECD_SIZE_EX_SHIFT);
  532. }
  533. eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
  534. }
  535. return ret_val;
  536. }
  537. /******************************************************************************
  538. * Polls the status bit (bit 1) of the EERD to determine when the read is done.
  539. *
  540. * hw - Struct containing variables accessed by shared code
  541. *****************************************************************************/
  542. static int32_t
  543. e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
  544. {
  545. uint32_t attempts = 100000;
  546. uint32_t i, reg = 0;
  547. int32_t done = E1000_ERR_EEPROM;
  548. for (i = 0; i < attempts; i++) {
  549. if (eerd == E1000_EEPROM_POLL_READ) {
  550. if (hw->mac_type == e1000_igb)
  551. reg = E1000_READ_REG(hw, I210_EERD);
  552. else
  553. reg = E1000_READ_REG(hw, EERD);
  554. } else {
  555. if (hw->mac_type == e1000_igb)
  556. reg = E1000_READ_REG(hw, I210_EEWR);
  557. else
  558. reg = E1000_READ_REG(hw, EEWR);
  559. }
  560. if (reg & E1000_EEPROM_RW_REG_DONE) {
  561. done = E1000_SUCCESS;
  562. break;
  563. }
  564. udelay(5);
  565. }
  566. return done;
  567. }
  568. /******************************************************************************
  569. * Reads a 16 bit word from the EEPROM using the EERD register.
  570. *
  571. * hw - Struct containing variables accessed by shared code
  572. * offset - offset of word in the EEPROM to read
  573. * data - word read from the EEPROM
  574. * words - number of words to read
  575. *****************************************************************************/
  576. static int32_t
  577. e1000_read_eeprom_eerd(struct e1000_hw *hw,
  578. uint16_t offset,
  579. uint16_t words,
  580. uint16_t *data)
  581. {
  582. uint32_t i, eerd = 0;
  583. int32_t error = 0;
  584. for (i = 0; i < words; i++) {
  585. eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
  586. E1000_EEPROM_RW_REG_START;
  587. if (hw->mac_type == e1000_igb)
  588. E1000_WRITE_REG(hw, I210_EERD, eerd);
  589. else
  590. E1000_WRITE_REG(hw, EERD, eerd);
  591. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
  592. if (error)
  593. break;
  594. if (hw->mac_type == e1000_igb) {
  595. data[i] = (E1000_READ_REG(hw, I210_EERD) >>
  596. E1000_EEPROM_RW_REG_DATA);
  597. } else {
  598. data[i] = (E1000_READ_REG(hw, EERD) >>
  599. E1000_EEPROM_RW_REG_DATA);
  600. }
  601. }
  602. return error;
  603. }
  604. void e1000_release_eeprom(struct e1000_hw *hw)
  605. {
  606. uint32_t eecd;
  607. DEBUGFUNC();
  608. eecd = E1000_READ_REG(hw, EECD);
  609. if (hw->eeprom.type == e1000_eeprom_spi) {
  610. eecd |= E1000_EECD_CS; /* Pull CS high */
  611. eecd &= ~E1000_EECD_SK; /* Lower SCK */
  612. E1000_WRITE_REG(hw, EECD, eecd);
  613. udelay(hw->eeprom.delay_usec);
  614. } else if (hw->eeprom.type == e1000_eeprom_microwire) {
  615. /* cleanup eeprom */
  616. /* CS on Microwire is active-high */
  617. eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  618. E1000_WRITE_REG(hw, EECD, eecd);
  619. /* Rising edge of clock */
  620. eecd |= E1000_EECD_SK;
  621. E1000_WRITE_REG(hw, EECD, eecd);
  622. E1000_WRITE_FLUSH(hw);
  623. udelay(hw->eeprom.delay_usec);
  624. /* Falling edge of clock */
  625. eecd &= ~E1000_EECD_SK;
  626. E1000_WRITE_REG(hw, EECD, eecd);
  627. E1000_WRITE_FLUSH(hw);
  628. udelay(hw->eeprom.delay_usec);
  629. }
  630. /* Stop requesting EEPROM access */
  631. if (hw->mac_type > e1000_82544) {
  632. eecd &= ~E1000_EECD_REQ;
  633. E1000_WRITE_REG(hw, EECD, eecd);
  634. }
  635. e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
  636. }
  637. /******************************************************************************
  638. * Reads a 16 bit word from the EEPROM.
  639. *
  640. * hw - Struct containing variables accessed by shared code
  641. *****************************************************************************/
  642. static int32_t
  643. e1000_spi_eeprom_ready(struct e1000_hw *hw)
  644. {
  645. uint16_t retry_count = 0;
  646. uint8_t spi_stat_reg;
  647. DEBUGFUNC();
  648. /* Read "Status Register" repeatedly until the LSB is cleared. The
  649. * EEPROM will signal that the command has been completed by clearing
  650. * bit 0 of the internal status register. If it's not cleared within
  651. * 5 milliseconds, then error out.
  652. */
  653. retry_count = 0;
  654. do {
  655. e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
  656. hw->eeprom.opcode_bits);
  657. spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
  658. if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
  659. break;
  660. udelay(5);
  661. retry_count += 5;
  662. e1000_standby_eeprom(hw);
  663. } while (retry_count < EEPROM_MAX_RETRY_SPI);
  664. /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
  665. * only 0-5mSec on 5V devices)
  666. */
  667. if (retry_count >= EEPROM_MAX_RETRY_SPI) {
  668. DEBUGOUT("SPI EEPROM Status error\n");
  669. return -E1000_ERR_EEPROM;
  670. }
  671. return E1000_SUCCESS;
  672. }
  673. /******************************************************************************
  674. * Reads a 16 bit word from the EEPROM.
  675. *
  676. * hw - Struct containing variables accessed by shared code
  677. * offset - offset of word in the EEPROM to read
  678. * data - word read from the EEPROM
  679. *****************************************************************************/
  680. static int32_t
  681. e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  682. uint16_t words, uint16_t *data)
  683. {
  684. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  685. uint32_t i = 0;
  686. DEBUGFUNC();
  687. /* If eeprom is not yet detected, do so now */
  688. if (eeprom->word_size == 0)
  689. e1000_init_eeprom_params(hw);
  690. /* A check for invalid values: offset too large, too many words,
  691. * and not enough words.
  692. */
  693. if ((offset >= eeprom->word_size) ||
  694. (words > eeprom->word_size - offset) ||
  695. (words == 0)) {
  696. DEBUGOUT("\"words\" parameter out of bounds."
  697. "Words = %d, size = %d\n", offset, eeprom->word_size);
  698. return -E1000_ERR_EEPROM;
  699. }
  700. /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
  701. * directly. In this case, we need to acquire the EEPROM so that
  702. * FW or other port software does not interrupt.
  703. */
  704. if (e1000_is_onboard_nvm_eeprom(hw) == true &&
  705. hw->eeprom.use_eerd == false) {
  706. /* Prepare the EEPROM for bit-bang reading */
  707. if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  708. return -E1000_ERR_EEPROM;
  709. }
  710. /* Eerd register EEPROM access requires no eeprom aquire/release */
  711. if (eeprom->use_eerd == true)
  712. return e1000_read_eeprom_eerd(hw, offset, words, data);
  713. /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
  714. * acquired the EEPROM at this point, so any returns should relase it */
  715. if (eeprom->type == e1000_eeprom_spi) {
  716. uint16_t word_in;
  717. uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
  718. if (e1000_spi_eeprom_ready(hw)) {
  719. e1000_release_eeprom(hw);
  720. return -E1000_ERR_EEPROM;
  721. }
  722. e1000_standby_eeprom(hw);
  723. /* Some SPI eeproms use the 8th address bit embedded in
  724. * the opcode */
  725. if ((eeprom->address_bits == 8) && (offset >= 128))
  726. read_opcode |= EEPROM_A8_OPCODE_SPI;
  727. /* Send the READ command (opcode + addr) */
  728. e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
  729. e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
  730. eeprom->address_bits);
  731. /* Read the data. The address of the eeprom internally
  732. * increments with each byte (spi) being read, saving on the
  733. * overhead of eeprom setup and tear-down. The address
  734. * counter will roll over if reading beyond the size of
  735. * the eeprom, thus allowing the entire memory to be read
  736. * starting from any offset. */
  737. for (i = 0; i < words; i++) {
  738. word_in = e1000_shift_in_ee_bits(hw, 16);
  739. data[i] = (word_in >> 8) | (word_in << 8);
  740. }
  741. } else if (eeprom->type == e1000_eeprom_microwire) {
  742. for (i = 0; i < words; i++) {
  743. /* Send the READ command (opcode + addr) */
  744. e1000_shift_out_ee_bits(hw,
  745. EEPROM_READ_OPCODE_MICROWIRE,
  746. eeprom->opcode_bits);
  747. e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
  748. eeprom->address_bits);
  749. /* Read the data. For microwire, each word requires
  750. * the overhead of eeprom setup and tear-down. */
  751. data[i] = e1000_shift_in_ee_bits(hw, 16);
  752. e1000_standby_eeprom(hw);
  753. }
  754. }
  755. /* End this read operation */
  756. e1000_release_eeprom(hw);
  757. return E1000_SUCCESS;
  758. }
  759. #ifndef CONFIG_DM_ETH
  760. /******************************************************************************
  761. * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
  762. * @hw: pointer to the HW structure
  763. * @offset: offset within the Shadow Ram to be written to
  764. * @words: number of words to write
  765. * @data: 16 bit word(s) to be written to the Shadow Ram
  766. *
  767. * Writes data to Shadow Ram at offset using EEWR register.
  768. *
  769. * If e1000_update_eeprom_checksum_i210 is not called after this function, the
  770. * Shadow Ram will most likely contain an invalid checksum.
  771. *****************************************************************************/
  772. static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
  773. uint16_t words, uint16_t *data)
  774. {
  775. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  776. uint32_t i, k, eewr = 0;
  777. uint32_t attempts = 100000;
  778. int32_t ret_val = 0;
  779. /* A check for invalid values: offset too large, too many words,
  780. * too many words for the offset, and not enough words.
  781. */
  782. if ((offset >= eeprom->word_size) ||
  783. (words > (eeprom->word_size - offset)) || (words == 0)) {
  784. DEBUGOUT("nvm parameter(s) out of bounds\n");
  785. ret_val = -E1000_ERR_EEPROM;
  786. goto out;
  787. }
  788. for (i = 0; i < words; i++) {
  789. eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
  790. | (data[i] << E1000_EEPROM_RW_REG_DATA) |
  791. E1000_EEPROM_RW_REG_START;
  792. E1000_WRITE_REG(hw, I210_EEWR, eewr);
  793. for (k = 0; k < attempts; k++) {
  794. if (E1000_EEPROM_RW_REG_DONE &
  795. E1000_READ_REG(hw, I210_EEWR)) {
  796. ret_val = 0;
  797. break;
  798. }
  799. udelay(5);
  800. }
  801. if (ret_val) {
  802. DEBUGOUT("Shadow RAM write EEWR timed out\n");
  803. break;
  804. }
  805. }
  806. out:
  807. return ret_val;
  808. }
  809. /******************************************************************************
  810. * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
  811. * @hw: pointer to the HW structure
  812. *
  813. *****************************************************************************/
  814. static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
  815. {
  816. int32_t ret_val = -E1000_ERR_EEPROM;
  817. uint32_t i, reg;
  818. for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
  819. reg = E1000_READ_REG(hw, EECD);
  820. if (reg & E1000_EECD_FLUDONE_I210) {
  821. ret_val = 0;
  822. break;
  823. }
  824. udelay(5);
  825. }
  826. return ret_val;
  827. }
  828. /******************************************************************************
  829. * e1000_update_flash_i210 - Commit EEPROM to the flash
  830. * @hw: pointer to the HW structure
  831. *
  832. *****************************************************************************/
  833. static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
  834. {
  835. int32_t ret_val = 0;
  836. uint32_t flup;
  837. ret_val = e1000_pool_flash_update_done_i210(hw);
  838. if (ret_val == -E1000_ERR_EEPROM) {
  839. DEBUGOUT("Flash update time out\n");
  840. goto out;
  841. }
  842. flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
  843. E1000_WRITE_REG(hw, EECD, flup);
  844. ret_val = e1000_pool_flash_update_done_i210(hw);
  845. if (ret_val)
  846. DEBUGOUT("Flash update time out\n");
  847. else
  848. DEBUGOUT("Flash update complete\n");
  849. out:
  850. return ret_val;
  851. }
  852. /******************************************************************************
  853. * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
  854. * @hw: pointer to the HW structure
  855. *
  856. * Updates the EEPROM checksum by reading/adding each word of the EEPROM
  857. * up to the checksum. Then calculates the EEPROM checksum and writes the
  858. * value to the EEPROM. Next commit EEPROM data onto the Flash.
  859. *****************************************************************************/
  860. static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
  861. {
  862. int32_t ret_val = 0;
  863. uint16_t checksum = 0;
  864. uint16_t i, nvm_data;
  865. /* Read the first word from the EEPROM. If this times out or fails, do
  866. * not continue or we could be in for a very long wait while every
  867. * EEPROM read fails
  868. */
  869. ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
  870. if (ret_val) {
  871. DEBUGOUT("EEPROM read failed\n");
  872. goto out;
  873. }
  874. if (!(e1000_get_hw_eeprom_semaphore(hw))) {
  875. /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
  876. * because we do not want to take the synchronization
  877. * semaphores twice here.
  878. */
  879. for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
  880. ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
  881. if (ret_val) {
  882. e1000_put_hw_eeprom_semaphore(hw);
  883. DEBUGOUT("EEPROM Read Error while updating checksum.\n");
  884. goto out;
  885. }
  886. checksum += nvm_data;
  887. }
  888. checksum = (uint16_t)EEPROM_SUM - checksum;
  889. ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
  890. &checksum);
  891. if (ret_val) {
  892. e1000_put_hw_eeprom_semaphore(hw);
  893. DEBUGOUT("EEPROM Write Error while updating checksum.\n");
  894. goto out;
  895. }
  896. e1000_put_hw_eeprom_semaphore(hw);
  897. ret_val = e1000_update_flash_i210(hw);
  898. } else {
  899. ret_val = -E1000_ERR_SWFW_SYNC;
  900. }
  901. out:
  902. return ret_val;
  903. }
  904. #endif
  905. /******************************************************************************
  906. * Verifies that the EEPROM has a valid checksum
  907. *
  908. * hw - Struct containing variables accessed by shared code
  909. *
  910. * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  911. * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  912. * valid.
  913. *****************************************************************************/
  914. static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
  915. {
  916. uint16_t i, checksum, checksum_reg, *buf;
  917. DEBUGFUNC();
  918. /* Allocate a temporary buffer */
  919. buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
  920. if (!buf) {
  921. E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
  922. return -E1000_ERR_EEPROM;
  923. }
  924. /* Read the EEPROM */
  925. if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
  926. E1000_ERR(hw, "Unable to read EEPROM!\n");
  927. return -E1000_ERR_EEPROM;
  928. }
  929. /* Compute the checksum */
  930. checksum = 0;
  931. for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
  932. checksum += buf[i];
  933. checksum = ((uint16_t)EEPROM_SUM) - checksum;
  934. checksum_reg = buf[i];
  935. /* Verify it! */
  936. if (checksum == checksum_reg)
  937. return 0;
  938. /* Hrm, verification failed, print an error */
  939. E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
  940. E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
  941. checksum_reg, checksum);
  942. return -E1000_ERR_EEPROM;
  943. }
  944. #endif /* CONFIG_E1000_NO_NVM */
  945. /*****************************************************************************
  946. * Set PHY to class A mode
  947. * Assumes the following operations will follow to enable the new class mode.
  948. * 1. Do a PHY soft reset
  949. * 2. Restart auto-negotiation or force link.
  950. *
  951. * hw - Struct containing variables accessed by shared code
  952. ****************************************************************************/
  953. static int32_t
  954. e1000_set_phy_mode(struct e1000_hw *hw)
  955. {
  956. #ifndef CONFIG_E1000_NO_NVM
  957. int32_t ret_val;
  958. uint16_t eeprom_data;
  959. DEBUGFUNC();
  960. if ((hw->mac_type == e1000_82545_rev_3) &&
  961. (hw->media_type == e1000_media_type_copper)) {
  962. ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
  963. 1, &eeprom_data);
  964. if (ret_val)
  965. return ret_val;
  966. if ((eeprom_data != EEPROM_RESERVED_WORD) &&
  967. (eeprom_data & EEPROM_PHY_CLASS_A)) {
  968. ret_val = e1000_write_phy_reg(hw,
  969. M88E1000_PHY_PAGE_SELECT, 0x000B);
  970. if (ret_val)
  971. return ret_val;
  972. ret_val = e1000_write_phy_reg(hw,
  973. M88E1000_PHY_GEN_CONTROL, 0x8104);
  974. if (ret_val)
  975. return ret_val;
  976. hw->phy_reset_disable = false;
  977. }
  978. }
  979. #endif
  980. return E1000_SUCCESS;
  981. }
  982. #ifndef CONFIG_E1000_NO_NVM
  983. /***************************************************************************
  984. *
  985. * Obtaining software semaphore bit (SMBI) before resetting PHY.
  986. *
  987. * hw: Struct containing variables accessed by shared code
  988. *
  989. * returns: - E1000_ERR_RESET if fail to obtain semaphore.
  990. * E1000_SUCCESS at any other case.
  991. *
  992. ***************************************************************************/
  993. static int32_t
  994. e1000_get_software_semaphore(struct e1000_hw *hw)
  995. {
  996. int32_t timeout = hw->eeprom.word_size + 1;
  997. uint32_t swsm;
  998. DEBUGFUNC();
  999. if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
  1000. return E1000_SUCCESS;
  1001. while (timeout) {
  1002. swsm = E1000_READ_REG(hw, SWSM);
  1003. /* If SMBI bit cleared, it is now set and we hold
  1004. * the semaphore */
  1005. if (!(swsm & E1000_SWSM_SMBI))
  1006. break;
  1007. mdelay(1);
  1008. timeout--;
  1009. }
  1010. if (!timeout) {
  1011. DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
  1012. return -E1000_ERR_RESET;
  1013. }
  1014. return E1000_SUCCESS;
  1015. }
  1016. #endif
  1017. /***************************************************************************
  1018. * This function clears HW semaphore bits.
  1019. *
  1020. * hw: Struct containing variables accessed by shared code
  1021. *
  1022. * returns: - None.
  1023. *
  1024. ***************************************************************************/
  1025. static void
  1026. e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
  1027. {
  1028. #ifndef CONFIG_E1000_NO_NVM
  1029. uint32_t swsm;
  1030. DEBUGFUNC();
  1031. if (!hw->eeprom_semaphore_present)
  1032. return;
  1033. swsm = E1000_READ_REG(hw, SWSM);
  1034. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1035. /* Release both semaphores. */
  1036. swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
  1037. } else
  1038. swsm &= ~(E1000_SWSM_SWESMBI);
  1039. E1000_WRITE_REG(hw, SWSM, swsm);
  1040. #endif
  1041. }
  1042. /***************************************************************************
  1043. *
  1044. * Using the combination of SMBI and SWESMBI semaphore bits when resetting
  1045. * adapter or Eeprom access.
  1046. *
  1047. * hw: Struct containing variables accessed by shared code
  1048. *
  1049. * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
  1050. * E1000_SUCCESS at any other case.
  1051. *
  1052. ***************************************************************************/
  1053. static int32_t
  1054. e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
  1055. {
  1056. #ifndef CONFIG_E1000_NO_NVM
  1057. int32_t timeout;
  1058. uint32_t swsm;
  1059. DEBUGFUNC();
  1060. if (!hw->eeprom_semaphore_present)
  1061. return E1000_SUCCESS;
  1062. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1063. /* Get the SW semaphore. */
  1064. if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
  1065. return -E1000_ERR_EEPROM;
  1066. }
  1067. /* Get the FW semaphore. */
  1068. timeout = hw->eeprom.word_size + 1;
  1069. while (timeout) {
  1070. swsm = E1000_READ_REG(hw, SWSM);
  1071. swsm |= E1000_SWSM_SWESMBI;
  1072. E1000_WRITE_REG(hw, SWSM, swsm);
  1073. /* if we managed to set the bit we got the semaphore. */
  1074. swsm = E1000_READ_REG(hw, SWSM);
  1075. if (swsm & E1000_SWSM_SWESMBI)
  1076. break;
  1077. udelay(50);
  1078. timeout--;
  1079. }
  1080. if (!timeout) {
  1081. /* Release semaphores */
  1082. e1000_put_hw_eeprom_semaphore(hw);
  1083. DEBUGOUT("Driver can't access the Eeprom - "
  1084. "SWESMBI bit is set.\n");
  1085. return -E1000_ERR_EEPROM;
  1086. }
  1087. #endif
  1088. return E1000_SUCCESS;
  1089. }
  1090. /* Take ownership of the PHY */
  1091. static int32_t
  1092. e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
  1093. {
  1094. uint32_t swfw_sync = 0;
  1095. uint32_t swmask = mask;
  1096. uint32_t fwmask = mask << 16;
  1097. int32_t timeout = 200;
  1098. DEBUGFUNC();
  1099. while (timeout) {
  1100. if (e1000_get_hw_eeprom_semaphore(hw))
  1101. return -E1000_ERR_SWFW_SYNC;
  1102. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1103. if (!(swfw_sync & (fwmask | swmask)))
  1104. break;
  1105. /* firmware currently using resource (fwmask) */
  1106. /* or other software thread currently using resource (swmask) */
  1107. e1000_put_hw_eeprom_semaphore(hw);
  1108. mdelay(5);
  1109. timeout--;
  1110. }
  1111. if (!timeout) {
  1112. DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
  1113. return -E1000_ERR_SWFW_SYNC;
  1114. }
  1115. swfw_sync |= swmask;
  1116. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1117. e1000_put_hw_eeprom_semaphore(hw);
  1118. return E1000_SUCCESS;
  1119. }
  1120. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
  1121. {
  1122. uint32_t swfw_sync = 0;
  1123. DEBUGFUNC();
  1124. while (e1000_get_hw_eeprom_semaphore(hw))
  1125. ; /* Empty */
  1126. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1127. swfw_sync &= ~mask;
  1128. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1129. e1000_put_hw_eeprom_semaphore(hw);
  1130. }
  1131. static bool e1000_is_second_port(struct e1000_hw *hw)
  1132. {
  1133. switch (hw->mac_type) {
  1134. case e1000_80003es2lan:
  1135. case e1000_82546:
  1136. case e1000_82571:
  1137. if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  1138. return true;
  1139. /* Fallthrough */
  1140. default:
  1141. return false;
  1142. }
  1143. }
  1144. #ifndef CONFIG_E1000_NO_NVM
  1145. /******************************************************************************
  1146. * Reads the adapter's MAC address from the EEPROM
  1147. *
  1148. * hw - Struct containing variables accessed by shared code
  1149. * enetaddr - buffering where the MAC address will be stored
  1150. *****************************************************************************/
  1151. static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
  1152. unsigned char enetaddr[6])
  1153. {
  1154. uint16_t offset;
  1155. uint16_t eeprom_data;
  1156. int i;
  1157. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1158. offset = i >> 1;
  1159. if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  1160. DEBUGOUT("EEPROM Read Error\n");
  1161. return -E1000_ERR_EEPROM;
  1162. }
  1163. enetaddr[i] = eeprom_data & 0xff;
  1164. enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
  1165. }
  1166. return 0;
  1167. }
  1168. /******************************************************************************
  1169. * Reads the adapter's MAC address from the RAL/RAH registers
  1170. *
  1171. * hw - Struct containing variables accessed by shared code
  1172. * enetaddr - buffering where the MAC address will be stored
  1173. *****************************************************************************/
  1174. static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
  1175. unsigned char enetaddr[6])
  1176. {
  1177. uint16_t offset, tmp;
  1178. uint32_t reg_data = 0;
  1179. int i;
  1180. if (hw->mac_type != e1000_igb)
  1181. return -E1000_ERR_MAC_TYPE;
  1182. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1183. offset = i >> 1;
  1184. if (offset == 0)
  1185. reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
  1186. else if (offset == 1)
  1187. reg_data >>= 16;
  1188. else if (offset == 2)
  1189. reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
  1190. tmp = reg_data & 0xffff;
  1191. enetaddr[i] = tmp & 0xff;
  1192. enetaddr[i + 1] = (tmp >> 8) & 0xff;
  1193. }
  1194. return 0;
  1195. }
  1196. /******************************************************************************
  1197. * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  1198. * second function of dual function devices
  1199. *
  1200. * hw - Struct containing variables accessed by shared code
  1201. * enetaddr - buffering where the MAC address will be stored
  1202. *****************************************************************************/
  1203. static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
  1204. {
  1205. int ret_val;
  1206. if (hw->mac_type == e1000_igb) {
  1207. /* i210 preloads MAC address into RAL/RAH registers */
  1208. ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
  1209. } else {
  1210. ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
  1211. }
  1212. if (ret_val)
  1213. return ret_val;
  1214. /* Invert the last bit if this is the second device */
  1215. if (e1000_is_second_port(hw))
  1216. enetaddr[5] ^= 1;
  1217. return 0;
  1218. }
  1219. #endif
  1220. /******************************************************************************
  1221. * Initializes receive address filters.
  1222. *
  1223. * hw - Struct containing variables accessed by shared code
  1224. *
  1225. * Places the MAC address in receive address register 0 and clears the rest
  1226. * of the receive addresss registers. Clears the multicast table. Assumes
  1227. * the receiver is in reset when the routine is called.
  1228. *****************************************************************************/
  1229. static void
  1230. e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
  1231. {
  1232. uint32_t i;
  1233. uint32_t addr_low;
  1234. uint32_t addr_high;
  1235. DEBUGFUNC();
  1236. /* Setup the receive address. */
  1237. DEBUGOUT("Programming MAC Address into RAR[0]\n");
  1238. addr_low = (enetaddr[0] |
  1239. (enetaddr[1] << 8) |
  1240. (enetaddr[2] << 16) | (enetaddr[3] << 24));
  1241. addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
  1242. E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
  1243. E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
  1244. /* Zero out the other 15 receive addresses. */
  1245. DEBUGOUT("Clearing RAR[1-15]\n");
  1246. for (i = 1; i < E1000_RAR_ENTRIES; i++) {
  1247. E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  1248. E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  1249. }
  1250. }
  1251. /******************************************************************************
  1252. * Clears the VLAN filer table
  1253. *
  1254. * hw - Struct containing variables accessed by shared code
  1255. *****************************************************************************/
  1256. static void
  1257. e1000_clear_vfta(struct e1000_hw *hw)
  1258. {
  1259. uint32_t offset;
  1260. for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
  1261. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
  1262. }
  1263. /******************************************************************************
  1264. * Set the mac type member in the hw struct.
  1265. *
  1266. * hw - Struct containing variables accessed by shared code
  1267. *****************************************************************************/
  1268. int32_t
  1269. e1000_set_mac_type(struct e1000_hw *hw)
  1270. {
  1271. DEBUGFUNC();
  1272. switch (hw->device_id) {
  1273. case E1000_DEV_ID_82542:
  1274. switch (hw->revision_id) {
  1275. case E1000_82542_2_0_REV_ID:
  1276. hw->mac_type = e1000_82542_rev2_0;
  1277. break;
  1278. case E1000_82542_2_1_REV_ID:
  1279. hw->mac_type = e1000_82542_rev2_1;
  1280. break;
  1281. default:
  1282. /* Invalid 82542 revision ID */
  1283. return -E1000_ERR_MAC_TYPE;
  1284. }
  1285. break;
  1286. case E1000_DEV_ID_82543GC_FIBER:
  1287. case E1000_DEV_ID_82543GC_COPPER:
  1288. hw->mac_type = e1000_82543;
  1289. break;
  1290. case E1000_DEV_ID_82544EI_COPPER:
  1291. case E1000_DEV_ID_82544EI_FIBER:
  1292. case E1000_DEV_ID_82544GC_COPPER:
  1293. case E1000_DEV_ID_82544GC_LOM:
  1294. hw->mac_type = e1000_82544;
  1295. break;
  1296. case E1000_DEV_ID_82540EM:
  1297. case E1000_DEV_ID_82540EM_LOM:
  1298. case E1000_DEV_ID_82540EP:
  1299. case E1000_DEV_ID_82540EP_LOM:
  1300. case E1000_DEV_ID_82540EP_LP:
  1301. hw->mac_type = e1000_82540;
  1302. break;
  1303. case E1000_DEV_ID_82545EM_COPPER:
  1304. case E1000_DEV_ID_82545EM_FIBER:
  1305. hw->mac_type = e1000_82545;
  1306. break;
  1307. case E1000_DEV_ID_82545GM_COPPER:
  1308. case E1000_DEV_ID_82545GM_FIBER:
  1309. case E1000_DEV_ID_82545GM_SERDES:
  1310. hw->mac_type = e1000_82545_rev_3;
  1311. break;
  1312. case E1000_DEV_ID_82546EB_COPPER:
  1313. case E1000_DEV_ID_82546EB_FIBER:
  1314. case E1000_DEV_ID_82546EB_QUAD_COPPER:
  1315. hw->mac_type = e1000_82546;
  1316. break;
  1317. case E1000_DEV_ID_82546GB_COPPER:
  1318. case E1000_DEV_ID_82546GB_FIBER:
  1319. case E1000_DEV_ID_82546GB_SERDES:
  1320. case E1000_DEV_ID_82546GB_PCIE:
  1321. case E1000_DEV_ID_82546GB_QUAD_COPPER:
  1322. case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
  1323. hw->mac_type = e1000_82546_rev_3;
  1324. break;
  1325. case E1000_DEV_ID_82541EI:
  1326. case E1000_DEV_ID_82541EI_MOBILE:
  1327. case E1000_DEV_ID_82541ER_LOM:
  1328. hw->mac_type = e1000_82541;
  1329. break;
  1330. case E1000_DEV_ID_82541ER:
  1331. case E1000_DEV_ID_82541GI:
  1332. case E1000_DEV_ID_82541GI_LF:
  1333. case E1000_DEV_ID_82541GI_MOBILE:
  1334. hw->mac_type = e1000_82541_rev_2;
  1335. break;
  1336. case E1000_DEV_ID_82547EI:
  1337. case E1000_DEV_ID_82547EI_MOBILE:
  1338. hw->mac_type = e1000_82547;
  1339. break;
  1340. case E1000_DEV_ID_82547GI:
  1341. hw->mac_type = e1000_82547_rev_2;
  1342. break;
  1343. case E1000_DEV_ID_82571EB_COPPER:
  1344. case E1000_DEV_ID_82571EB_FIBER:
  1345. case E1000_DEV_ID_82571EB_SERDES:
  1346. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  1347. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  1348. case E1000_DEV_ID_82571EB_QUAD_COPPER:
  1349. case E1000_DEV_ID_82571PT_QUAD_COPPER:
  1350. case E1000_DEV_ID_82571EB_QUAD_FIBER:
  1351. case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
  1352. hw->mac_type = e1000_82571;
  1353. break;
  1354. case E1000_DEV_ID_82572EI_COPPER:
  1355. case E1000_DEV_ID_82572EI_FIBER:
  1356. case E1000_DEV_ID_82572EI_SERDES:
  1357. case E1000_DEV_ID_82572EI:
  1358. hw->mac_type = e1000_82572;
  1359. break;
  1360. case E1000_DEV_ID_82573E:
  1361. case E1000_DEV_ID_82573E_IAMT:
  1362. case E1000_DEV_ID_82573L:
  1363. hw->mac_type = e1000_82573;
  1364. break;
  1365. case E1000_DEV_ID_82574L:
  1366. hw->mac_type = e1000_82574;
  1367. break;
  1368. case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
  1369. case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
  1370. case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
  1371. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  1372. hw->mac_type = e1000_80003es2lan;
  1373. break;
  1374. case E1000_DEV_ID_ICH8_IGP_M_AMT:
  1375. case E1000_DEV_ID_ICH8_IGP_AMT:
  1376. case E1000_DEV_ID_ICH8_IGP_C:
  1377. case E1000_DEV_ID_ICH8_IFE:
  1378. case E1000_DEV_ID_ICH8_IFE_GT:
  1379. case E1000_DEV_ID_ICH8_IFE_G:
  1380. case E1000_DEV_ID_ICH8_IGP_M:
  1381. hw->mac_type = e1000_ich8lan;
  1382. break;
  1383. case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
  1384. case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
  1385. case PCI_DEVICE_ID_INTEL_I210_COPPER:
  1386. case PCI_DEVICE_ID_INTEL_I211_COPPER:
  1387. case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
  1388. case PCI_DEVICE_ID_INTEL_I210_SERDES:
  1389. case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
  1390. case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
  1391. hw->mac_type = e1000_igb;
  1392. break;
  1393. default:
  1394. /* Should never have loaded on this device */
  1395. return -E1000_ERR_MAC_TYPE;
  1396. }
  1397. return E1000_SUCCESS;
  1398. }
  1399. /******************************************************************************
  1400. * Reset the transmit and receive units; mask and clear all interrupts.
  1401. *
  1402. * hw - Struct containing variables accessed by shared code
  1403. *****************************************************************************/
  1404. void
  1405. e1000_reset_hw(struct e1000_hw *hw)
  1406. {
  1407. uint32_t ctrl;
  1408. uint32_t ctrl_ext;
  1409. uint32_t manc;
  1410. uint32_t pba = 0;
  1411. uint32_t reg;
  1412. DEBUGFUNC();
  1413. /* get the correct pba value for both PCI and PCIe*/
  1414. if (hw->mac_type < e1000_82571)
  1415. pba = E1000_DEFAULT_PCI_PBA;
  1416. else
  1417. pba = E1000_DEFAULT_PCIE_PBA;
  1418. /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  1419. if (hw->mac_type == e1000_82542_rev2_0) {
  1420. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1421. #ifdef CONFIG_DM_ETH
  1422. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1423. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1424. #else
  1425. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1426. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1427. #endif
  1428. }
  1429. /* Clear interrupt mask to stop board from generating interrupts */
  1430. DEBUGOUT("Masking off all interrupts\n");
  1431. if (hw->mac_type == e1000_igb)
  1432. E1000_WRITE_REG(hw, I210_IAM, 0);
  1433. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1434. /* Disable the Transmit and Receive units. Then delay to allow
  1435. * any pending transactions to complete before we hit the MAC with
  1436. * the global reset.
  1437. */
  1438. E1000_WRITE_REG(hw, RCTL, 0);
  1439. E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
  1440. E1000_WRITE_FLUSH(hw);
  1441. if (hw->mac_type == e1000_igb) {
  1442. E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT);
  1443. E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT);
  1444. }
  1445. /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
  1446. hw->tbi_compatibility_on = false;
  1447. /* Delay to allow any outstanding PCI transactions to complete before
  1448. * resetting the device
  1449. */
  1450. mdelay(10);
  1451. /* Issue a global reset to the MAC. This will reset the chip's
  1452. * transmit, receive, DMA, and link units. It will not effect
  1453. * the current PCI configuration. The global reset bit is self-
  1454. * clearing, and should clear within a microsecond.
  1455. */
  1456. DEBUGOUT("Issuing a global reset to MAC\n");
  1457. ctrl = E1000_READ_REG(hw, CTRL);
  1458. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  1459. /* Force a reload from the EEPROM if necessary */
  1460. if (hw->mac_type == e1000_igb) {
  1461. mdelay(20);
  1462. reg = E1000_READ_REG(hw, STATUS);
  1463. if (reg & E1000_STATUS_PF_RST_DONE)
  1464. DEBUGOUT("PF OK\n");
  1465. reg = E1000_READ_REG(hw, I210_EECD);
  1466. if (reg & E1000_EECD_AUTO_RD)
  1467. DEBUGOUT("EEC OK\n");
  1468. } else if (hw->mac_type < e1000_82540) {
  1469. /* Wait for reset to complete */
  1470. udelay(10);
  1471. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1472. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  1473. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1474. E1000_WRITE_FLUSH(hw);
  1475. /* Wait for EEPROM reload */
  1476. mdelay(2);
  1477. } else {
  1478. /* Wait for EEPROM reload (it happens automatically) */
  1479. mdelay(4);
  1480. /* Dissable HW ARPs on ASF enabled adapters */
  1481. manc = E1000_READ_REG(hw, MANC);
  1482. manc &= ~(E1000_MANC_ARP_EN);
  1483. E1000_WRITE_REG(hw, MANC, manc);
  1484. }
  1485. /* Clear interrupt mask to stop board from generating interrupts */
  1486. DEBUGOUT("Masking off all interrupts\n");
  1487. if (hw->mac_type == e1000_igb)
  1488. E1000_WRITE_REG(hw, I210_IAM, 0);
  1489. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1490. /* Clear any pending interrupt events. */
  1491. E1000_READ_REG(hw, ICR);
  1492. /* If MWI was previously enabled, reenable it. */
  1493. if (hw->mac_type == e1000_82542_rev2_0) {
  1494. #ifdef CONFIG_DM_ETH
  1495. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1496. #else
  1497. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1498. #endif
  1499. }
  1500. if (hw->mac_type != e1000_igb)
  1501. E1000_WRITE_REG(hw, PBA, pba);
  1502. }
  1503. /******************************************************************************
  1504. *
  1505. * Initialize a number of hardware-dependent bits
  1506. *
  1507. * hw: Struct containing variables accessed by shared code
  1508. *
  1509. * This function contains hardware limitation workarounds for PCI-E adapters
  1510. *
  1511. *****************************************************************************/
  1512. static void
  1513. e1000_initialize_hardware_bits(struct e1000_hw *hw)
  1514. {
  1515. if ((hw->mac_type >= e1000_82571) &&
  1516. (!hw->initialize_hw_bits_disable)) {
  1517. /* Settings common to all PCI-express silicon */
  1518. uint32_t reg_ctrl, reg_ctrl_ext;
  1519. uint32_t reg_tarc0, reg_tarc1;
  1520. uint32_t reg_tctl;
  1521. uint32_t reg_txdctl, reg_txdctl1;
  1522. /* link autonegotiation/sync workarounds */
  1523. reg_tarc0 = E1000_READ_REG(hw, TARC0);
  1524. reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  1525. /* Enable not-done TX descriptor counting */
  1526. reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  1527. reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
  1528. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  1529. reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
  1530. reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
  1531. E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
  1532. switch (hw->mac_type) {
  1533. case e1000_igb: /* IGB is cool */
  1534. return;
  1535. case e1000_82571:
  1536. case e1000_82572:
  1537. /* Clear PHY TX compatible mode bits */
  1538. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1539. reg_tarc1 &= ~((1 << 30)|(1 << 29));
  1540. /* link autonegotiation/sync workarounds */
  1541. reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
  1542. /* TX ring control fixes */
  1543. reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
  1544. /* Multiple read bit is reversed polarity */
  1545. reg_tctl = E1000_READ_REG(hw, TCTL);
  1546. if (reg_tctl & E1000_TCTL_MULR)
  1547. reg_tarc1 &= ~(1 << 28);
  1548. else
  1549. reg_tarc1 |= (1 << 28);
  1550. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1551. break;
  1552. case e1000_82573:
  1553. case e1000_82574:
  1554. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1555. reg_ctrl_ext &= ~(1 << 23);
  1556. reg_ctrl_ext |= (1 << 22);
  1557. /* TX byte count fix */
  1558. reg_ctrl = E1000_READ_REG(hw, CTRL);
  1559. reg_ctrl &= ~(1 << 29);
  1560. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1561. E1000_WRITE_REG(hw, CTRL, reg_ctrl);
  1562. break;
  1563. case e1000_80003es2lan:
  1564. /* improve small packet performace for fiber/serdes */
  1565. if ((hw->media_type == e1000_media_type_fiber)
  1566. || (hw->media_type ==
  1567. e1000_media_type_internal_serdes)) {
  1568. reg_tarc0 &= ~(1 << 20);
  1569. }
  1570. /* Multiple read bit is reversed polarity */
  1571. reg_tctl = E1000_READ_REG(hw, TCTL);
  1572. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1573. if (reg_tctl & E1000_TCTL_MULR)
  1574. reg_tarc1 &= ~(1 << 28);
  1575. else
  1576. reg_tarc1 |= (1 << 28);
  1577. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1578. break;
  1579. case e1000_ich8lan:
  1580. /* Reduce concurrent DMA requests to 3 from 4 */
  1581. if ((hw->revision_id < 3) ||
  1582. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1583. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
  1584. reg_tarc0 |= ((1 << 29)|(1 << 28));
  1585. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1586. reg_ctrl_ext |= (1 << 22);
  1587. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1588. /* workaround TX hang with TSO=on */
  1589. reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
  1590. /* Multiple read bit is reversed polarity */
  1591. reg_tctl = E1000_READ_REG(hw, TCTL);
  1592. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1593. if (reg_tctl & E1000_TCTL_MULR)
  1594. reg_tarc1 &= ~(1 << 28);
  1595. else
  1596. reg_tarc1 |= (1 << 28);
  1597. /* workaround TX hang with TSO=on */
  1598. reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
  1599. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1600. break;
  1601. default:
  1602. break;
  1603. }
  1604. E1000_WRITE_REG(hw, TARC0, reg_tarc0);
  1605. }
  1606. }
  1607. /******************************************************************************
  1608. * Performs basic configuration of the adapter.
  1609. *
  1610. * hw - Struct containing variables accessed by shared code
  1611. *
  1612. * Assumes that the controller has previously been reset and is in a
  1613. * post-reset uninitialized state. Initializes the receive address registers,
  1614. * multicast table, and VLAN filter table. Calls routines to setup link
  1615. * configuration and flow control settings. Clears all on-chip counters. Leaves
  1616. * the transmit and receive units disabled and uninitialized.
  1617. *****************************************************************************/
  1618. static int
  1619. e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
  1620. {
  1621. uint32_t ctrl;
  1622. uint32_t i;
  1623. int32_t ret_val;
  1624. uint16_t pcix_cmd_word;
  1625. uint16_t pcix_stat_hi_word;
  1626. uint16_t cmd_mmrbc;
  1627. uint16_t stat_mmrbc;
  1628. uint32_t mta_size;
  1629. uint32_t reg_data;
  1630. uint32_t ctrl_ext;
  1631. DEBUGFUNC();
  1632. /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
  1633. if ((hw->mac_type == e1000_ich8lan) &&
  1634. ((hw->revision_id < 3) ||
  1635. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1636. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
  1637. reg_data = E1000_READ_REG(hw, STATUS);
  1638. reg_data &= ~0x80000000;
  1639. E1000_WRITE_REG(hw, STATUS, reg_data);
  1640. }
  1641. /* Do not need initialize Identification LED */
  1642. /* Set the media type and TBI compatibility */
  1643. e1000_set_media_type(hw);
  1644. /* Must be called after e1000_set_media_type
  1645. * because media_type is used */
  1646. e1000_initialize_hardware_bits(hw);
  1647. /* Disabling VLAN filtering. */
  1648. DEBUGOUT("Initializing the IEEE VLAN\n");
  1649. /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
  1650. if (hw->mac_type != e1000_ich8lan) {
  1651. if (hw->mac_type < e1000_82545_rev_3)
  1652. E1000_WRITE_REG(hw, VET, 0);
  1653. e1000_clear_vfta(hw);
  1654. }
  1655. /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  1656. if (hw->mac_type == e1000_82542_rev2_0) {
  1657. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1658. #ifdef CONFIG_DM_ETH
  1659. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1660. hw->
  1661. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1662. #else
  1663. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1664. hw->
  1665. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1666. #endif
  1667. E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
  1668. E1000_WRITE_FLUSH(hw);
  1669. mdelay(5);
  1670. }
  1671. /* Setup the receive address. This involves initializing all of the Receive
  1672. * Address Registers (RARs 0 - 15).
  1673. */
  1674. e1000_init_rx_addrs(hw, enetaddr);
  1675. /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  1676. if (hw->mac_type == e1000_82542_rev2_0) {
  1677. E1000_WRITE_REG(hw, RCTL, 0);
  1678. E1000_WRITE_FLUSH(hw);
  1679. mdelay(1);
  1680. #ifdef CONFIG_DM_ETH
  1681. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1682. #else
  1683. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1684. #endif
  1685. }
  1686. /* Zero out the Multicast HASH table */
  1687. DEBUGOUT("Zeroing the MTA\n");
  1688. mta_size = E1000_MC_TBL_SIZE;
  1689. if (hw->mac_type == e1000_ich8lan)
  1690. mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
  1691. for (i = 0; i < mta_size; i++) {
  1692. E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  1693. /* use write flush to prevent Memory Write Block (MWB) from
  1694. * occuring when accessing our register space */
  1695. E1000_WRITE_FLUSH(hw);
  1696. }
  1697. switch (hw->mac_type) {
  1698. case e1000_82545_rev_3:
  1699. case e1000_82546_rev_3:
  1700. case e1000_igb:
  1701. break;
  1702. default:
  1703. /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  1704. if (hw->bus_type == e1000_bus_type_pcix) {
  1705. #ifdef CONFIG_DM_ETH
  1706. dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1707. &pcix_cmd_word);
  1708. dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1709. &pcix_stat_hi_word);
  1710. #else
  1711. pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1712. &pcix_cmd_word);
  1713. pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1714. &pcix_stat_hi_word);
  1715. #endif
  1716. cmd_mmrbc =
  1717. (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
  1718. PCIX_COMMAND_MMRBC_SHIFT;
  1719. stat_mmrbc =
  1720. (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
  1721. PCIX_STATUS_HI_MMRBC_SHIFT;
  1722. if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
  1723. stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  1724. if (cmd_mmrbc > stat_mmrbc) {
  1725. pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
  1726. pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
  1727. #ifdef CONFIG_DM_ETH
  1728. dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1729. pcix_cmd_word);
  1730. #else
  1731. pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1732. pcix_cmd_word);
  1733. #endif
  1734. }
  1735. }
  1736. break;
  1737. }
  1738. /* More time needed for PHY to initialize */
  1739. if (hw->mac_type == e1000_ich8lan)
  1740. mdelay(15);
  1741. if (hw->mac_type == e1000_igb)
  1742. mdelay(15);
  1743. /* Call a subroutine to configure the link and setup flow control. */
  1744. ret_val = e1000_setup_link(hw);
  1745. /* Set the transmit descriptor write-back policy */
  1746. if (hw->mac_type > e1000_82544) {
  1747. ctrl = E1000_READ_REG(hw, TXDCTL);
  1748. ctrl =
  1749. (ctrl & ~E1000_TXDCTL_WTHRESH) |
  1750. E1000_TXDCTL_FULL_TX_DESC_WB;
  1751. E1000_WRITE_REG(hw, TXDCTL, ctrl);
  1752. }
  1753. /* Set the receive descriptor write back policy */
  1754. if (hw->mac_type >= e1000_82571) {
  1755. ctrl = E1000_READ_REG(hw, RXDCTL);
  1756. ctrl =
  1757. (ctrl & ~E1000_RXDCTL_WTHRESH) |
  1758. E1000_RXDCTL_FULL_RX_DESC_WB;
  1759. E1000_WRITE_REG(hw, RXDCTL, ctrl);
  1760. }
  1761. switch (hw->mac_type) {
  1762. default:
  1763. break;
  1764. case e1000_80003es2lan:
  1765. /* Enable retransmit on late collisions */
  1766. reg_data = E1000_READ_REG(hw, TCTL);
  1767. reg_data |= E1000_TCTL_RTLC;
  1768. E1000_WRITE_REG(hw, TCTL, reg_data);
  1769. /* Configure Gigabit Carry Extend Padding */
  1770. reg_data = E1000_READ_REG(hw, TCTL_EXT);
  1771. reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  1772. reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
  1773. E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
  1774. /* Configure Transmit Inter-Packet Gap */
  1775. reg_data = E1000_READ_REG(hw, TIPG);
  1776. reg_data &= ~E1000_TIPG_IPGT_MASK;
  1777. reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  1778. E1000_WRITE_REG(hw, TIPG, reg_data);
  1779. reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
  1780. reg_data &= ~0x00100000;
  1781. E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
  1782. /* Fall through */
  1783. case e1000_82571:
  1784. case e1000_82572:
  1785. case e1000_ich8lan:
  1786. ctrl = E1000_READ_REG(hw, TXDCTL1);
  1787. ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
  1788. | E1000_TXDCTL_FULL_TX_DESC_WB;
  1789. E1000_WRITE_REG(hw, TXDCTL1, ctrl);
  1790. break;
  1791. case e1000_82573:
  1792. case e1000_82574:
  1793. reg_data = E1000_READ_REG(hw, GCR);
  1794. reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
  1795. E1000_WRITE_REG(hw, GCR, reg_data);
  1796. case e1000_igb:
  1797. break;
  1798. }
  1799. if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
  1800. hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
  1801. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1802. /* Relaxed ordering must be disabled to avoid a parity
  1803. * error crash in a PCI slot. */
  1804. ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  1805. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1806. }
  1807. return ret_val;
  1808. }
  1809. /******************************************************************************
  1810. * Configures flow control and link settings.
  1811. *
  1812. * hw - Struct containing variables accessed by shared code
  1813. *
  1814. * Determines which flow control settings to use. Calls the apropriate media-
  1815. * specific link configuration function. Configures the flow control settings.
  1816. * Assuming the adapter has a valid link partner, a valid link should be
  1817. * established. Assumes the hardware has previously been reset and the
  1818. * transmitter and receiver are not enabled.
  1819. *****************************************************************************/
  1820. static int
  1821. e1000_setup_link(struct e1000_hw *hw)
  1822. {
  1823. int32_t ret_val;
  1824. #ifndef CONFIG_E1000_NO_NVM
  1825. uint32_t ctrl_ext;
  1826. uint16_t eeprom_data;
  1827. #endif
  1828. DEBUGFUNC();
  1829. /* In the case of the phy reset being blocked, we already have a link.
  1830. * We do not have to set it up again. */
  1831. if (e1000_check_phy_reset_block(hw))
  1832. return E1000_SUCCESS;
  1833. #ifndef CONFIG_E1000_NO_NVM
  1834. /* Read and store word 0x0F of the EEPROM. This word contains bits
  1835. * that determine the hardware's default PAUSE (flow control) mode,
  1836. * a bit that determines whether the HW defaults to enabling or
  1837. * disabling auto-negotiation, and the direction of the
  1838. * SW defined pins. If there is no SW over-ride of the flow
  1839. * control setting, then the variable hw->fc will
  1840. * be initialized based on a value in the EEPROM.
  1841. */
  1842. if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
  1843. &eeprom_data) < 0) {
  1844. DEBUGOUT("EEPROM Read Error\n");
  1845. return -E1000_ERR_EEPROM;
  1846. }
  1847. #endif
  1848. if (hw->fc == e1000_fc_default) {
  1849. switch (hw->mac_type) {
  1850. case e1000_ich8lan:
  1851. case e1000_82573:
  1852. case e1000_82574:
  1853. case e1000_igb:
  1854. hw->fc = e1000_fc_full;
  1855. break;
  1856. default:
  1857. #ifndef CONFIG_E1000_NO_NVM
  1858. ret_val = e1000_read_eeprom(hw,
  1859. EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
  1860. if (ret_val) {
  1861. DEBUGOUT("EEPROM Read Error\n");
  1862. return -E1000_ERR_EEPROM;
  1863. }
  1864. if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
  1865. hw->fc = e1000_fc_none;
  1866. else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
  1867. EEPROM_WORD0F_ASM_DIR)
  1868. hw->fc = e1000_fc_tx_pause;
  1869. else
  1870. #endif
  1871. hw->fc = e1000_fc_full;
  1872. break;
  1873. }
  1874. }
  1875. /* We want to save off the original Flow Control configuration just
  1876. * in case we get disconnected and then reconnected into a different
  1877. * hub or switch with different Flow Control capabilities.
  1878. */
  1879. if (hw->mac_type == e1000_82542_rev2_0)
  1880. hw->fc &= (~e1000_fc_tx_pause);
  1881. if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
  1882. hw->fc &= (~e1000_fc_rx_pause);
  1883. hw->original_fc = hw->fc;
  1884. DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
  1885. #ifndef CONFIG_E1000_NO_NVM
  1886. /* Take the 4 bits from EEPROM word 0x0F that determine the initial
  1887. * polarity value for the SW controlled pins, and setup the
  1888. * Extended Device Control reg with that info.
  1889. * This is needed because one of the SW controlled pins is used for
  1890. * signal detection. So this should be done before e1000_setup_pcs_link()
  1891. * or e1000_phy_setup() is called.
  1892. */
  1893. if (hw->mac_type == e1000_82543) {
  1894. ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
  1895. SWDPIO__EXT_SHIFT);
  1896. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1897. }
  1898. #endif
  1899. /* Call the necessary subroutine to configure the link. */
  1900. ret_val = (hw->media_type == e1000_media_type_fiber) ?
  1901. e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
  1902. if (ret_val < 0) {
  1903. return ret_val;
  1904. }
  1905. /* Initialize the flow control address, type, and PAUSE timer
  1906. * registers to their default values. This is done even if flow
  1907. * control is disabled, because it does not hurt anything to
  1908. * initialize these registers.
  1909. */
  1910. DEBUGOUT("Initializing the Flow Control address, type"
  1911. "and timer regs\n");
  1912. /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
  1913. if (hw->mac_type != e1000_ich8lan) {
  1914. E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
  1915. E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  1916. E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
  1917. }
  1918. E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
  1919. /* Set the flow control receive threshold registers. Normally,
  1920. * these registers will be set to a default threshold that may be
  1921. * adjusted later by the driver's runtime code. However, if the
  1922. * ability to transmit pause frames in not enabled, then these
  1923. * registers will be set to 0.
  1924. */
  1925. if (!(hw->fc & e1000_fc_tx_pause)) {
  1926. E1000_WRITE_REG(hw, FCRTL, 0);
  1927. E1000_WRITE_REG(hw, FCRTH, 0);
  1928. } else {
  1929. /* We need to set up the Receive Threshold high and low water marks
  1930. * as well as (optionally) enabling the transmission of XON frames.
  1931. */
  1932. if (hw->fc_send_xon) {
  1933. E1000_WRITE_REG(hw, FCRTL,
  1934. (hw->fc_low_water | E1000_FCRTL_XONE));
  1935. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1936. } else {
  1937. E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
  1938. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1939. }
  1940. }
  1941. return ret_val;
  1942. }
  1943. /******************************************************************************
  1944. * Sets up link for a fiber based adapter
  1945. *
  1946. * hw - Struct containing variables accessed by shared code
  1947. *
  1948. * Manipulates Physical Coding Sublayer functions in order to configure
  1949. * link. Assumes the hardware has been previously reset and the transmitter
  1950. * and receiver are not enabled.
  1951. *****************************************************************************/
  1952. static int
  1953. e1000_setup_fiber_link(struct e1000_hw *hw)
  1954. {
  1955. uint32_t ctrl;
  1956. uint32_t status;
  1957. uint32_t txcw = 0;
  1958. uint32_t i;
  1959. uint32_t signal;
  1960. int32_t ret_val;
  1961. DEBUGFUNC();
  1962. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  1963. * set when the optics detect a signal. On older adapters, it will be
  1964. * cleared when there is a signal
  1965. */
  1966. ctrl = E1000_READ_REG(hw, CTRL);
  1967. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  1968. signal = E1000_CTRL_SWDPIN1;
  1969. else
  1970. signal = 0;
  1971. printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
  1972. ctrl);
  1973. /* Take the link out of reset */
  1974. ctrl &= ~(E1000_CTRL_LRST);
  1975. e1000_config_collision_dist(hw);
  1976. /* Check for a software override of the flow control settings, and setup
  1977. * the device accordingly. If auto-negotiation is enabled, then software
  1978. * will have to set the "PAUSE" bits to the correct value in the Tranmsit
  1979. * Config Word Register (TXCW) and re-start auto-negotiation. However, if
  1980. * auto-negotiation is disabled, then software will have to manually
  1981. * configure the two flow control enable bits in the CTRL register.
  1982. *
  1983. * The possible values of the "fc" parameter are:
  1984. * 0: Flow control is completely disabled
  1985. * 1: Rx flow control is enabled (we can receive pause frames, but
  1986. * not send pause frames).
  1987. * 2: Tx flow control is enabled (we can send pause frames but we do
  1988. * not support receiving pause frames).
  1989. * 3: Both Rx and TX flow control (symmetric) are enabled.
  1990. */
  1991. switch (hw->fc) {
  1992. case e1000_fc_none:
  1993. /* Flow control is completely disabled by a software over-ride. */
  1994. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
  1995. break;
  1996. case e1000_fc_rx_pause:
  1997. /* RX Flow control is enabled and TX Flow control is disabled by a
  1998. * software over-ride. Since there really isn't a way to advertise
  1999. * that we are capable of RX Pause ONLY, we will advertise that we
  2000. * support both symmetric and asymmetric RX PAUSE. Later, we will
  2001. * disable the adapter's ability to send PAUSE frames.
  2002. */
  2003. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  2004. break;
  2005. case e1000_fc_tx_pause:
  2006. /* TX Flow control is enabled, and RX Flow control is disabled, by a
  2007. * software over-ride.
  2008. */
  2009. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
  2010. break;
  2011. case e1000_fc_full:
  2012. /* Flow control (both RX and TX) is enabled by a software over-ride. */
  2013. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  2014. break;
  2015. default:
  2016. DEBUGOUT("Flow control param set incorrectly\n");
  2017. return -E1000_ERR_CONFIG;
  2018. break;
  2019. }
  2020. /* Since auto-negotiation is enabled, take the link out of reset (the link
  2021. * will be in reset, because we previously reset the chip). This will
  2022. * restart auto-negotiation. If auto-neogtiation is successful then the
  2023. * link-up status bit will be set and the flow control enable bits (RFCE
  2024. * and TFCE) will be set according to their negotiated value.
  2025. */
  2026. DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
  2027. E1000_WRITE_REG(hw, TXCW, txcw);
  2028. E1000_WRITE_REG(hw, CTRL, ctrl);
  2029. E1000_WRITE_FLUSH(hw);
  2030. hw->txcw = txcw;
  2031. mdelay(1);
  2032. /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
  2033. * indication in the Device Status Register. Time-out if a link isn't
  2034. * seen in 500 milliseconds seconds (Auto-negotiation should complete in
  2035. * less than 500 milliseconds even if the other end is doing it in SW).
  2036. */
  2037. if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
  2038. DEBUGOUT("Looking for Link\n");
  2039. for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
  2040. mdelay(10);
  2041. status = E1000_READ_REG(hw, STATUS);
  2042. if (status & E1000_STATUS_LU)
  2043. break;
  2044. }
  2045. if (i == (LINK_UP_TIMEOUT / 10)) {
  2046. /* AutoNeg failed to achieve a link, so we'll call
  2047. * e1000_check_for_link. This routine will force the link up if we
  2048. * detect a signal. This will allow us to communicate with
  2049. * non-autonegotiating link partners.
  2050. */
  2051. DEBUGOUT("Never got a valid link from auto-neg!!!\n");
  2052. hw->autoneg_failed = 1;
  2053. ret_val = e1000_check_for_link(hw);
  2054. if (ret_val < 0) {
  2055. DEBUGOUT("Error while checking for link\n");
  2056. return ret_val;
  2057. }
  2058. hw->autoneg_failed = 0;
  2059. } else {
  2060. hw->autoneg_failed = 0;
  2061. DEBUGOUT("Valid Link Found\n");
  2062. }
  2063. } else {
  2064. DEBUGOUT("No Signal Detected\n");
  2065. return -E1000_ERR_NOLINK;
  2066. }
  2067. return 0;
  2068. }
  2069. /******************************************************************************
  2070. * Make sure we have a valid PHY and change PHY mode before link setup.
  2071. *
  2072. * hw - Struct containing variables accessed by shared code
  2073. ******************************************************************************/
  2074. static int32_t
  2075. e1000_copper_link_preconfig(struct e1000_hw *hw)
  2076. {
  2077. uint32_t ctrl;
  2078. int32_t ret_val;
  2079. uint16_t phy_data;
  2080. DEBUGFUNC();
  2081. ctrl = E1000_READ_REG(hw, CTRL);
  2082. /* With 82543, we need to force speed and duplex on the MAC equal to what
  2083. * the PHY speed and duplex configuration is. In addition, we need to
  2084. * perform a hardware reset on the PHY to take it out of reset.
  2085. */
  2086. if (hw->mac_type > e1000_82543) {
  2087. ctrl |= E1000_CTRL_SLU;
  2088. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  2089. E1000_WRITE_REG(hw, CTRL, ctrl);
  2090. } else {
  2091. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
  2092. | E1000_CTRL_SLU);
  2093. E1000_WRITE_REG(hw, CTRL, ctrl);
  2094. ret_val = e1000_phy_hw_reset(hw);
  2095. if (ret_val)
  2096. return ret_val;
  2097. }
  2098. /* Make sure we have a valid PHY */
  2099. ret_val = e1000_detect_gig_phy(hw);
  2100. if (ret_val) {
  2101. DEBUGOUT("Error, did not detect valid phy.\n");
  2102. return ret_val;
  2103. }
  2104. DEBUGOUT("Phy ID = %x\n", hw->phy_id);
  2105. /* Set PHY to class A mode (if necessary) */
  2106. ret_val = e1000_set_phy_mode(hw);
  2107. if (ret_val)
  2108. return ret_val;
  2109. if ((hw->mac_type == e1000_82545_rev_3) ||
  2110. (hw->mac_type == e1000_82546_rev_3)) {
  2111. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2112. &phy_data);
  2113. phy_data |= 0x00000008;
  2114. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2115. phy_data);
  2116. }
  2117. if (hw->mac_type <= e1000_82543 ||
  2118. hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
  2119. hw->mac_type == e1000_82541_rev_2
  2120. || hw->mac_type == e1000_82547_rev_2)
  2121. hw->phy_reset_disable = false;
  2122. return E1000_SUCCESS;
  2123. }
  2124. /*****************************************************************************
  2125. *
  2126. * This function sets the lplu state according to the active flag. When
  2127. * activating lplu this function also disables smart speed and vise versa.
  2128. * lplu will not be activated unless the device autonegotiation advertisment
  2129. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2130. * hw: Struct containing variables accessed by shared code
  2131. * active - true to enable lplu false to disable lplu.
  2132. *
  2133. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2134. * E1000_SUCCESS at any other case.
  2135. *
  2136. ****************************************************************************/
  2137. static int32_t
  2138. e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
  2139. {
  2140. uint32_t phy_ctrl = 0;
  2141. int32_t ret_val;
  2142. uint16_t phy_data;
  2143. DEBUGFUNC();
  2144. if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
  2145. && hw->phy_type != e1000_phy_igp_3)
  2146. return E1000_SUCCESS;
  2147. /* During driver activity LPLU should not be used or it will attain link
  2148. * from the lowest speeds starting from 10Mbps. The capability is used
  2149. * for Dx transitions and states */
  2150. if (hw->mac_type == e1000_82541_rev_2
  2151. || hw->mac_type == e1000_82547_rev_2) {
  2152. ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2153. &phy_data);
  2154. if (ret_val)
  2155. return ret_val;
  2156. } else if (hw->mac_type == e1000_ich8lan) {
  2157. /* MAC writes into PHY register based on the state transition
  2158. * and start auto-negotiation. SW driver can overwrite the
  2159. * settings in CSR PHY power control E1000_PHY_CTRL register. */
  2160. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2161. } else {
  2162. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2163. &phy_data);
  2164. if (ret_val)
  2165. return ret_val;
  2166. }
  2167. if (!active) {
  2168. if (hw->mac_type == e1000_82541_rev_2 ||
  2169. hw->mac_type == e1000_82547_rev_2) {
  2170. phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
  2171. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2172. phy_data);
  2173. if (ret_val)
  2174. return ret_val;
  2175. } else {
  2176. if (hw->mac_type == e1000_ich8lan) {
  2177. phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
  2178. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2179. } else {
  2180. phy_data &= ~IGP02E1000_PM_D3_LPLU;
  2181. ret_val = e1000_write_phy_reg(hw,
  2182. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2183. if (ret_val)
  2184. return ret_val;
  2185. }
  2186. }
  2187. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2188. * Dx states where the power conservation is most important. During
  2189. * driver activity we should enable SmartSpeed, so performance is
  2190. * maintained. */
  2191. if (hw->smart_speed == e1000_smart_speed_on) {
  2192. ret_val = e1000_read_phy_reg(hw,
  2193. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2194. if (ret_val)
  2195. return ret_val;
  2196. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2197. ret_val = e1000_write_phy_reg(hw,
  2198. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2199. if (ret_val)
  2200. return ret_val;
  2201. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2202. ret_val = e1000_read_phy_reg(hw,
  2203. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2204. if (ret_val)
  2205. return ret_val;
  2206. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2207. ret_val = e1000_write_phy_reg(hw,
  2208. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2209. if (ret_val)
  2210. return ret_val;
  2211. }
  2212. } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
  2213. || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
  2214. (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
  2215. if (hw->mac_type == e1000_82541_rev_2 ||
  2216. hw->mac_type == e1000_82547_rev_2) {
  2217. phy_data |= IGP01E1000_GMII_FLEX_SPD;
  2218. ret_val = e1000_write_phy_reg(hw,
  2219. IGP01E1000_GMII_FIFO, phy_data);
  2220. if (ret_val)
  2221. return ret_val;
  2222. } else {
  2223. if (hw->mac_type == e1000_ich8lan) {
  2224. phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
  2225. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2226. } else {
  2227. phy_data |= IGP02E1000_PM_D3_LPLU;
  2228. ret_val = e1000_write_phy_reg(hw,
  2229. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2230. if (ret_val)
  2231. return ret_val;
  2232. }
  2233. }
  2234. /* When LPLU is enabled we should disable SmartSpeed */
  2235. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2236. &phy_data);
  2237. if (ret_val)
  2238. return ret_val;
  2239. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2240. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2241. phy_data);
  2242. if (ret_val)
  2243. return ret_val;
  2244. }
  2245. return E1000_SUCCESS;
  2246. }
  2247. /*****************************************************************************
  2248. *
  2249. * This function sets the lplu d0 state according to the active flag. When
  2250. * activating lplu this function also disables smart speed and vise versa.
  2251. * lplu will not be activated unless the device autonegotiation advertisment
  2252. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2253. * hw: Struct containing variables accessed by shared code
  2254. * active - true to enable lplu false to disable lplu.
  2255. *
  2256. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2257. * E1000_SUCCESS at any other case.
  2258. *
  2259. ****************************************************************************/
  2260. static int32_t
  2261. e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
  2262. {
  2263. uint32_t phy_ctrl = 0;
  2264. int32_t ret_val;
  2265. uint16_t phy_data;
  2266. DEBUGFUNC();
  2267. if (hw->mac_type <= e1000_82547_rev_2)
  2268. return E1000_SUCCESS;
  2269. if (hw->mac_type == e1000_ich8lan) {
  2270. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2271. } else if (hw->mac_type == e1000_igb) {
  2272. phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
  2273. } else {
  2274. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2275. &phy_data);
  2276. if (ret_val)
  2277. return ret_val;
  2278. }
  2279. if (!active) {
  2280. if (hw->mac_type == e1000_ich8lan) {
  2281. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2282. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2283. } else if (hw->mac_type == e1000_igb) {
  2284. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2285. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2286. } else {
  2287. phy_data &= ~IGP02E1000_PM_D0_LPLU;
  2288. ret_val = e1000_write_phy_reg(hw,
  2289. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2290. if (ret_val)
  2291. return ret_val;
  2292. }
  2293. if (hw->mac_type == e1000_igb)
  2294. return E1000_SUCCESS;
  2295. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2296. * Dx states where the power conservation is most important. During
  2297. * driver activity we should enable SmartSpeed, so performance is
  2298. * maintained. */
  2299. if (hw->smart_speed == e1000_smart_speed_on) {
  2300. ret_val = e1000_read_phy_reg(hw,
  2301. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2302. if (ret_val)
  2303. return ret_val;
  2304. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2305. ret_val = e1000_write_phy_reg(hw,
  2306. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2307. if (ret_val)
  2308. return ret_val;
  2309. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2310. ret_val = e1000_read_phy_reg(hw,
  2311. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2312. if (ret_val)
  2313. return ret_val;
  2314. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2315. ret_val = e1000_write_phy_reg(hw,
  2316. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2317. if (ret_val)
  2318. return ret_val;
  2319. }
  2320. } else {
  2321. if (hw->mac_type == e1000_ich8lan) {
  2322. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2323. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2324. } else if (hw->mac_type == e1000_igb) {
  2325. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2326. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2327. } else {
  2328. phy_data |= IGP02E1000_PM_D0_LPLU;
  2329. ret_val = e1000_write_phy_reg(hw,
  2330. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2331. if (ret_val)
  2332. return ret_val;
  2333. }
  2334. if (hw->mac_type == e1000_igb)
  2335. return E1000_SUCCESS;
  2336. /* When LPLU is enabled we should disable SmartSpeed */
  2337. ret_val = e1000_read_phy_reg(hw,
  2338. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2339. if (ret_val)
  2340. return ret_val;
  2341. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2342. ret_val = e1000_write_phy_reg(hw,
  2343. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2344. if (ret_val)
  2345. return ret_val;
  2346. }
  2347. return E1000_SUCCESS;
  2348. }
  2349. /********************************************************************
  2350. * Copper link setup for e1000_phy_igp series.
  2351. *
  2352. * hw - Struct containing variables accessed by shared code
  2353. *********************************************************************/
  2354. static int32_t
  2355. e1000_copper_link_igp_setup(struct e1000_hw *hw)
  2356. {
  2357. uint32_t led_ctrl;
  2358. int32_t ret_val;
  2359. uint16_t phy_data;
  2360. DEBUGFUNC();
  2361. if (hw->phy_reset_disable)
  2362. return E1000_SUCCESS;
  2363. ret_val = e1000_phy_reset(hw);
  2364. if (ret_val) {
  2365. DEBUGOUT("Error Resetting the PHY\n");
  2366. return ret_val;
  2367. }
  2368. /* Wait 15ms for MAC to configure PHY from eeprom settings */
  2369. mdelay(15);
  2370. if (hw->mac_type != e1000_ich8lan) {
  2371. /* Configure activity LED after PHY reset */
  2372. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  2373. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  2374. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  2375. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  2376. }
  2377. /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
  2378. if (hw->phy_type == e1000_phy_igp) {
  2379. /* disable lplu d3 during driver init */
  2380. ret_val = e1000_set_d3_lplu_state(hw, false);
  2381. if (ret_val) {
  2382. DEBUGOUT("Error Disabling LPLU D3\n");
  2383. return ret_val;
  2384. }
  2385. }
  2386. /* disable lplu d0 during driver init */
  2387. ret_val = e1000_set_d0_lplu_state(hw, false);
  2388. if (ret_val) {
  2389. DEBUGOUT("Error Disabling LPLU D0\n");
  2390. return ret_val;
  2391. }
  2392. /* Configure mdi-mdix settings */
  2393. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  2394. if (ret_val)
  2395. return ret_val;
  2396. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  2397. hw->dsp_config_state = e1000_dsp_config_disabled;
  2398. /* Force MDI for earlier revs of the IGP PHY */
  2399. phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
  2400. | IGP01E1000_PSCR_FORCE_MDI_MDIX);
  2401. hw->mdix = 1;
  2402. } else {
  2403. hw->dsp_config_state = e1000_dsp_config_enabled;
  2404. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  2405. switch (hw->mdix) {
  2406. case 1:
  2407. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2408. break;
  2409. case 2:
  2410. phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2411. break;
  2412. case 0:
  2413. default:
  2414. phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
  2415. break;
  2416. }
  2417. }
  2418. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  2419. if (ret_val)
  2420. return ret_val;
  2421. /* set auto-master slave resolution settings */
  2422. if (hw->autoneg) {
  2423. e1000_ms_type phy_ms_setting = hw->master_slave;
  2424. if (hw->ffe_config_state == e1000_ffe_config_active)
  2425. hw->ffe_config_state = e1000_ffe_config_enabled;
  2426. if (hw->dsp_config_state == e1000_dsp_config_activated)
  2427. hw->dsp_config_state = e1000_dsp_config_enabled;
  2428. /* when autonegotiation advertisment is only 1000Mbps then we
  2429. * should disable SmartSpeed and enable Auto MasterSlave
  2430. * resolution as hardware default. */
  2431. if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
  2432. /* Disable SmartSpeed */
  2433. ret_val = e1000_read_phy_reg(hw,
  2434. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2435. if (ret_val)
  2436. return ret_val;
  2437. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2438. ret_val = e1000_write_phy_reg(hw,
  2439. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2440. if (ret_val)
  2441. return ret_val;
  2442. /* Set auto Master/Slave resolution process */
  2443. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2444. &phy_data);
  2445. if (ret_val)
  2446. return ret_val;
  2447. phy_data &= ~CR_1000T_MS_ENABLE;
  2448. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  2449. phy_data);
  2450. if (ret_val)
  2451. return ret_val;
  2452. }
  2453. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
  2454. if (ret_val)
  2455. return ret_val;
  2456. /* load defaults for future use */
  2457. hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
  2458. ((phy_data & CR_1000T_MS_VALUE) ?
  2459. e1000_ms_force_master :
  2460. e1000_ms_force_slave) :
  2461. e1000_ms_auto;
  2462. switch (phy_ms_setting) {
  2463. case e1000_ms_force_master:
  2464. phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  2465. break;
  2466. case e1000_ms_force_slave:
  2467. phy_data |= CR_1000T_MS_ENABLE;
  2468. phy_data &= ~(CR_1000T_MS_VALUE);
  2469. break;
  2470. case e1000_ms_auto:
  2471. phy_data &= ~CR_1000T_MS_ENABLE;
  2472. default:
  2473. break;
  2474. }
  2475. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
  2476. if (ret_val)
  2477. return ret_val;
  2478. }
  2479. return E1000_SUCCESS;
  2480. }
  2481. /*****************************************************************************
  2482. * This function checks the mode of the firmware.
  2483. *
  2484. * returns - true when the mode is IAMT or false.
  2485. ****************************************************************************/
  2486. bool
  2487. e1000_check_mng_mode(struct e1000_hw *hw)
  2488. {
  2489. uint32_t fwsm;
  2490. DEBUGFUNC();
  2491. fwsm = E1000_READ_REG(hw, FWSM);
  2492. if (hw->mac_type == e1000_ich8lan) {
  2493. if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2494. (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2495. return true;
  2496. } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2497. (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2498. return true;
  2499. return false;
  2500. }
  2501. static int32_t
  2502. e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
  2503. {
  2504. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2505. uint32_t reg_val;
  2506. DEBUGFUNC();
  2507. if (e1000_is_second_port(hw))
  2508. swfw = E1000_SWFW_PHY1_SM;
  2509. if (e1000_swfw_sync_acquire(hw, swfw))
  2510. return -E1000_ERR_SWFW_SYNC;
  2511. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
  2512. & E1000_KUMCTRLSTA_OFFSET) | data;
  2513. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2514. udelay(2);
  2515. return E1000_SUCCESS;
  2516. }
  2517. static int32_t
  2518. e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
  2519. {
  2520. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2521. uint32_t reg_val;
  2522. DEBUGFUNC();
  2523. if (e1000_is_second_port(hw))
  2524. swfw = E1000_SWFW_PHY1_SM;
  2525. if (e1000_swfw_sync_acquire(hw, swfw)) {
  2526. debug("%s[%i]\n", __func__, __LINE__);
  2527. return -E1000_ERR_SWFW_SYNC;
  2528. }
  2529. /* Write register address */
  2530. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
  2531. E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
  2532. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2533. udelay(2);
  2534. /* Read the data returned */
  2535. reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
  2536. *data = (uint16_t)reg_val;
  2537. return E1000_SUCCESS;
  2538. }
  2539. /********************************************************************
  2540. * Copper link setup for e1000_phy_gg82563 series.
  2541. *
  2542. * hw - Struct containing variables accessed by shared code
  2543. *********************************************************************/
  2544. static int32_t
  2545. e1000_copper_link_ggp_setup(struct e1000_hw *hw)
  2546. {
  2547. int32_t ret_val;
  2548. uint16_t phy_data;
  2549. uint32_t reg_data;
  2550. DEBUGFUNC();
  2551. if (!hw->phy_reset_disable) {
  2552. /* Enable CRS on TX for half-duplex operation. */
  2553. ret_val = e1000_read_phy_reg(hw,
  2554. GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  2555. if (ret_val)
  2556. return ret_val;
  2557. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  2558. /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
  2559. phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
  2560. ret_val = e1000_write_phy_reg(hw,
  2561. GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  2562. if (ret_val)
  2563. return ret_val;
  2564. /* Options:
  2565. * MDI/MDI-X = 0 (default)
  2566. * 0 - Auto for all speeds
  2567. * 1 - MDI mode
  2568. * 2 - MDI-X mode
  2569. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2570. */
  2571. ret_val = e1000_read_phy_reg(hw,
  2572. GG82563_PHY_SPEC_CTRL, &phy_data);
  2573. if (ret_val)
  2574. return ret_val;
  2575. phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  2576. switch (hw->mdix) {
  2577. case 1:
  2578. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  2579. break;
  2580. case 2:
  2581. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  2582. break;
  2583. case 0:
  2584. default:
  2585. phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  2586. break;
  2587. }
  2588. /* Options:
  2589. * disable_polarity_correction = 0 (default)
  2590. * Automatic Correction for Reversed Cable Polarity
  2591. * 0 - Disabled
  2592. * 1 - Enabled
  2593. */
  2594. phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  2595. ret_val = e1000_write_phy_reg(hw,
  2596. GG82563_PHY_SPEC_CTRL, phy_data);
  2597. if (ret_val)
  2598. return ret_val;
  2599. /* SW Reset the PHY so all changes take effect */
  2600. ret_val = e1000_phy_reset(hw);
  2601. if (ret_val) {
  2602. DEBUGOUT("Error Resetting the PHY\n");
  2603. return ret_val;
  2604. }
  2605. } /* phy_reset_disable */
  2606. if (hw->mac_type == e1000_80003es2lan) {
  2607. /* Bypass RX and TX FIFO's */
  2608. ret_val = e1000_write_kmrn_reg(hw,
  2609. E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
  2610. E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
  2611. | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
  2612. if (ret_val)
  2613. return ret_val;
  2614. ret_val = e1000_read_phy_reg(hw,
  2615. GG82563_PHY_SPEC_CTRL_2, &phy_data);
  2616. if (ret_val)
  2617. return ret_val;
  2618. phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
  2619. ret_val = e1000_write_phy_reg(hw,
  2620. GG82563_PHY_SPEC_CTRL_2, phy_data);
  2621. if (ret_val)
  2622. return ret_val;
  2623. reg_data = E1000_READ_REG(hw, CTRL_EXT);
  2624. reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
  2625. E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
  2626. ret_val = e1000_read_phy_reg(hw,
  2627. GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
  2628. if (ret_val)
  2629. return ret_val;
  2630. /* Do not init these registers when the HW is in IAMT mode, since the
  2631. * firmware will have already initialized them. We only initialize
  2632. * them if the HW is not in IAMT mode.
  2633. */
  2634. if (e1000_check_mng_mode(hw) == false) {
  2635. /* Enable Electrical Idle on the PHY */
  2636. phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
  2637. ret_val = e1000_write_phy_reg(hw,
  2638. GG82563_PHY_PWR_MGMT_CTRL, phy_data);
  2639. if (ret_val)
  2640. return ret_val;
  2641. ret_val = e1000_read_phy_reg(hw,
  2642. GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
  2643. if (ret_val)
  2644. return ret_val;
  2645. phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  2646. ret_val = e1000_write_phy_reg(hw,
  2647. GG82563_PHY_KMRN_MODE_CTRL, phy_data);
  2648. if (ret_val)
  2649. return ret_val;
  2650. }
  2651. /* Workaround: Disable padding in Kumeran interface in the MAC
  2652. * and in the PHY to avoid CRC errors.
  2653. */
  2654. ret_val = e1000_read_phy_reg(hw,
  2655. GG82563_PHY_INBAND_CTRL, &phy_data);
  2656. if (ret_val)
  2657. return ret_val;
  2658. phy_data |= GG82563_ICR_DIS_PADDING;
  2659. ret_val = e1000_write_phy_reg(hw,
  2660. GG82563_PHY_INBAND_CTRL, phy_data);
  2661. if (ret_val)
  2662. return ret_val;
  2663. }
  2664. return E1000_SUCCESS;
  2665. }
  2666. /********************************************************************
  2667. * Copper link setup for e1000_phy_m88 series.
  2668. *
  2669. * hw - Struct containing variables accessed by shared code
  2670. *********************************************************************/
  2671. static int32_t
  2672. e1000_copper_link_mgp_setup(struct e1000_hw *hw)
  2673. {
  2674. int32_t ret_val;
  2675. uint16_t phy_data;
  2676. DEBUGFUNC();
  2677. if (hw->phy_reset_disable)
  2678. return E1000_SUCCESS;
  2679. /* Enable CRS on TX. This must be set for half-duplex operation. */
  2680. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  2681. if (ret_val)
  2682. return ret_val;
  2683. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  2684. /* Options:
  2685. * MDI/MDI-X = 0 (default)
  2686. * 0 - Auto for all speeds
  2687. * 1 - MDI mode
  2688. * 2 - MDI-X mode
  2689. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2690. */
  2691. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  2692. switch (hw->mdix) {
  2693. case 1:
  2694. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  2695. break;
  2696. case 2:
  2697. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  2698. break;
  2699. case 3:
  2700. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  2701. break;
  2702. case 0:
  2703. default:
  2704. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  2705. break;
  2706. }
  2707. /* Options:
  2708. * disable_polarity_correction = 0 (default)
  2709. * Automatic Correction for Reversed Cable Polarity
  2710. * 0 - Disabled
  2711. * 1 - Enabled
  2712. */
  2713. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  2714. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  2715. if (ret_val)
  2716. return ret_val;
  2717. if (hw->phy_revision < M88E1011_I_REV_4) {
  2718. /* Force TX_CLK in the Extended PHY Specific Control Register
  2719. * to 25MHz clock.
  2720. */
  2721. ret_val = e1000_read_phy_reg(hw,
  2722. M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  2723. if (ret_val)
  2724. return ret_val;
  2725. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  2726. if ((hw->phy_revision == E1000_REVISION_2) &&
  2727. (hw->phy_id == M88E1111_I_PHY_ID)) {
  2728. /* Vidalia Phy, set the downshift counter to 5x */
  2729. phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
  2730. phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  2731. ret_val = e1000_write_phy_reg(hw,
  2732. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2733. if (ret_val)
  2734. return ret_val;
  2735. } else {
  2736. /* Configure Master and Slave downshift values */
  2737. phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
  2738. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  2739. phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
  2740. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  2741. ret_val = e1000_write_phy_reg(hw,
  2742. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2743. if (ret_val)
  2744. return ret_val;
  2745. }
  2746. }
  2747. /* SW Reset the PHY so all changes take effect */
  2748. ret_val = e1000_phy_reset(hw);
  2749. if (ret_val) {
  2750. DEBUGOUT("Error Resetting the PHY\n");
  2751. return ret_val;
  2752. }
  2753. return E1000_SUCCESS;
  2754. }
  2755. /********************************************************************
  2756. * Setup auto-negotiation and flow control advertisements,
  2757. * and then perform auto-negotiation.
  2758. *
  2759. * hw - Struct containing variables accessed by shared code
  2760. *********************************************************************/
  2761. static int32_t
  2762. e1000_copper_link_autoneg(struct e1000_hw *hw)
  2763. {
  2764. int32_t ret_val;
  2765. uint16_t phy_data;
  2766. DEBUGFUNC();
  2767. /* Perform some bounds checking on the hw->autoneg_advertised
  2768. * parameter. If this variable is zero, then set it to the default.
  2769. */
  2770. hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2771. /* If autoneg_advertised is zero, we assume it was not defaulted
  2772. * by the calling code so we set to advertise full capability.
  2773. */
  2774. if (hw->autoneg_advertised == 0)
  2775. hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2776. /* IFE phy only supports 10/100 */
  2777. if (hw->phy_type == e1000_phy_ife)
  2778. hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
  2779. DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  2780. ret_val = e1000_phy_setup_autoneg(hw);
  2781. if (ret_val) {
  2782. DEBUGOUT("Error Setting up Auto-Negotiation\n");
  2783. return ret_val;
  2784. }
  2785. DEBUGOUT("Restarting Auto-Neg\n");
  2786. /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  2787. * the Auto Neg Restart bit in the PHY control register.
  2788. */
  2789. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  2790. if (ret_val)
  2791. return ret_val;
  2792. phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  2793. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  2794. if (ret_val)
  2795. return ret_val;
  2796. /* Does the user want to wait for Auto-Neg to complete here, or
  2797. * check at a later time (for example, callback routine).
  2798. */
  2799. /* If we do not wait for autonegtation to complete I
  2800. * do not see a valid link status.
  2801. * wait_autoneg_complete = 1 .
  2802. */
  2803. if (hw->wait_autoneg_complete) {
  2804. ret_val = e1000_wait_autoneg(hw);
  2805. if (ret_val) {
  2806. DEBUGOUT("Error while waiting for autoneg"
  2807. "to complete\n");
  2808. return ret_val;
  2809. }
  2810. }
  2811. hw->get_link_status = true;
  2812. return E1000_SUCCESS;
  2813. }
  2814. /******************************************************************************
  2815. * Config the MAC and the PHY after link is up.
  2816. * 1) Set up the MAC to the current PHY speed/duplex
  2817. * if we are on 82543. If we
  2818. * are on newer silicon, we only need to configure
  2819. * collision distance in the Transmit Control Register.
  2820. * 2) Set up flow control on the MAC to that established with
  2821. * the link partner.
  2822. * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
  2823. *
  2824. * hw - Struct containing variables accessed by shared code
  2825. ******************************************************************************/
  2826. static int32_t
  2827. e1000_copper_link_postconfig(struct e1000_hw *hw)
  2828. {
  2829. int32_t ret_val;
  2830. DEBUGFUNC();
  2831. if (hw->mac_type >= e1000_82544) {
  2832. e1000_config_collision_dist(hw);
  2833. } else {
  2834. ret_val = e1000_config_mac_to_phy(hw);
  2835. if (ret_val) {
  2836. DEBUGOUT("Error configuring MAC to PHY settings\n");
  2837. return ret_val;
  2838. }
  2839. }
  2840. ret_val = e1000_config_fc_after_link_up(hw);
  2841. if (ret_val) {
  2842. DEBUGOUT("Error Configuring Flow Control\n");
  2843. return ret_val;
  2844. }
  2845. return E1000_SUCCESS;
  2846. }
  2847. /******************************************************************************
  2848. * Detects which PHY is present and setup the speed and duplex
  2849. *
  2850. * hw - Struct containing variables accessed by shared code
  2851. ******************************************************************************/
  2852. static int
  2853. e1000_setup_copper_link(struct e1000_hw *hw)
  2854. {
  2855. int32_t ret_val;
  2856. uint16_t i;
  2857. uint16_t phy_data;
  2858. uint16_t reg_data;
  2859. DEBUGFUNC();
  2860. switch (hw->mac_type) {
  2861. case e1000_80003es2lan:
  2862. case e1000_ich8lan:
  2863. /* Set the mac to wait the maximum time between each
  2864. * iteration and increase the max iterations when
  2865. * polling the phy; this fixes erroneous timeouts at 10Mbps. */
  2866. ret_val = e1000_write_kmrn_reg(hw,
  2867. GG82563_REG(0x34, 4), 0xFFFF);
  2868. if (ret_val)
  2869. return ret_val;
  2870. ret_val = e1000_read_kmrn_reg(hw,
  2871. GG82563_REG(0x34, 9), &reg_data);
  2872. if (ret_val)
  2873. return ret_val;
  2874. reg_data |= 0x3F;
  2875. ret_val = e1000_write_kmrn_reg(hw,
  2876. GG82563_REG(0x34, 9), reg_data);
  2877. if (ret_val)
  2878. return ret_val;
  2879. default:
  2880. break;
  2881. }
  2882. /* Check if it is a valid PHY and set PHY mode if necessary. */
  2883. ret_val = e1000_copper_link_preconfig(hw);
  2884. if (ret_val)
  2885. return ret_val;
  2886. switch (hw->mac_type) {
  2887. case e1000_80003es2lan:
  2888. /* Kumeran registers are written-only */
  2889. reg_data =
  2890. E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
  2891. reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
  2892. ret_val = e1000_write_kmrn_reg(hw,
  2893. E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
  2894. if (ret_val)
  2895. return ret_val;
  2896. break;
  2897. default:
  2898. break;
  2899. }
  2900. if (hw->phy_type == e1000_phy_igp ||
  2901. hw->phy_type == e1000_phy_igp_3 ||
  2902. hw->phy_type == e1000_phy_igp_2) {
  2903. ret_val = e1000_copper_link_igp_setup(hw);
  2904. if (ret_val)
  2905. return ret_val;
  2906. } else if (hw->phy_type == e1000_phy_m88 ||
  2907. hw->phy_type == e1000_phy_igb) {
  2908. ret_val = e1000_copper_link_mgp_setup(hw);
  2909. if (ret_val)
  2910. return ret_val;
  2911. } else if (hw->phy_type == e1000_phy_gg82563) {
  2912. ret_val = e1000_copper_link_ggp_setup(hw);
  2913. if (ret_val)
  2914. return ret_val;
  2915. }
  2916. /* always auto */
  2917. /* Setup autoneg and flow control advertisement
  2918. * and perform autonegotiation */
  2919. ret_val = e1000_copper_link_autoneg(hw);
  2920. if (ret_val)
  2921. return ret_val;
  2922. /* Check link status. Wait up to 100 microseconds for link to become
  2923. * valid.
  2924. */
  2925. for (i = 0; i < 10; i++) {
  2926. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2927. if (ret_val)
  2928. return ret_val;
  2929. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2930. if (ret_val)
  2931. return ret_val;
  2932. if (phy_data & MII_SR_LINK_STATUS) {
  2933. /* Config the MAC and PHY after link is up */
  2934. ret_val = e1000_copper_link_postconfig(hw);
  2935. if (ret_val)
  2936. return ret_val;
  2937. DEBUGOUT("Valid link established!!!\n");
  2938. return E1000_SUCCESS;
  2939. }
  2940. udelay(10);
  2941. }
  2942. DEBUGOUT("Unable to establish link!!!\n");
  2943. return E1000_SUCCESS;
  2944. }
  2945. /******************************************************************************
  2946. * Configures PHY autoneg and flow control advertisement settings
  2947. *
  2948. * hw - Struct containing variables accessed by shared code
  2949. ******************************************************************************/
  2950. int32_t
  2951. e1000_phy_setup_autoneg(struct e1000_hw *hw)
  2952. {
  2953. int32_t ret_val;
  2954. uint16_t mii_autoneg_adv_reg;
  2955. uint16_t mii_1000t_ctrl_reg;
  2956. DEBUGFUNC();
  2957. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  2958. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
  2959. if (ret_val)
  2960. return ret_val;
  2961. if (hw->phy_type != e1000_phy_ife) {
  2962. /* Read the MII 1000Base-T Control Register (Address 9). */
  2963. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2964. &mii_1000t_ctrl_reg);
  2965. if (ret_val)
  2966. return ret_val;
  2967. } else
  2968. mii_1000t_ctrl_reg = 0;
  2969. /* Need to parse both autoneg_advertised and fc and set up
  2970. * the appropriate PHY registers. First we will parse for
  2971. * autoneg_advertised software override. Since we can advertise
  2972. * a plethora of combinations, we need to check each bit
  2973. * individually.
  2974. */
  2975. /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  2976. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  2977. * the 1000Base-T Control Register (Address 9).
  2978. */
  2979. mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
  2980. mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
  2981. DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
  2982. /* Do we want to advertise 10 Mb Half Duplex? */
  2983. if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
  2984. DEBUGOUT("Advertise 10mb Half duplex\n");
  2985. mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  2986. }
  2987. /* Do we want to advertise 10 Mb Full Duplex? */
  2988. if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
  2989. DEBUGOUT("Advertise 10mb Full duplex\n");
  2990. mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  2991. }
  2992. /* Do we want to advertise 100 Mb Half Duplex? */
  2993. if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
  2994. DEBUGOUT("Advertise 100mb Half duplex\n");
  2995. mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  2996. }
  2997. /* Do we want to advertise 100 Mb Full Duplex? */
  2998. if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
  2999. DEBUGOUT("Advertise 100mb Full duplex\n");
  3000. mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  3001. }
  3002. /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  3003. if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
  3004. DEBUGOUT
  3005. ("Advertise 1000mb Half duplex requested, request denied!\n");
  3006. }
  3007. /* Do we want to advertise 1000 Mb Full Duplex? */
  3008. if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
  3009. DEBUGOUT("Advertise 1000mb Full duplex\n");
  3010. mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  3011. }
  3012. /* Check for a software override of the flow control settings, and
  3013. * setup the PHY advertisement registers accordingly. If
  3014. * auto-negotiation is enabled, then software will have to set the
  3015. * "PAUSE" bits to the correct value in the Auto-Negotiation
  3016. * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
  3017. *
  3018. * The possible values of the "fc" parameter are:
  3019. * 0: Flow control is completely disabled
  3020. * 1: Rx flow control is enabled (we can receive pause frames
  3021. * but not send pause frames).
  3022. * 2: Tx flow control is enabled (we can send pause frames
  3023. * but we do not support receiving pause frames).
  3024. * 3: Both Rx and TX flow control (symmetric) are enabled.
  3025. * other: No software override. The flow control configuration
  3026. * in the EEPROM is used.
  3027. */
  3028. switch (hw->fc) {
  3029. case e1000_fc_none: /* 0 */
  3030. /* Flow control (RX & TX) is completely disabled by a
  3031. * software over-ride.
  3032. */
  3033. mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3034. break;
  3035. case e1000_fc_rx_pause: /* 1 */
  3036. /* RX Flow control is enabled, and TX Flow control is
  3037. * disabled, by a software over-ride.
  3038. */
  3039. /* Since there really isn't a way to advertise that we are
  3040. * capable of RX Pause ONLY, we will advertise that we
  3041. * support both symmetric and asymmetric RX PAUSE. Later
  3042. * (in e1000_config_fc_after_link_up) we will disable the
  3043. *hw's ability to send PAUSE frames.
  3044. */
  3045. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3046. break;
  3047. case e1000_fc_tx_pause: /* 2 */
  3048. /* TX Flow control is enabled, and RX Flow control is
  3049. * disabled, by a software over-ride.
  3050. */
  3051. mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  3052. mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  3053. break;
  3054. case e1000_fc_full: /* 3 */
  3055. /* Flow control (both RX and TX) is enabled by a software
  3056. * over-ride.
  3057. */
  3058. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3059. break;
  3060. default:
  3061. DEBUGOUT("Flow control param set incorrectly\n");
  3062. return -E1000_ERR_CONFIG;
  3063. }
  3064. ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
  3065. if (ret_val)
  3066. return ret_val;
  3067. DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  3068. if (hw->phy_type != e1000_phy_ife) {
  3069. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  3070. mii_1000t_ctrl_reg);
  3071. if (ret_val)
  3072. return ret_val;
  3073. }
  3074. return E1000_SUCCESS;
  3075. }
  3076. /******************************************************************************
  3077. * Sets the collision distance in the Transmit Control register
  3078. *
  3079. * hw - Struct containing variables accessed by shared code
  3080. *
  3081. * Link should have been established previously. Reads the speed and duplex
  3082. * information from the Device Status register.
  3083. ******************************************************************************/
  3084. static void
  3085. e1000_config_collision_dist(struct e1000_hw *hw)
  3086. {
  3087. uint32_t tctl, coll_dist;
  3088. DEBUGFUNC();
  3089. if (hw->mac_type < e1000_82543)
  3090. coll_dist = E1000_COLLISION_DISTANCE_82542;
  3091. else
  3092. coll_dist = E1000_COLLISION_DISTANCE;
  3093. tctl = E1000_READ_REG(hw, TCTL);
  3094. tctl &= ~E1000_TCTL_COLD;
  3095. tctl |= coll_dist << E1000_COLD_SHIFT;
  3096. E1000_WRITE_REG(hw, TCTL, tctl);
  3097. E1000_WRITE_FLUSH(hw);
  3098. }
  3099. /******************************************************************************
  3100. * Sets MAC speed and duplex settings to reflect the those in the PHY
  3101. *
  3102. * hw - Struct containing variables accessed by shared code
  3103. * mii_reg - data to write to the MII control register
  3104. *
  3105. * The contents of the PHY register containing the needed information need to
  3106. * be passed in.
  3107. ******************************************************************************/
  3108. static int
  3109. e1000_config_mac_to_phy(struct e1000_hw *hw)
  3110. {
  3111. uint32_t ctrl;
  3112. uint16_t phy_data;
  3113. DEBUGFUNC();
  3114. /* Read the Device Control Register and set the bits to Force Speed
  3115. * and Duplex.
  3116. */
  3117. ctrl = E1000_READ_REG(hw, CTRL);
  3118. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  3119. ctrl &= ~(E1000_CTRL_ILOS);
  3120. ctrl |= (E1000_CTRL_SPD_SEL);
  3121. /* Set up duplex in the Device Control and Transmit Control
  3122. * registers depending on negotiated values.
  3123. */
  3124. if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
  3125. DEBUGOUT("PHY Read Error\n");
  3126. return -E1000_ERR_PHY;
  3127. }
  3128. if (phy_data & M88E1000_PSSR_DPLX)
  3129. ctrl |= E1000_CTRL_FD;
  3130. else
  3131. ctrl &= ~E1000_CTRL_FD;
  3132. e1000_config_collision_dist(hw);
  3133. /* Set up speed in the Device Control register depending on
  3134. * negotiated values.
  3135. */
  3136. if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  3137. ctrl |= E1000_CTRL_SPD_1000;
  3138. else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  3139. ctrl |= E1000_CTRL_SPD_100;
  3140. /* Write the configured values back to the Device Control Reg. */
  3141. E1000_WRITE_REG(hw, CTRL, ctrl);
  3142. return 0;
  3143. }
  3144. /******************************************************************************
  3145. * Forces the MAC's flow control settings.
  3146. *
  3147. * hw - Struct containing variables accessed by shared code
  3148. *
  3149. * Sets the TFCE and RFCE bits in the device control register to reflect
  3150. * the adapter settings. TFCE and RFCE need to be explicitly set by
  3151. * software when a Copper PHY is used because autonegotiation is managed
  3152. * by the PHY rather than the MAC. Software must also configure these
  3153. * bits when link is forced on a fiber connection.
  3154. *****************************************************************************/
  3155. static int
  3156. e1000_force_mac_fc(struct e1000_hw *hw)
  3157. {
  3158. uint32_t ctrl;
  3159. DEBUGFUNC();
  3160. /* Get the current configuration of the Device Control Register */
  3161. ctrl = E1000_READ_REG(hw, CTRL);
  3162. /* Because we didn't get link via the internal auto-negotiation
  3163. * mechanism (we either forced link or we got link via PHY
  3164. * auto-neg), we have to manually enable/disable transmit an
  3165. * receive flow control.
  3166. *
  3167. * The "Case" statement below enables/disable flow control
  3168. * according to the "hw->fc" parameter.
  3169. *
  3170. * The possible values of the "fc" parameter are:
  3171. * 0: Flow control is completely disabled
  3172. * 1: Rx flow control is enabled (we can receive pause
  3173. * frames but not send pause frames).
  3174. * 2: Tx flow control is enabled (we can send pause frames
  3175. * frames but we do not receive pause frames).
  3176. * 3: Both Rx and TX flow control (symmetric) is enabled.
  3177. * other: No other values should be possible at this point.
  3178. */
  3179. switch (hw->fc) {
  3180. case e1000_fc_none:
  3181. ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  3182. break;
  3183. case e1000_fc_rx_pause:
  3184. ctrl &= (~E1000_CTRL_TFCE);
  3185. ctrl |= E1000_CTRL_RFCE;
  3186. break;
  3187. case e1000_fc_tx_pause:
  3188. ctrl &= (~E1000_CTRL_RFCE);
  3189. ctrl |= E1000_CTRL_TFCE;
  3190. break;
  3191. case e1000_fc_full:
  3192. ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  3193. break;
  3194. default:
  3195. DEBUGOUT("Flow control param set incorrectly\n");
  3196. return -E1000_ERR_CONFIG;
  3197. }
  3198. /* Disable TX Flow Control for 82542 (rev 2.0) */
  3199. if (hw->mac_type == e1000_82542_rev2_0)
  3200. ctrl &= (~E1000_CTRL_TFCE);
  3201. E1000_WRITE_REG(hw, CTRL, ctrl);
  3202. return 0;
  3203. }
  3204. /******************************************************************************
  3205. * Configures flow control settings after link is established
  3206. *
  3207. * hw - Struct containing variables accessed by shared code
  3208. *
  3209. * Should be called immediately after a valid link has been established.
  3210. * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  3211. * and autonegotiation is enabled, the MAC flow control settings will be set
  3212. * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
  3213. * and RFCE bits will be automaticaly set to the negotiated flow control mode.
  3214. *****************************************************************************/
  3215. static int32_t
  3216. e1000_config_fc_after_link_up(struct e1000_hw *hw)
  3217. {
  3218. int32_t ret_val;
  3219. uint16_t mii_status_reg;
  3220. uint16_t mii_nway_adv_reg;
  3221. uint16_t mii_nway_lp_ability_reg;
  3222. uint16_t speed;
  3223. uint16_t duplex;
  3224. DEBUGFUNC();
  3225. /* Check for the case where we have fiber media and auto-neg failed
  3226. * so we had to force link. In this case, we need to force the
  3227. * configuration of the MAC to match the "fc" parameter.
  3228. */
  3229. if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
  3230. || ((hw->media_type == e1000_media_type_internal_serdes)
  3231. && (hw->autoneg_failed))
  3232. || ((hw->media_type == e1000_media_type_copper)
  3233. && (!hw->autoneg))) {
  3234. ret_val = e1000_force_mac_fc(hw);
  3235. if (ret_val < 0) {
  3236. DEBUGOUT("Error forcing flow control settings\n");
  3237. return ret_val;
  3238. }
  3239. }
  3240. /* Check for the case where we have copper media and auto-neg is
  3241. * enabled. In this case, we need to check and see if Auto-Neg
  3242. * has completed, and if so, how the PHY and link partner has
  3243. * flow control configured.
  3244. */
  3245. if (hw->media_type == e1000_media_type_copper) {
  3246. /* Read the MII Status Register and check to see if AutoNeg
  3247. * has completed. We read this twice because this reg has
  3248. * some "sticky" (latched) bits.
  3249. */
  3250. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3251. DEBUGOUT("PHY Read Error\n");
  3252. return -E1000_ERR_PHY;
  3253. }
  3254. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3255. DEBUGOUT("PHY Read Error\n");
  3256. return -E1000_ERR_PHY;
  3257. }
  3258. if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  3259. /* The AutoNeg process has completed, so we now need to
  3260. * read both the Auto Negotiation Advertisement Register
  3261. * (Address 4) and the Auto_Negotiation Base Page Ability
  3262. * Register (Address 5) to determine how flow control was
  3263. * negotiated.
  3264. */
  3265. if (e1000_read_phy_reg
  3266. (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
  3267. DEBUGOUT("PHY Read Error\n");
  3268. return -E1000_ERR_PHY;
  3269. }
  3270. if (e1000_read_phy_reg
  3271. (hw, PHY_LP_ABILITY,
  3272. &mii_nway_lp_ability_reg) < 0) {
  3273. DEBUGOUT("PHY Read Error\n");
  3274. return -E1000_ERR_PHY;
  3275. }
  3276. /* Two bits in the Auto Negotiation Advertisement Register
  3277. * (Address 4) and two bits in the Auto Negotiation Base
  3278. * Page Ability Register (Address 5) determine flow control
  3279. * for both the PHY and the link partner. The following
  3280. * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  3281. * 1999, describes these PAUSE resolution bits and how flow
  3282. * control is determined based upon these settings.
  3283. * NOTE: DC = Don't Care
  3284. *
  3285. * LOCAL DEVICE | LINK PARTNER
  3286. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  3287. *-------|---------|-------|---------|--------------------
  3288. * 0 | 0 | DC | DC | e1000_fc_none
  3289. * 0 | 1 | 0 | DC | e1000_fc_none
  3290. * 0 | 1 | 1 | 0 | e1000_fc_none
  3291. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3292. * 1 | 0 | 0 | DC | e1000_fc_none
  3293. * 1 | DC | 1 | DC | e1000_fc_full
  3294. * 1 | 1 | 0 | 0 | e1000_fc_none
  3295. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3296. *
  3297. */
  3298. /* Are both PAUSE bits set to 1? If so, this implies
  3299. * Symmetric Flow Control is enabled at both ends. The
  3300. * ASM_DIR bits are irrelevant per the spec.
  3301. *
  3302. * For Symmetric Flow Control:
  3303. *
  3304. * LOCAL DEVICE | LINK PARTNER
  3305. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3306. *-------|---------|-------|---------|--------------------
  3307. * 1 | DC | 1 | DC | e1000_fc_full
  3308. *
  3309. */
  3310. if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3311. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  3312. /* Now we need to check if the user selected RX ONLY
  3313. * of pause frames. In this case, we had to advertise
  3314. * FULL flow control because we could not advertise RX
  3315. * ONLY. Hence, we must now check to see if we need to
  3316. * turn OFF the TRANSMISSION of PAUSE frames.
  3317. */
  3318. if (hw->original_fc == e1000_fc_full) {
  3319. hw->fc = e1000_fc_full;
  3320. DEBUGOUT("Flow Control = FULL.\r\n");
  3321. } else {
  3322. hw->fc = e1000_fc_rx_pause;
  3323. DEBUGOUT
  3324. ("Flow Control = RX PAUSE frames only.\r\n");
  3325. }
  3326. }
  3327. /* For receiving PAUSE frames ONLY.
  3328. *
  3329. * LOCAL DEVICE | LINK PARTNER
  3330. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3331. *-------|---------|-------|---------|--------------------
  3332. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3333. *
  3334. */
  3335. else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3336. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3337. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3338. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3339. {
  3340. hw->fc = e1000_fc_tx_pause;
  3341. DEBUGOUT
  3342. ("Flow Control = TX PAUSE frames only.\r\n");
  3343. }
  3344. /* For transmitting PAUSE frames ONLY.
  3345. *
  3346. * LOCAL DEVICE | LINK PARTNER
  3347. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3348. *-------|---------|-------|---------|--------------------
  3349. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3350. *
  3351. */
  3352. else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3353. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3354. !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3355. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3356. {
  3357. hw->fc = e1000_fc_rx_pause;
  3358. DEBUGOUT
  3359. ("Flow Control = RX PAUSE frames only.\r\n");
  3360. }
  3361. /* Per the IEEE spec, at this point flow control should be
  3362. * disabled. However, we want to consider that we could
  3363. * be connected to a legacy switch that doesn't advertise
  3364. * desired flow control, but can be forced on the link
  3365. * partner. So if we advertised no flow control, that is
  3366. * what we will resolve to. If we advertised some kind of
  3367. * receive capability (Rx Pause Only or Full Flow Control)
  3368. * and the link partner advertised none, we will configure
  3369. * ourselves to enable Rx Flow Control only. We can do
  3370. * this safely for two reasons: If the link partner really
  3371. * didn't want flow control enabled, and we enable Rx, no
  3372. * harm done since we won't be receiving any PAUSE frames
  3373. * anyway. If the intent on the link partner was to have
  3374. * flow control enabled, then by us enabling RX only, we
  3375. * can at least receive pause frames and process them.
  3376. * This is a good idea because in most cases, since we are
  3377. * predominantly a server NIC, more times than not we will
  3378. * be asked to delay transmission of packets than asking
  3379. * our link partner to pause transmission of frames.
  3380. */
  3381. else if (hw->original_fc == e1000_fc_none ||
  3382. hw->original_fc == e1000_fc_tx_pause) {
  3383. hw->fc = e1000_fc_none;
  3384. DEBUGOUT("Flow Control = NONE.\r\n");
  3385. } else {
  3386. hw->fc = e1000_fc_rx_pause;
  3387. DEBUGOUT
  3388. ("Flow Control = RX PAUSE frames only.\r\n");
  3389. }
  3390. /* Now we need to do one last check... If we auto-
  3391. * negotiated to HALF DUPLEX, flow control should not be
  3392. * enabled per IEEE 802.3 spec.
  3393. */
  3394. e1000_get_speed_and_duplex(hw, &speed, &duplex);
  3395. if (duplex == HALF_DUPLEX)
  3396. hw->fc = e1000_fc_none;
  3397. /* Now we call a subroutine to actually force the MAC
  3398. * controller to use the correct flow control settings.
  3399. */
  3400. ret_val = e1000_force_mac_fc(hw);
  3401. if (ret_val < 0) {
  3402. DEBUGOUT
  3403. ("Error forcing flow control settings\n");
  3404. return ret_val;
  3405. }
  3406. } else {
  3407. DEBUGOUT
  3408. ("Copper PHY and Auto Neg has not completed.\r\n");
  3409. }
  3410. }
  3411. return E1000_SUCCESS;
  3412. }
  3413. /******************************************************************************
  3414. * Checks to see if the link status of the hardware has changed.
  3415. *
  3416. * hw - Struct containing variables accessed by shared code
  3417. *
  3418. * Called by any function that needs to check the link status of the adapter.
  3419. *****************************************************************************/
  3420. static int
  3421. e1000_check_for_link(struct e1000_hw *hw)
  3422. {
  3423. uint32_t rxcw;
  3424. uint32_t ctrl;
  3425. uint32_t status;
  3426. uint32_t rctl;
  3427. uint32_t signal;
  3428. int32_t ret_val;
  3429. uint16_t phy_data;
  3430. uint16_t lp_capability;
  3431. DEBUGFUNC();
  3432. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  3433. * set when the optics detect a signal. On older adapters, it will be
  3434. * cleared when there is a signal
  3435. */
  3436. ctrl = E1000_READ_REG(hw, CTRL);
  3437. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  3438. signal = E1000_CTRL_SWDPIN1;
  3439. else
  3440. signal = 0;
  3441. status = E1000_READ_REG(hw, STATUS);
  3442. rxcw = E1000_READ_REG(hw, RXCW);
  3443. DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
  3444. /* If we have a copper PHY then we only want to go out to the PHY
  3445. * registers to see if Auto-Neg has completed and/or if our link
  3446. * status has changed. The get_link_status flag will be set if we
  3447. * receive a Link Status Change interrupt or we have Rx Sequence
  3448. * Errors.
  3449. */
  3450. if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
  3451. /* First we want to see if the MII Status Register reports
  3452. * link. If so, then we want to get the current speed/duplex
  3453. * of the PHY.
  3454. * Read the register twice since the link bit is sticky.
  3455. */
  3456. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3457. DEBUGOUT("PHY Read Error\n");
  3458. return -E1000_ERR_PHY;
  3459. }
  3460. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3461. DEBUGOUT("PHY Read Error\n");
  3462. return -E1000_ERR_PHY;
  3463. }
  3464. if (phy_data & MII_SR_LINK_STATUS) {
  3465. hw->get_link_status = false;
  3466. } else {
  3467. /* No link detected */
  3468. return -E1000_ERR_NOLINK;
  3469. }
  3470. /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
  3471. * have Si on board that is 82544 or newer, Auto
  3472. * Speed Detection takes care of MAC speed/duplex
  3473. * configuration. So we only need to configure Collision
  3474. * Distance in the MAC. Otherwise, we need to force
  3475. * speed/duplex on the MAC to the current PHY speed/duplex
  3476. * settings.
  3477. */
  3478. if (hw->mac_type >= e1000_82544)
  3479. e1000_config_collision_dist(hw);
  3480. else {
  3481. ret_val = e1000_config_mac_to_phy(hw);
  3482. if (ret_val < 0) {
  3483. DEBUGOUT
  3484. ("Error configuring MAC to PHY settings\n");
  3485. return ret_val;
  3486. }
  3487. }
  3488. /* Configure Flow Control now that Auto-Neg has completed. First, we
  3489. * need to restore the desired flow control settings because we may
  3490. * have had to re-autoneg with a different link partner.
  3491. */
  3492. ret_val = e1000_config_fc_after_link_up(hw);
  3493. if (ret_val < 0) {
  3494. DEBUGOUT("Error configuring flow control\n");
  3495. return ret_val;
  3496. }
  3497. /* At this point we know that we are on copper and we have
  3498. * auto-negotiated link. These are conditions for checking the link
  3499. * parter capability register. We use the link partner capability to
  3500. * determine if TBI Compatibility needs to be turned on or off. If
  3501. * the link partner advertises any speed in addition to Gigabit, then
  3502. * we assume that they are GMII-based, and TBI compatibility is not
  3503. * needed. If no other speeds are advertised, we assume the link
  3504. * partner is TBI-based, and we turn on TBI Compatibility.
  3505. */
  3506. if (hw->tbi_compatibility_en) {
  3507. if (e1000_read_phy_reg
  3508. (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
  3509. DEBUGOUT("PHY Read Error\n");
  3510. return -E1000_ERR_PHY;
  3511. }
  3512. if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
  3513. NWAY_LPAR_10T_FD_CAPS |
  3514. NWAY_LPAR_100TX_HD_CAPS |
  3515. NWAY_LPAR_100TX_FD_CAPS |
  3516. NWAY_LPAR_100T4_CAPS)) {
  3517. /* If our link partner advertises anything in addition to
  3518. * gigabit, we do not need to enable TBI compatibility.
  3519. */
  3520. if (hw->tbi_compatibility_on) {
  3521. /* If we previously were in the mode, turn it off. */
  3522. rctl = E1000_READ_REG(hw, RCTL);
  3523. rctl &= ~E1000_RCTL_SBP;
  3524. E1000_WRITE_REG(hw, RCTL, rctl);
  3525. hw->tbi_compatibility_on = false;
  3526. }
  3527. } else {
  3528. /* If TBI compatibility is was previously off, turn it on. For
  3529. * compatibility with a TBI link partner, we will store bad
  3530. * packets. Some frames have an additional byte on the end and
  3531. * will look like CRC errors to to the hardware.
  3532. */
  3533. if (!hw->tbi_compatibility_on) {
  3534. hw->tbi_compatibility_on = true;
  3535. rctl = E1000_READ_REG(hw, RCTL);
  3536. rctl |= E1000_RCTL_SBP;
  3537. E1000_WRITE_REG(hw, RCTL, rctl);
  3538. }
  3539. }
  3540. }
  3541. }
  3542. /* If we don't have link (auto-negotiation failed or link partner cannot
  3543. * auto-negotiate), the cable is plugged in (we have signal), and our
  3544. * link partner is not trying to auto-negotiate with us (we are receiving
  3545. * idles or data), we need to force link up. We also need to give
  3546. * auto-negotiation time to complete, in case the cable was just plugged
  3547. * in. The autoneg_failed flag does this.
  3548. */
  3549. else if ((hw->media_type == e1000_media_type_fiber) &&
  3550. (!(status & E1000_STATUS_LU)) &&
  3551. ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
  3552. (!(rxcw & E1000_RXCW_C))) {
  3553. if (hw->autoneg_failed == 0) {
  3554. hw->autoneg_failed = 1;
  3555. return 0;
  3556. }
  3557. DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
  3558. /* Disable auto-negotiation in the TXCW register */
  3559. E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
  3560. /* Force link-up and also force full-duplex. */
  3561. ctrl = E1000_READ_REG(hw, CTRL);
  3562. ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
  3563. E1000_WRITE_REG(hw, CTRL, ctrl);
  3564. /* Configure Flow Control after forcing link up. */
  3565. ret_val = e1000_config_fc_after_link_up(hw);
  3566. if (ret_val < 0) {
  3567. DEBUGOUT("Error configuring flow control\n");
  3568. return ret_val;
  3569. }
  3570. }
  3571. /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
  3572. * auto-negotiation in the TXCW register and disable forced link in the
  3573. * Device Control register in an attempt to auto-negotiate with our link
  3574. * partner.
  3575. */
  3576. else if ((hw->media_type == e1000_media_type_fiber) &&
  3577. (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
  3578. DEBUGOUT
  3579. ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
  3580. E1000_WRITE_REG(hw, TXCW, hw->txcw);
  3581. E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  3582. }
  3583. return 0;
  3584. }
  3585. /******************************************************************************
  3586. * Configure the MAC-to-PHY interface for 10/100Mbps
  3587. *
  3588. * hw - Struct containing variables accessed by shared code
  3589. ******************************************************************************/
  3590. static int32_t
  3591. e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
  3592. {
  3593. int32_t ret_val = E1000_SUCCESS;
  3594. uint32_t tipg;
  3595. uint16_t reg_data;
  3596. DEBUGFUNC();
  3597. reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
  3598. ret_val = e1000_write_kmrn_reg(hw,
  3599. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3600. if (ret_val)
  3601. return ret_val;
  3602. /* Configure Transmit Inter-Packet Gap */
  3603. tipg = E1000_READ_REG(hw, TIPG);
  3604. tipg &= ~E1000_TIPG_IPGT_MASK;
  3605. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
  3606. E1000_WRITE_REG(hw, TIPG, tipg);
  3607. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3608. if (ret_val)
  3609. return ret_val;
  3610. if (duplex == HALF_DUPLEX)
  3611. reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
  3612. else
  3613. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3614. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3615. return ret_val;
  3616. }
  3617. static int32_t
  3618. e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
  3619. {
  3620. int32_t ret_val = E1000_SUCCESS;
  3621. uint16_t reg_data;
  3622. uint32_t tipg;
  3623. DEBUGFUNC();
  3624. reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
  3625. ret_val = e1000_write_kmrn_reg(hw,
  3626. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3627. if (ret_val)
  3628. return ret_val;
  3629. /* Configure Transmit Inter-Packet Gap */
  3630. tipg = E1000_READ_REG(hw, TIPG);
  3631. tipg &= ~E1000_TIPG_IPGT_MASK;
  3632. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  3633. E1000_WRITE_REG(hw, TIPG, tipg);
  3634. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3635. if (ret_val)
  3636. return ret_val;
  3637. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3638. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3639. return ret_val;
  3640. }
  3641. /******************************************************************************
  3642. * Detects the current speed and duplex settings of the hardware.
  3643. *
  3644. * hw - Struct containing variables accessed by shared code
  3645. * speed - Speed of the connection
  3646. * duplex - Duplex setting of the connection
  3647. *****************************************************************************/
  3648. static int
  3649. e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
  3650. uint16_t *duplex)
  3651. {
  3652. uint32_t status;
  3653. int32_t ret_val;
  3654. uint16_t phy_data;
  3655. DEBUGFUNC();
  3656. if (hw->mac_type >= e1000_82543) {
  3657. status = E1000_READ_REG(hw, STATUS);
  3658. if (status & E1000_STATUS_SPEED_1000) {
  3659. *speed = SPEED_1000;
  3660. DEBUGOUT("1000 Mbs, ");
  3661. } else if (status & E1000_STATUS_SPEED_100) {
  3662. *speed = SPEED_100;
  3663. DEBUGOUT("100 Mbs, ");
  3664. } else {
  3665. *speed = SPEED_10;
  3666. DEBUGOUT("10 Mbs, ");
  3667. }
  3668. if (status & E1000_STATUS_FD) {
  3669. *duplex = FULL_DUPLEX;
  3670. DEBUGOUT("Full Duplex\r\n");
  3671. } else {
  3672. *duplex = HALF_DUPLEX;
  3673. DEBUGOUT(" Half Duplex\r\n");
  3674. }
  3675. } else {
  3676. DEBUGOUT("1000 Mbs, Full Duplex\r\n");
  3677. *speed = SPEED_1000;
  3678. *duplex = FULL_DUPLEX;
  3679. }
  3680. /* IGP01 PHY may advertise full duplex operation after speed downgrade
  3681. * even if it is operating at half duplex. Here we set the duplex
  3682. * settings to match the duplex in the link partner's capabilities.
  3683. */
  3684. if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
  3685. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
  3686. if (ret_val)
  3687. return ret_val;
  3688. if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
  3689. *duplex = HALF_DUPLEX;
  3690. else {
  3691. ret_val = e1000_read_phy_reg(hw,
  3692. PHY_LP_ABILITY, &phy_data);
  3693. if (ret_val)
  3694. return ret_val;
  3695. if ((*speed == SPEED_100 &&
  3696. !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
  3697. || (*speed == SPEED_10
  3698. && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
  3699. *duplex = HALF_DUPLEX;
  3700. }
  3701. }
  3702. if ((hw->mac_type == e1000_80003es2lan) &&
  3703. (hw->media_type == e1000_media_type_copper)) {
  3704. if (*speed == SPEED_1000)
  3705. ret_val = e1000_configure_kmrn_for_1000(hw);
  3706. else
  3707. ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
  3708. if (ret_val)
  3709. return ret_val;
  3710. }
  3711. return E1000_SUCCESS;
  3712. }
  3713. /******************************************************************************
  3714. * Blocks until autoneg completes or times out (~4.5 seconds)
  3715. *
  3716. * hw - Struct containing variables accessed by shared code
  3717. ******************************************************************************/
  3718. static int
  3719. e1000_wait_autoneg(struct e1000_hw *hw)
  3720. {
  3721. uint16_t i;
  3722. uint16_t phy_data;
  3723. DEBUGFUNC();
  3724. DEBUGOUT("Waiting for Auto-Neg to complete.\n");
  3725. /* We will wait for autoneg to complete or timeout to expire. */
  3726. for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
  3727. /* Read the MII Status Register and wait for Auto-Neg
  3728. * Complete bit to be set.
  3729. */
  3730. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3731. DEBUGOUT("PHY Read Error\n");
  3732. return -E1000_ERR_PHY;
  3733. }
  3734. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3735. DEBUGOUT("PHY Read Error\n");
  3736. return -E1000_ERR_PHY;
  3737. }
  3738. if (phy_data & MII_SR_AUTONEG_COMPLETE) {
  3739. DEBUGOUT("Auto-Neg complete.\n");
  3740. return 0;
  3741. }
  3742. mdelay(100);
  3743. }
  3744. DEBUGOUT("Auto-Neg timedout.\n");
  3745. return -E1000_ERR_TIMEOUT;
  3746. }
  3747. /******************************************************************************
  3748. * Raises the Management Data Clock
  3749. *
  3750. * hw - Struct containing variables accessed by shared code
  3751. * ctrl - Device control register's current value
  3752. ******************************************************************************/
  3753. static void
  3754. e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3755. {
  3756. /* Raise the clock input to the Management Data Clock (by setting the MDC
  3757. * bit), and then delay 2 microseconds.
  3758. */
  3759. E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  3760. E1000_WRITE_FLUSH(hw);
  3761. udelay(2);
  3762. }
  3763. /******************************************************************************
  3764. * Lowers the Management Data Clock
  3765. *
  3766. * hw - Struct containing variables accessed by shared code
  3767. * ctrl - Device control register's current value
  3768. ******************************************************************************/
  3769. static void
  3770. e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3771. {
  3772. /* Lower the clock input to the Management Data Clock (by clearing the MDC
  3773. * bit), and then delay 2 microseconds.
  3774. */
  3775. E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  3776. E1000_WRITE_FLUSH(hw);
  3777. udelay(2);
  3778. }
  3779. /******************************************************************************
  3780. * Shifts data bits out to the PHY
  3781. *
  3782. * hw - Struct containing variables accessed by shared code
  3783. * data - Data to send out to the PHY
  3784. * count - Number of bits to shift out
  3785. *
  3786. * Bits are shifted out in MSB to LSB order.
  3787. ******************************************************************************/
  3788. static void
  3789. e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
  3790. {
  3791. uint32_t ctrl;
  3792. uint32_t mask;
  3793. /* We need to shift "count" number of bits out to the PHY. So, the value
  3794. * in the "data" parameter will be shifted out to the PHY one bit at a
  3795. * time. In order to do this, "data" must be broken down into bits.
  3796. */
  3797. mask = 0x01;
  3798. mask <<= (count - 1);
  3799. ctrl = E1000_READ_REG(hw, CTRL);
  3800. /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
  3801. ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
  3802. while (mask) {
  3803. /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
  3804. * then raising and lowering the Management Data Clock. A "0" is
  3805. * shifted out to the PHY by setting the MDIO bit to "0" and then
  3806. * raising and lowering the clock.
  3807. */
  3808. if (data & mask)
  3809. ctrl |= E1000_CTRL_MDIO;
  3810. else
  3811. ctrl &= ~E1000_CTRL_MDIO;
  3812. E1000_WRITE_REG(hw, CTRL, ctrl);
  3813. E1000_WRITE_FLUSH(hw);
  3814. udelay(2);
  3815. e1000_raise_mdi_clk(hw, &ctrl);
  3816. e1000_lower_mdi_clk(hw, &ctrl);
  3817. mask = mask >> 1;
  3818. }
  3819. }
  3820. /******************************************************************************
  3821. * Shifts data bits in from the PHY
  3822. *
  3823. * hw - Struct containing variables accessed by shared code
  3824. *
  3825. * Bits are shifted in in MSB to LSB order.
  3826. ******************************************************************************/
  3827. static uint16_t
  3828. e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  3829. {
  3830. uint32_t ctrl;
  3831. uint16_t data = 0;
  3832. uint8_t i;
  3833. /* In order to read a register from the PHY, we need to shift in a total
  3834. * of 18 bits from the PHY. The first two bit (turnaround) times are used
  3835. * to avoid contention on the MDIO pin when a read operation is performed.
  3836. * These two bits are ignored by us and thrown away. Bits are "shifted in"
  3837. * by raising the input to the Management Data Clock (setting the MDC bit),
  3838. * and then reading the value of the MDIO bit.
  3839. */
  3840. ctrl = E1000_READ_REG(hw, CTRL);
  3841. /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  3842. ctrl &= ~E1000_CTRL_MDIO_DIR;
  3843. ctrl &= ~E1000_CTRL_MDIO;
  3844. E1000_WRITE_REG(hw, CTRL, ctrl);
  3845. E1000_WRITE_FLUSH(hw);
  3846. /* Raise and Lower the clock before reading in the data. This accounts for
  3847. * the turnaround bits. The first clock occurred when we clocked out the
  3848. * last bit of the Register Address.
  3849. */
  3850. e1000_raise_mdi_clk(hw, &ctrl);
  3851. e1000_lower_mdi_clk(hw, &ctrl);
  3852. for (data = 0, i = 0; i < 16; i++) {
  3853. data = data << 1;
  3854. e1000_raise_mdi_clk(hw, &ctrl);
  3855. ctrl = E1000_READ_REG(hw, CTRL);
  3856. /* Check to see if we shifted in a "1". */
  3857. if (ctrl & E1000_CTRL_MDIO)
  3858. data |= 1;
  3859. e1000_lower_mdi_clk(hw, &ctrl);
  3860. }
  3861. e1000_raise_mdi_clk(hw, &ctrl);
  3862. e1000_lower_mdi_clk(hw, &ctrl);
  3863. return data;
  3864. }
  3865. /*****************************************************************************
  3866. * Reads the value from a PHY register
  3867. *
  3868. * hw - Struct containing variables accessed by shared code
  3869. * reg_addr - address of the PHY register to read
  3870. ******************************************************************************/
  3871. static int
  3872. e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
  3873. {
  3874. uint32_t i;
  3875. uint32_t mdic = 0;
  3876. const uint32_t phy_addr = 1;
  3877. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3878. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3879. return -E1000_ERR_PARAM;
  3880. }
  3881. if (hw->mac_type > e1000_82543) {
  3882. /* Set up Op-code, Phy Address, and register address in the MDI
  3883. * Control register. The MAC will take care of interfacing with the
  3884. * PHY to retrieve the desired data.
  3885. */
  3886. mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  3887. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3888. (E1000_MDIC_OP_READ));
  3889. E1000_WRITE_REG(hw, MDIC, mdic);
  3890. /* Poll the ready bit to see if the MDI read completed */
  3891. for (i = 0; i < 64; i++) {
  3892. udelay(10);
  3893. mdic = E1000_READ_REG(hw, MDIC);
  3894. if (mdic & E1000_MDIC_READY)
  3895. break;
  3896. }
  3897. if (!(mdic & E1000_MDIC_READY)) {
  3898. DEBUGOUT("MDI Read did not complete\n");
  3899. return -E1000_ERR_PHY;
  3900. }
  3901. if (mdic & E1000_MDIC_ERROR) {
  3902. DEBUGOUT("MDI Error\n");
  3903. return -E1000_ERR_PHY;
  3904. }
  3905. *phy_data = (uint16_t) mdic;
  3906. } else {
  3907. /* We must first send a preamble through the MDIO pin to signal the
  3908. * beginning of an MII instruction. This is done by sending 32
  3909. * consecutive "1" bits.
  3910. */
  3911. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3912. /* Now combine the next few fields that are required for a read
  3913. * operation. We use this method instead of calling the
  3914. * e1000_shift_out_mdi_bits routine five different times. The format of
  3915. * a MII read instruction consists of a shift out of 14 bits and is
  3916. * defined as follows:
  3917. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
  3918. * followed by a shift in of 18 bits. This first two bits shifted in
  3919. * are TurnAround bits used to avoid contention on the MDIO pin when a
  3920. * READ operation is performed. These two bits are thrown away
  3921. * followed by a shift in of 16 bits which contains the desired data.
  3922. */
  3923. mdic = ((reg_addr) | (phy_addr << 5) |
  3924. (PHY_OP_READ << 10) | (PHY_SOF << 12));
  3925. e1000_shift_out_mdi_bits(hw, mdic, 14);
  3926. /* Now that we've shifted out the read command to the MII, we need to
  3927. * "shift in" the 16-bit value (18 total bits) of the requested PHY
  3928. * register address.
  3929. */
  3930. *phy_data = e1000_shift_in_mdi_bits(hw);
  3931. }
  3932. return 0;
  3933. }
  3934. /******************************************************************************
  3935. * Writes a value to a PHY register
  3936. *
  3937. * hw - Struct containing variables accessed by shared code
  3938. * reg_addr - address of the PHY register to write
  3939. * data - data to write to the PHY
  3940. ******************************************************************************/
  3941. static int
  3942. e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
  3943. {
  3944. uint32_t i;
  3945. uint32_t mdic = 0;
  3946. const uint32_t phy_addr = 1;
  3947. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3948. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3949. return -E1000_ERR_PARAM;
  3950. }
  3951. if (hw->mac_type > e1000_82543) {
  3952. /* Set up Op-code, Phy Address, register address, and data intended
  3953. * for the PHY register in the MDI Control register. The MAC will take
  3954. * care of interfacing with the PHY to send the desired data.
  3955. */
  3956. mdic = (((uint32_t) phy_data) |
  3957. (reg_addr << E1000_MDIC_REG_SHIFT) |
  3958. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3959. (E1000_MDIC_OP_WRITE));
  3960. E1000_WRITE_REG(hw, MDIC, mdic);
  3961. /* Poll the ready bit to see if the MDI read completed */
  3962. for (i = 0; i < 64; i++) {
  3963. udelay(10);
  3964. mdic = E1000_READ_REG(hw, MDIC);
  3965. if (mdic & E1000_MDIC_READY)
  3966. break;
  3967. }
  3968. if (!(mdic & E1000_MDIC_READY)) {
  3969. DEBUGOUT("MDI Write did not complete\n");
  3970. return -E1000_ERR_PHY;
  3971. }
  3972. } else {
  3973. /* We'll need to use the SW defined pins to shift the write command
  3974. * out to the PHY. We first send a preamble to the PHY to signal the
  3975. * beginning of the MII instruction. This is done by sending 32
  3976. * consecutive "1" bits.
  3977. */
  3978. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3979. /* Now combine the remaining required fields that will indicate a
  3980. * write operation. We use this method instead of calling the
  3981. * e1000_shift_out_mdi_bits routine for each field in the command. The
  3982. * format of a MII write instruction is as follows:
  3983. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
  3984. */
  3985. mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
  3986. (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
  3987. mdic <<= 16;
  3988. mdic |= (uint32_t) phy_data;
  3989. e1000_shift_out_mdi_bits(hw, mdic, 32);
  3990. }
  3991. return 0;
  3992. }
  3993. /******************************************************************************
  3994. * Checks if PHY reset is blocked due to SOL/IDER session, for example.
  3995. * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
  3996. * the caller to figure out how to deal with it.
  3997. *
  3998. * hw - Struct containing variables accessed by shared code
  3999. *
  4000. * returns: - E1000_BLK_PHY_RESET
  4001. * E1000_SUCCESS
  4002. *
  4003. *****************************************************************************/
  4004. int32_t
  4005. e1000_check_phy_reset_block(struct e1000_hw *hw)
  4006. {
  4007. uint32_t manc = 0;
  4008. uint32_t fwsm = 0;
  4009. if (hw->mac_type == e1000_ich8lan) {
  4010. fwsm = E1000_READ_REG(hw, FWSM);
  4011. return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
  4012. : E1000_BLK_PHY_RESET;
  4013. }
  4014. if (hw->mac_type > e1000_82547_rev_2)
  4015. manc = E1000_READ_REG(hw, MANC);
  4016. return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
  4017. E1000_BLK_PHY_RESET : E1000_SUCCESS;
  4018. }
  4019. /***************************************************************************
  4020. * Checks if the PHY configuration is done
  4021. *
  4022. * hw: Struct containing variables accessed by shared code
  4023. *
  4024. * returns: - E1000_ERR_RESET if fail to reset MAC
  4025. * E1000_SUCCESS at any other case.
  4026. *
  4027. ***************************************************************************/
  4028. static int32_t
  4029. e1000_get_phy_cfg_done(struct e1000_hw *hw)
  4030. {
  4031. int32_t timeout = PHY_CFG_TIMEOUT;
  4032. uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
  4033. DEBUGFUNC();
  4034. switch (hw->mac_type) {
  4035. default:
  4036. mdelay(10);
  4037. break;
  4038. case e1000_80003es2lan:
  4039. /* Separate *_CFG_DONE_* bit for each port */
  4040. if (e1000_is_second_port(hw))
  4041. cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
  4042. /* Fall Through */
  4043. case e1000_82571:
  4044. case e1000_82572:
  4045. case e1000_igb:
  4046. while (timeout) {
  4047. if (hw->mac_type == e1000_igb) {
  4048. if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
  4049. break;
  4050. } else {
  4051. if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
  4052. break;
  4053. }
  4054. mdelay(1);
  4055. timeout--;
  4056. }
  4057. if (!timeout) {
  4058. DEBUGOUT("MNG configuration cycle has not "
  4059. "completed.\n");
  4060. return -E1000_ERR_RESET;
  4061. }
  4062. break;
  4063. }
  4064. return E1000_SUCCESS;
  4065. }
  4066. /******************************************************************************
  4067. * Returns the PHY to the power-on reset state
  4068. *
  4069. * hw - Struct containing variables accessed by shared code
  4070. ******************************************************************************/
  4071. int32_t
  4072. e1000_phy_hw_reset(struct e1000_hw *hw)
  4073. {
  4074. uint16_t swfw = E1000_SWFW_PHY0_SM;
  4075. uint32_t ctrl, ctrl_ext;
  4076. uint32_t led_ctrl;
  4077. int32_t ret_val;
  4078. DEBUGFUNC();
  4079. /* In the case of the phy reset being blocked, it's not an error, we
  4080. * simply return success without performing the reset. */
  4081. ret_val = e1000_check_phy_reset_block(hw);
  4082. if (ret_val)
  4083. return E1000_SUCCESS;
  4084. DEBUGOUT("Resetting Phy...\n");
  4085. if (hw->mac_type > e1000_82543) {
  4086. if (e1000_is_second_port(hw))
  4087. swfw = E1000_SWFW_PHY1_SM;
  4088. if (e1000_swfw_sync_acquire(hw, swfw)) {
  4089. DEBUGOUT("Unable to acquire swfw sync\n");
  4090. return -E1000_ERR_SWFW_SYNC;
  4091. }
  4092. /* Read the device control register and assert the E1000_CTRL_PHY_RST
  4093. * bit. Then, take it out of reset.
  4094. */
  4095. ctrl = E1000_READ_REG(hw, CTRL);
  4096. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
  4097. E1000_WRITE_FLUSH(hw);
  4098. if (hw->mac_type < e1000_82571)
  4099. udelay(10);
  4100. else
  4101. udelay(100);
  4102. E1000_WRITE_REG(hw, CTRL, ctrl);
  4103. E1000_WRITE_FLUSH(hw);
  4104. if (hw->mac_type >= e1000_82571)
  4105. mdelay(10);
  4106. } else {
  4107. /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
  4108. * bit to put the PHY into reset. Then, take it out of reset.
  4109. */
  4110. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4111. ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
  4112. ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
  4113. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4114. E1000_WRITE_FLUSH(hw);
  4115. mdelay(10);
  4116. ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
  4117. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4118. E1000_WRITE_FLUSH(hw);
  4119. }
  4120. udelay(150);
  4121. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  4122. /* Configure activity LED after PHY reset */
  4123. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  4124. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  4125. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  4126. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  4127. }
  4128. e1000_swfw_sync_release(hw, swfw);
  4129. /* Wait for FW to finish PHY configuration. */
  4130. ret_val = e1000_get_phy_cfg_done(hw);
  4131. if (ret_val != E1000_SUCCESS)
  4132. return ret_val;
  4133. return ret_val;
  4134. }
  4135. /******************************************************************************
  4136. * IGP phy init script - initializes the GbE PHY
  4137. *
  4138. * hw - Struct containing variables accessed by shared code
  4139. *****************************************************************************/
  4140. static void
  4141. e1000_phy_init_script(struct e1000_hw *hw)
  4142. {
  4143. uint32_t ret_val;
  4144. uint16_t phy_saved_data;
  4145. DEBUGFUNC();
  4146. if (hw->phy_init_script) {
  4147. mdelay(20);
  4148. /* Save off the current value of register 0x2F5B to be
  4149. * restored at the end of this routine. */
  4150. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  4151. /* Disabled the PHY transmitter */
  4152. e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  4153. mdelay(20);
  4154. e1000_write_phy_reg(hw, 0x0000, 0x0140);
  4155. mdelay(5);
  4156. switch (hw->mac_type) {
  4157. case e1000_82541:
  4158. case e1000_82547:
  4159. e1000_write_phy_reg(hw, 0x1F95, 0x0001);
  4160. e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
  4161. e1000_write_phy_reg(hw, 0x1F79, 0x0018);
  4162. e1000_write_phy_reg(hw, 0x1F30, 0x1600);
  4163. e1000_write_phy_reg(hw, 0x1F31, 0x0014);
  4164. e1000_write_phy_reg(hw, 0x1F32, 0x161C);
  4165. e1000_write_phy_reg(hw, 0x1F94, 0x0003);
  4166. e1000_write_phy_reg(hw, 0x1F96, 0x003F);
  4167. e1000_write_phy_reg(hw, 0x2010, 0x0008);
  4168. break;
  4169. case e1000_82541_rev_2:
  4170. case e1000_82547_rev_2:
  4171. e1000_write_phy_reg(hw, 0x1F73, 0x0099);
  4172. break;
  4173. default:
  4174. break;
  4175. }
  4176. e1000_write_phy_reg(hw, 0x0000, 0x3300);
  4177. mdelay(20);
  4178. /* Now enable the transmitter */
  4179. if (!ret_val)
  4180. e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  4181. if (hw->mac_type == e1000_82547) {
  4182. uint16_t fused, fine, coarse;
  4183. /* Move to analog registers page */
  4184. e1000_read_phy_reg(hw,
  4185. IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
  4186. if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
  4187. e1000_read_phy_reg(hw,
  4188. IGP01E1000_ANALOG_FUSE_STATUS, &fused);
  4189. fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
  4190. coarse = fused
  4191. & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
  4192. if (coarse >
  4193. IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
  4194. coarse -=
  4195. IGP01E1000_ANALOG_FUSE_COARSE_10;
  4196. fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
  4197. } else if (coarse
  4198. == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
  4199. fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
  4200. fused = (fused
  4201. & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
  4202. (fine
  4203. & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
  4204. (coarse
  4205. & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
  4206. e1000_write_phy_reg(hw,
  4207. IGP01E1000_ANALOG_FUSE_CONTROL, fused);
  4208. e1000_write_phy_reg(hw,
  4209. IGP01E1000_ANALOG_FUSE_BYPASS,
  4210. IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
  4211. }
  4212. }
  4213. }
  4214. }
  4215. /******************************************************************************
  4216. * Resets the PHY
  4217. *
  4218. * hw - Struct containing variables accessed by shared code
  4219. *
  4220. * Sets bit 15 of the MII Control register
  4221. ******************************************************************************/
  4222. int32_t
  4223. e1000_phy_reset(struct e1000_hw *hw)
  4224. {
  4225. int32_t ret_val;
  4226. uint16_t phy_data;
  4227. DEBUGFUNC();
  4228. /* In the case of the phy reset being blocked, it's not an error, we
  4229. * simply return success without performing the reset. */
  4230. ret_val = e1000_check_phy_reset_block(hw);
  4231. if (ret_val)
  4232. return E1000_SUCCESS;
  4233. switch (hw->phy_type) {
  4234. case e1000_phy_igp:
  4235. case e1000_phy_igp_2:
  4236. case e1000_phy_igp_3:
  4237. case e1000_phy_ife:
  4238. case e1000_phy_igb:
  4239. ret_val = e1000_phy_hw_reset(hw);
  4240. if (ret_val)
  4241. return ret_val;
  4242. break;
  4243. default:
  4244. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  4245. if (ret_val)
  4246. return ret_val;
  4247. phy_data |= MII_CR_RESET;
  4248. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  4249. if (ret_val)
  4250. return ret_val;
  4251. udelay(1);
  4252. break;
  4253. }
  4254. if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
  4255. e1000_phy_init_script(hw);
  4256. return E1000_SUCCESS;
  4257. }
  4258. static int e1000_set_phy_type (struct e1000_hw *hw)
  4259. {
  4260. DEBUGFUNC ();
  4261. if (hw->mac_type == e1000_undefined)
  4262. return -E1000_ERR_PHY_TYPE;
  4263. switch (hw->phy_id) {
  4264. case M88E1000_E_PHY_ID:
  4265. case M88E1000_I_PHY_ID:
  4266. case M88E1011_I_PHY_ID:
  4267. case M88E1111_I_PHY_ID:
  4268. hw->phy_type = e1000_phy_m88;
  4269. break;
  4270. case IGP01E1000_I_PHY_ID:
  4271. if (hw->mac_type == e1000_82541 ||
  4272. hw->mac_type == e1000_82541_rev_2 ||
  4273. hw->mac_type == e1000_82547 ||
  4274. hw->mac_type == e1000_82547_rev_2) {
  4275. hw->phy_type = e1000_phy_igp;
  4276. break;
  4277. }
  4278. case IGP03E1000_E_PHY_ID:
  4279. hw->phy_type = e1000_phy_igp_3;
  4280. break;
  4281. case IFE_E_PHY_ID:
  4282. case IFE_PLUS_E_PHY_ID:
  4283. case IFE_C_E_PHY_ID:
  4284. hw->phy_type = e1000_phy_ife;
  4285. break;
  4286. case GG82563_E_PHY_ID:
  4287. if (hw->mac_type == e1000_80003es2lan) {
  4288. hw->phy_type = e1000_phy_gg82563;
  4289. break;
  4290. }
  4291. case BME1000_E_PHY_ID:
  4292. hw->phy_type = e1000_phy_bm;
  4293. break;
  4294. case I210_I_PHY_ID:
  4295. hw->phy_type = e1000_phy_igb;
  4296. break;
  4297. /* Fall Through */
  4298. default:
  4299. /* Should never have loaded on this device */
  4300. hw->phy_type = e1000_phy_undefined;
  4301. return -E1000_ERR_PHY_TYPE;
  4302. }
  4303. return E1000_SUCCESS;
  4304. }
  4305. /******************************************************************************
  4306. * Probes the expected PHY address for known PHY IDs
  4307. *
  4308. * hw - Struct containing variables accessed by shared code
  4309. ******************************************************************************/
  4310. static int32_t
  4311. e1000_detect_gig_phy(struct e1000_hw *hw)
  4312. {
  4313. int32_t phy_init_status, ret_val;
  4314. uint16_t phy_id_high, phy_id_low;
  4315. bool match = false;
  4316. DEBUGFUNC();
  4317. /* The 82571 firmware may still be configuring the PHY. In this
  4318. * case, we cannot access the PHY until the configuration is done. So
  4319. * we explicitly set the PHY values. */
  4320. if (hw->mac_type == e1000_82571 ||
  4321. hw->mac_type == e1000_82572) {
  4322. hw->phy_id = IGP01E1000_I_PHY_ID;
  4323. hw->phy_type = e1000_phy_igp_2;
  4324. return E1000_SUCCESS;
  4325. }
  4326. /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
  4327. * work- around that forces PHY page 0 to be set or the reads fail.
  4328. * The rest of the code in this routine uses e1000_read_phy_reg to
  4329. * read the PHY ID. So for ESB-2 we need to have this set so our
  4330. * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
  4331. * the routines below will figure this out as well. */
  4332. if (hw->mac_type == e1000_80003es2lan)
  4333. hw->phy_type = e1000_phy_gg82563;
  4334. /* Read the PHY ID Registers to identify which PHY is onboard. */
  4335. ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
  4336. if (ret_val)
  4337. return ret_val;
  4338. hw->phy_id = (uint32_t) (phy_id_high << 16);
  4339. udelay(20);
  4340. ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
  4341. if (ret_val)
  4342. return ret_val;
  4343. hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  4344. hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  4345. switch (hw->mac_type) {
  4346. case e1000_82543:
  4347. if (hw->phy_id == M88E1000_E_PHY_ID)
  4348. match = true;
  4349. break;
  4350. case e1000_82544:
  4351. if (hw->phy_id == M88E1000_I_PHY_ID)
  4352. match = true;
  4353. break;
  4354. case e1000_82540:
  4355. case e1000_82545:
  4356. case e1000_82545_rev_3:
  4357. case e1000_82546:
  4358. case e1000_82546_rev_3:
  4359. if (hw->phy_id == M88E1011_I_PHY_ID)
  4360. match = true;
  4361. break;
  4362. case e1000_82541:
  4363. case e1000_82541_rev_2:
  4364. case e1000_82547:
  4365. case e1000_82547_rev_2:
  4366. if(hw->phy_id == IGP01E1000_I_PHY_ID)
  4367. match = true;
  4368. break;
  4369. case e1000_82573:
  4370. if (hw->phy_id == M88E1111_I_PHY_ID)
  4371. match = true;
  4372. break;
  4373. case e1000_82574:
  4374. if (hw->phy_id == BME1000_E_PHY_ID)
  4375. match = true;
  4376. break;
  4377. case e1000_80003es2lan:
  4378. if (hw->phy_id == GG82563_E_PHY_ID)
  4379. match = true;
  4380. break;
  4381. case e1000_ich8lan:
  4382. if (hw->phy_id == IGP03E1000_E_PHY_ID)
  4383. match = true;
  4384. if (hw->phy_id == IFE_E_PHY_ID)
  4385. match = true;
  4386. if (hw->phy_id == IFE_PLUS_E_PHY_ID)
  4387. match = true;
  4388. if (hw->phy_id == IFE_C_E_PHY_ID)
  4389. match = true;
  4390. break;
  4391. case e1000_igb:
  4392. if (hw->phy_id == I210_I_PHY_ID)
  4393. match = true;
  4394. break;
  4395. default:
  4396. DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
  4397. return -E1000_ERR_CONFIG;
  4398. }
  4399. phy_init_status = e1000_set_phy_type(hw);
  4400. if ((match) && (phy_init_status == E1000_SUCCESS)) {
  4401. DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
  4402. return 0;
  4403. }
  4404. DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
  4405. return -E1000_ERR_PHY;
  4406. }
  4407. /*****************************************************************************
  4408. * Set media type and TBI compatibility.
  4409. *
  4410. * hw - Struct containing variables accessed by shared code
  4411. * **************************************************************************/
  4412. void
  4413. e1000_set_media_type(struct e1000_hw *hw)
  4414. {
  4415. uint32_t status;
  4416. DEBUGFUNC();
  4417. if (hw->mac_type != e1000_82543) {
  4418. /* tbi_compatibility is only valid on 82543 */
  4419. hw->tbi_compatibility_en = false;
  4420. }
  4421. switch (hw->device_id) {
  4422. case E1000_DEV_ID_82545GM_SERDES:
  4423. case E1000_DEV_ID_82546GB_SERDES:
  4424. case E1000_DEV_ID_82571EB_SERDES:
  4425. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  4426. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  4427. case E1000_DEV_ID_82572EI_SERDES:
  4428. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  4429. hw->media_type = e1000_media_type_internal_serdes;
  4430. break;
  4431. default:
  4432. switch (hw->mac_type) {
  4433. case e1000_82542_rev2_0:
  4434. case e1000_82542_rev2_1:
  4435. hw->media_type = e1000_media_type_fiber;
  4436. break;
  4437. case e1000_ich8lan:
  4438. case e1000_82573:
  4439. case e1000_82574:
  4440. case e1000_igb:
  4441. /* The STATUS_TBIMODE bit is reserved or reused
  4442. * for the this device.
  4443. */
  4444. hw->media_type = e1000_media_type_copper;
  4445. break;
  4446. default:
  4447. status = E1000_READ_REG(hw, STATUS);
  4448. if (status & E1000_STATUS_TBIMODE) {
  4449. hw->media_type = e1000_media_type_fiber;
  4450. /* tbi_compatibility not valid on fiber */
  4451. hw->tbi_compatibility_en = false;
  4452. } else {
  4453. hw->media_type = e1000_media_type_copper;
  4454. }
  4455. break;
  4456. }
  4457. }
  4458. }
  4459. /**
  4460. * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  4461. *
  4462. * e1000_sw_init initializes the Adapter private data structure.
  4463. * Fields are initialized based on PCI device information and
  4464. * OS network device settings (MTU size).
  4465. **/
  4466. static int
  4467. e1000_sw_init(struct e1000_hw *hw)
  4468. {
  4469. int result;
  4470. /* PCI config space info */
  4471. #ifdef CONFIG_DM_ETH
  4472. dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4473. dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4474. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4475. &hw->subsystem_vendor_id);
  4476. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4477. dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4478. dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4479. #else
  4480. pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4481. pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4482. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4483. &hw->subsystem_vendor_id);
  4484. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4485. pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4486. pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4487. #endif
  4488. /* identify the MAC */
  4489. result = e1000_set_mac_type(hw);
  4490. if (result) {
  4491. E1000_ERR(hw, "Unknown MAC Type\n");
  4492. return result;
  4493. }
  4494. switch (hw->mac_type) {
  4495. default:
  4496. break;
  4497. case e1000_82541:
  4498. case e1000_82547:
  4499. case e1000_82541_rev_2:
  4500. case e1000_82547_rev_2:
  4501. hw->phy_init_script = 1;
  4502. break;
  4503. }
  4504. /* flow control settings */
  4505. hw->fc_high_water = E1000_FC_HIGH_THRESH;
  4506. hw->fc_low_water = E1000_FC_LOW_THRESH;
  4507. hw->fc_pause_time = E1000_FC_PAUSE_TIME;
  4508. hw->fc_send_xon = 1;
  4509. /* Media type - copper or fiber */
  4510. hw->tbi_compatibility_en = true;
  4511. e1000_set_media_type(hw);
  4512. if (hw->mac_type >= e1000_82543) {
  4513. uint32_t status = E1000_READ_REG(hw, STATUS);
  4514. if (status & E1000_STATUS_TBIMODE) {
  4515. DEBUGOUT("fiber interface\n");
  4516. hw->media_type = e1000_media_type_fiber;
  4517. } else {
  4518. DEBUGOUT("copper interface\n");
  4519. hw->media_type = e1000_media_type_copper;
  4520. }
  4521. } else {
  4522. hw->media_type = e1000_media_type_fiber;
  4523. }
  4524. hw->wait_autoneg_complete = true;
  4525. if (hw->mac_type < e1000_82543)
  4526. hw->report_tx_early = 0;
  4527. else
  4528. hw->report_tx_early = 1;
  4529. return E1000_SUCCESS;
  4530. }
  4531. void
  4532. fill_rx(struct e1000_hw *hw)
  4533. {
  4534. struct e1000_rx_desc *rd;
  4535. unsigned long flush_start, flush_end;
  4536. rx_last = rx_tail;
  4537. rd = rx_base + rx_tail;
  4538. rx_tail = (rx_tail + 1) % 8;
  4539. memset(rd, 0, 16);
  4540. rd->buffer_addr = cpu_to_le64((unsigned long)packet);
  4541. /*
  4542. * Make sure there are no stale data in WB over this area, which
  4543. * might get written into the memory while the e1000 also writes
  4544. * into the same memory area.
  4545. */
  4546. invalidate_dcache_range((unsigned long)packet,
  4547. (unsigned long)packet + 4096);
  4548. /* Dump the DMA descriptor into RAM. */
  4549. flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4550. flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4551. flush_dcache_range(flush_start, flush_end);
  4552. E1000_WRITE_REG(hw, RDT, rx_tail);
  4553. }
  4554. /**
  4555. * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  4556. * @adapter: board private structure
  4557. *
  4558. * Configure the Tx unit of the MAC after a reset.
  4559. **/
  4560. static void
  4561. e1000_configure_tx(struct e1000_hw *hw)
  4562. {
  4563. unsigned long tctl;
  4564. unsigned long tipg, tarc;
  4565. uint32_t ipgr1, ipgr2;
  4566. E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
  4567. E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
  4568. E1000_WRITE_REG(hw, TDLEN, 128);
  4569. /* Setup the HW Tx Head and Tail descriptor pointers */
  4570. E1000_WRITE_REG(hw, TDH, 0);
  4571. E1000_WRITE_REG(hw, TDT, 0);
  4572. tx_tail = 0;
  4573. /* Set the default values for the Tx Inter Packet Gap timer */
  4574. if (hw->mac_type <= e1000_82547_rev_2 &&
  4575. (hw->media_type == e1000_media_type_fiber ||
  4576. hw->media_type == e1000_media_type_internal_serdes))
  4577. tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  4578. else
  4579. tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  4580. /* Set the default values for the Tx Inter Packet Gap timer */
  4581. switch (hw->mac_type) {
  4582. case e1000_82542_rev2_0:
  4583. case e1000_82542_rev2_1:
  4584. tipg = DEFAULT_82542_TIPG_IPGT;
  4585. ipgr1 = DEFAULT_82542_TIPG_IPGR1;
  4586. ipgr2 = DEFAULT_82542_TIPG_IPGR2;
  4587. break;
  4588. case e1000_80003es2lan:
  4589. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4590. ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
  4591. break;
  4592. default:
  4593. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4594. ipgr2 = DEFAULT_82543_TIPG_IPGR2;
  4595. break;
  4596. }
  4597. tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
  4598. tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
  4599. E1000_WRITE_REG(hw, TIPG, tipg);
  4600. /* Program the Transmit Control Register */
  4601. tctl = E1000_READ_REG(hw, TCTL);
  4602. tctl &= ~E1000_TCTL_CT;
  4603. tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
  4604. (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  4605. if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
  4606. tarc = E1000_READ_REG(hw, TARC0);
  4607. /* set the speed mode bit, we'll clear it if we're not at
  4608. * gigabit link later */
  4609. /* git bit can be set to 1*/
  4610. } else if (hw->mac_type == e1000_80003es2lan) {
  4611. tarc = E1000_READ_REG(hw, TARC0);
  4612. tarc |= 1;
  4613. E1000_WRITE_REG(hw, TARC0, tarc);
  4614. tarc = E1000_READ_REG(hw, TARC1);
  4615. tarc |= 1;
  4616. E1000_WRITE_REG(hw, TARC1, tarc);
  4617. }
  4618. e1000_config_collision_dist(hw);
  4619. /* Setup Transmit Descriptor Settings for eop descriptor */
  4620. hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
  4621. /* Need to set up RS bit */
  4622. if (hw->mac_type < e1000_82543)
  4623. hw->txd_cmd |= E1000_TXD_CMD_RPS;
  4624. else
  4625. hw->txd_cmd |= E1000_TXD_CMD_RS;
  4626. if (hw->mac_type == e1000_igb) {
  4627. E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
  4628. uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  4629. reg_txdctl |= 1 << 25;
  4630. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  4631. mdelay(20);
  4632. }
  4633. E1000_WRITE_REG(hw, TCTL, tctl);
  4634. }
  4635. /**
  4636. * e1000_setup_rctl - configure the receive control register
  4637. * @adapter: Board private structure
  4638. **/
  4639. static void
  4640. e1000_setup_rctl(struct e1000_hw *hw)
  4641. {
  4642. uint32_t rctl;
  4643. rctl = E1000_READ_REG(hw, RCTL);
  4644. rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  4645. rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
  4646. | E1000_RCTL_RDMTS_HALF; /* |
  4647. (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
  4648. if (hw->tbi_compatibility_on == 1)
  4649. rctl |= E1000_RCTL_SBP;
  4650. else
  4651. rctl &= ~E1000_RCTL_SBP;
  4652. rctl &= ~(E1000_RCTL_SZ_4096);
  4653. rctl |= E1000_RCTL_SZ_2048;
  4654. rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
  4655. E1000_WRITE_REG(hw, RCTL, rctl);
  4656. }
  4657. /**
  4658. * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  4659. * @adapter: board private structure
  4660. *
  4661. * Configure the Rx unit of the MAC after a reset.
  4662. **/
  4663. static void
  4664. e1000_configure_rx(struct e1000_hw *hw)
  4665. {
  4666. unsigned long rctl, ctrl_ext;
  4667. rx_tail = 0;
  4668. /* make sure receives are disabled while setting up the descriptors */
  4669. rctl = E1000_READ_REG(hw, RCTL);
  4670. E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
  4671. if (hw->mac_type >= e1000_82540) {
  4672. /* Set the interrupt throttling rate. Value is calculated
  4673. * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
  4674. #define MAX_INTS_PER_SEC 8000
  4675. #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
  4676. E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
  4677. }
  4678. if (hw->mac_type >= e1000_82571) {
  4679. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4680. /* Reset delay timers after every interrupt */
  4681. ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
  4682. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4683. E1000_WRITE_FLUSH(hw);
  4684. }
  4685. /* Setup the Base and Length of the Rx Descriptor Ring */
  4686. E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
  4687. E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
  4688. E1000_WRITE_REG(hw, RDLEN, 128);
  4689. /* Setup the HW Rx Head and Tail Descriptor Pointers */
  4690. E1000_WRITE_REG(hw, RDH, 0);
  4691. E1000_WRITE_REG(hw, RDT, 0);
  4692. /* Enable Receives */
  4693. if (hw->mac_type == e1000_igb) {
  4694. uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
  4695. reg_rxdctl |= 1 << 25;
  4696. E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
  4697. mdelay(20);
  4698. }
  4699. E1000_WRITE_REG(hw, RCTL, rctl);
  4700. fill_rx(hw);
  4701. }
  4702. /**************************************************************************
  4703. POLL - Wait for a frame
  4704. ***************************************************************************/
  4705. static int
  4706. _e1000_poll(struct e1000_hw *hw)
  4707. {
  4708. struct e1000_rx_desc *rd;
  4709. unsigned long inval_start, inval_end;
  4710. uint32_t len;
  4711. /* return true if there's an ethernet packet ready to read */
  4712. rd = rx_base + rx_last;
  4713. /* Re-load the descriptor from RAM. */
  4714. inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4715. inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4716. invalidate_dcache_range(inval_start, inval_end);
  4717. if (!(rd->status & E1000_RXD_STAT_DD))
  4718. return 0;
  4719. /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
  4720. /* Packet received, make sure the data are re-loaded from RAM. */
  4721. len = le16_to_cpu(rd->length);
  4722. invalidate_dcache_range((unsigned long)packet,
  4723. (unsigned long)packet +
  4724. roundup(len, ARCH_DMA_MINALIGN));
  4725. return len;
  4726. }
  4727. static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
  4728. {
  4729. void *nv_packet = (void *)txpacket;
  4730. struct e1000_tx_desc *txp;
  4731. int i = 0;
  4732. unsigned long flush_start, flush_end;
  4733. txp = tx_base + tx_tail;
  4734. tx_tail = (tx_tail + 1) % 8;
  4735. txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
  4736. txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
  4737. txp->upper.data = 0;
  4738. /* Dump the packet into RAM so e1000 can pick them. */
  4739. flush_dcache_range((unsigned long)nv_packet,
  4740. (unsigned long)nv_packet +
  4741. roundup(length, ARCH_DMA_MINALIGN));
  4742. /* Dump the descriptor into RAM as well. */
  4743. flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
  4744. flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
  4745. flush_dcache_range(flush_start, flush_end);
  4746. E1000_WRITE_REG(hw, TDT, tx_tail);
  4747. E1000_WRITE_FLUSH(hw);
  4748. while (1) {
  4749. invalidate_dcache_range(flush_start, flush_end);
  4750. if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
  4751. break;
  4752. if (i++ > TOUT_LOOP) {
  4753. DEBUGOUT("e1000: tx timeout\n");
  4754. return 0;
  4755. }
  4756. udelay(10); /* give the nic a chance to write to the register */
  4757. }
  4758. return 1;
  4759. }
  4760. static void
  4761. _e1000_disable(struct e1000_hw *hw)
  4762. {
  4763. /* Turn off the ethernet interface */
  4764. E1000_WRITE_REG(hw, RCTL, 0);
  4765. E1000_WRITE_REG(hw, TCTL, 0);
  4766. /* Clear the transmit ring */
  4767. E1000_WRITE_REG(hw, TDH, 0);
  4768. E1000_WRITE_REG(hw, TDT, 0);
  4769. /* Clear the receive ring */
  4770. E1000_WRITE_REG(hw, RDH, 0);
  4771. E1000_WRITE_REG(hw, RDT, 0);
  4772. mdelay(10);
  4773. }
  4774. /*reset function*/
  4775. static inline int
  4776. e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
  4777. {
  4778. e1000_reset_hw(hw);
  4779. if (hw->mac_type >= e1000_82544)
  4780. E1000_WRITE_REG(hw, WUC, 0);
  4781. return e1000_init_hw(hw, enetaddr);
  4782. }
  4783. static int
  4784. _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
  4785. {
  4786. int ret_val = 0;
  4787. ret_val = e1000_reset(hw, enetaddr);
  4788. if (ret_val < 0) {
  4789. if ((ret_val == -E1000_ERR_NOLINK) ||
  4790. (ret_val == -E1000_ERR_TIMEOUT)) {
  4791. E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
  4792. } else {
  4793. E1000_ERR(hw, "Hardware Initialization Failed\n");
  4794. }
  4795. return ret_val;
  4796. }
  4797. e1000_configure_tx(hw);
  4798. e1000_setup_rctl(hw);
  4799. e1000_configure_rx(hw);
  4800. return 0;
  4801. }
  4802. /******************************************************************************
  4803. * Gets the current PCI bus type of hardware
  4804. *
  4805. * hw - Struct containing variables accessed by shared code
  4806. *****************************************************************************/
  4807. void e1000_get_bus_type(struct e1000_hw *hw)
  4808. {
  4809. uint32_t status;
  4810. switch (hw->mac_type) {
  4811. case e1000_82542_rev2_0:
  4812. case e1000_82542_rev2_1:
  4813. hw->bus_type = e1000_bus_type_pci;
  4814. break;
  4815. case e1000_82571:
  4816. case e1000_82572:
  4817. case e1000_82573:
  4818. case e1000_82574:
  4819. case e1000_80003es2lan:
  4820. case e1000_ich8lan:
  4821. case e1000_igb:
  4822. hw->bus_type = e1000_bus_type_pci_express;
  4823. break;
  4824. default:
  4825. status = E1000_READ_REG(hw, STATUS);
  4826. hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  4827. e1000_bus_type_pcix : e1000_bus_type_pci;
  4828. break;
  4829. }
  4830. }
  4831. #ifndef CONFIG_DM_ETH
  4832. /* A list of all registered e1000 devices */
  4833. static LIST_HEAD(e1000_hw_list);
  4834. #endif
  4835. #ifdef CONFIG_DM_ETH
  4836. static int e1000_init_one(struct e1000_hw *hw, int cardnum,
  4837. struct udevice *devno, unsigned char enetaddr[6])
  4838. #else
  4839. static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
  4840. unsigned char enetaddr[6])
  4841. #endif
  4842. {
  4843. u32 val;
  4844. /* Assign the passed-in values */
  4845. #ifdef CONFIG_DM_ETH
  4846. hw->pdev = devno;
  4847. #else
  4848. hw->pdev = devno;
  4849. #endif
  4850. hw->cardnum = cardnum;
  4851. /* Print a debug message with the IO base address */
  4852. #ifdef CONFIG_DM_ETH
  4853. dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
  4854. #else
  4855. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
  4856. #endif
  4857. E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
  4858. /* Try to enable I/O accesses and bus-mastering */
  4859. val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  4860. #ifdef CONFIG_DM_ETH
  4861. dm_pci_write_config32(devno, PCI_COMMAND, val);
  4862. #else
  4863. pci_write_config_dword(devno, PCI_COMMAND, val);
  4864. #endif
  4865. /* Make sure it worked */
  4866. #ifdef CONFIG_DM_ETH
  4867. dm_pci_read_config32(devno, PCI_COMMAND, &val);
  4868. #else
  4869. pci_read_config_dword(devno, PCI_COMMAND, &val);
  4870. #endif
  4871. if (!(val & PCI_COMMAND_MEMORY)) {
  4872. E1000_ERR(hw, "Can't enable I/O memory\n");
  4873. return -ENOSPC;
  4874. }
  4875. if (!(val & PCI_COMMAND_MASTER)) {
  4876. E1000_ERR(hw, "Can't enable bus-mastering\n");
  4877. return -EPERM;
  4878. }
  4879. /* Are these variables needed? */
  4880. hw->fc = e1000_fc_default;
  4881. hw->original_fc = e1000_fc_default;
  4882. hw->autoneg_failed = 0;
  4883. hw->autoneg = 1;
  4884. hw->get_link_status = true;
  4885. #ifndef CONFIG_E1000_NO_NVM
  4886. hw->eeprom_semaphore_present = true;
  4887. #endif
  4888. #ifdef CONFIG_DM_ETH
  4889. hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4890. PCI_REGION_MEM);
  4891. #else
  4892. hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4893. PCI_REGION_MEM);
  4894. #endif
  4895. hw->mac_type = e1000_undefined;
  4896. /* MAC and Phy settings */
  4897. if (e1000_sw_init(hw) < 0) {
  4898. E1000_ERR(hw, "Software init failed\n");
  4899. return -EIO;
  4900. }
  4901. if (e1000_check_phy_reset_block(hw))
  4902. E1000_ERR(hw, "PHY Reset is blocked!\n");
  4903. /* Basic init was OK, reset the hardware and allow SPI access */
  4904. e1000_reset_hw(hw);
  4905. #ifndef CONFIG_E1000_NO_NVM
  4906. /* Validate the EEPROM and get chipset information */
  4907. if (e1000_init_eeprom_params(hw)) {
  4908. E1000_ERR(hw, "EEPROM is invalid!\n");
  4909. return -EINVAL;
  4910. }
  4911. if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
  4912. e1000_validate_eeprom_checksum(hw))
  4913. return -ENXIO;
  4914. e1000_read_mac_addr(hw, enetaddr);
  4915. #endif
  4916. e1000_get_bus_type(hw);
  4917. #ifndef CONFIG_E1000_NO_NVM
  4918. printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
  4919. enetaddr[0], enetaddr[1], enetaddr[2],
  4920. enetaddr[3], enetaddr[4], enetaddr[5]);
  4921. #else
  4922. memset(enetaddr, 0, 6);
  4923. printf("e1000: no NVM\n");
  4924. #endif
  4925. return 0;
  4926. }
  4927. /* Put the name of a device in a string */
  4928. static void e1000_name(char *str, int cardnum)
  4929. {
  4930. sprintf(str, "e1000#%u", cardnum);
  4931. }
  4932. #ifndef CONFIG_DM_ETH
  4933. /**************************************************************************
  4934. TRANSMIT - Transmit a frame
  4935. ***************************************************************************/
  4936. static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
  4937. {
  4938. struct e1000_hw *hw = nic->priv;
  4939. return _e1000_transmit(hw, txpacket, length);
  4940. }
  4941. /**************************************************************************
  4942. DISABLE - Turn off ethernet interface
  4943. ***************************************************************************/
  4944. static void
  4945. e1000_disable(struct eth_device *nic)
  4946. {
  4947. struct e1000_hw *hw = nic->priv;
  4948. _e1000_disable(hw);
  4949. }
  4950. /**************************************************************************
  4951. INIT - set up ethernet interface(s)
  4952. ***************************************************************************/
  4953. static int
  4954. e1000_init(struct eth_device *nic, struct bd_info *bis)
  4955. {
  4956. struct e1000_hw *hw = nic->priv;
  4957. return _e1000_init(hw, nic->enetaddr);
  4958. }
  4959. static int
  4960. e1000_poll(struct eth_device *nic)
  4961. {
  4962. struct e1000_hw *hw = nic->priv;
  4963. int len;
  4964. len = _e1000_poll(hw);
  4965. if (len) {
  4966. net_process_received_packet((uchar *)packet, len);
  4967. fill_rx(hw);
  4968. }
  4969. return len ? 1 : 0;
  4970. }
  4971. static int e1000_write_hwaddr(struct eth_device *dev)
  4972. {
  4973. #ifndef CONFIG_E1000_NO_NVM
  4974. unsigned char *mac = dev->enetaddr;
  4975. unsigned char current_mac[6];
  4976. struct e1000_hw *hw = dev->priv;
  4977. uint16_t data[3];
  4978. int ret_val, i;
  4979. DEBUGOUT("%s: mac=%pM\n", __func__, mac);
  4980. memset(current_mac, 0, 6);
  4981. /* Read from EEPROM, not from registers, to make sure
  4982. * the address is persistently configured
  4983. */
  4984. ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
  4985. DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
  4986. /* Only write to EEPROM if the given address is different or
  4987. * reading the current address failed
  4988. */
  4989. if (!ret_val && memcmp(current_mac, mac, 6) == 0)
  4990. return 0;
  4991. for (i = 0; i < 3; ++i)
  4992. data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
  4993. ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
  4994. if (!ret_val)
  4995. ret_val = e1000_update_eeprom_checksum_i210(hw);
  4996. return ret_val;
  4997. #else
  4998. return 0;
  4999. #endif
  5000. }
  5001. /**************************************************************************
  5002. PROBE - Look for an adapter, this routine's visible to the outside
  5003. You should omit the last argument struct pci_device * for a non-PCI NIC
  5004. ***************************************************************************/
  5005. int
  5006. e1000_initialize(struct bd_info * bis)
  5007. {
  5008. unsigned int i;
  5009. pci_dev_t devno;
  5010. int ret;
  5011. DEBUGFUNC();
  5012. /* Find and probe all the matching PCI devices */
  5013. for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
  5014. /*
  5015. * These will never get freed due to errors, this allows us to
  5016. * perform SPI EEPROM programming from U-Boot, for example.
  5017. */
  5018. struct eth_device *nic = malloc(sizeof(*nic));
  5019. struct e1000_hw *hw = malloc(sizeof(*hw));
  5020. if (!nic || !hw) {
  5021. printf("e1000#%u: Out of Memory!\n", i);
  5022. free(nic);
  5023. free(hw);
  5024. continue;
  5025. }
  5026. /* Make sure all of the fields are initially zeroed */
  5027. memset(nic, 0, sizeof(*nic));
  5028. memset(hw, 0, sizeof(*hw));
  5029. nic->priv = hw;
  5030. /* Generate a card name */
  5031. e1000_name(nic->name, i);
  5032. hw->name = nic->name;
  5033. ret = e1000_init_one(hw, i, devno, nic->enetaddr);
  5034. if (ret)
  5035. continue;
  5036. list_add_tail(&hw->list_node, &e1000_hw_list);
  5037. hw->nic = nic;
  5038. /* Set up the function pointers and register the device */
  5039. nic->init = e1000_init;
  5040. nic->recv = e1000_poll;
  5041. nic->send = e1000_transmit;
  5042. nic->halt = e1000_disable;
  5043. nic->write_hwaddr = e1000_write_hwaddr;
  5044. eth_register(nic);
  5045. }
  5046. return i;
  5047. }
  5048. struct e1000_hw *e1000_find_card(unsigned int cardnum)
  5049. {
  5050. struct e1000_hw *hw;
  5051. list_for_each_entry(hw, &e1000_hw_list, list_node)
  5052. if (hw->cardnum == cardnum)
  5053. return hw;
  5054. return NULL;
  5055. }
  5056. #endif /* !CONFIG_DM_ETH */
  5057. #ifdef CONFIG_CMD_E1000
  5058. static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
  5059. char *const argv[])
  5060. {
  5061. unsigned char *mac = NULL;
  5062. #ifdef CONFIG_DM_ETH
  5063. struct eth_pdata *plat;
  5064. struct udevice *dev;
  5065. char name[30];
  5066. int ret;
  5067. #endif
  5068. #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
  5069. struct e1000_hw *hw;
  5070. #endif
  5071. int cardnum;
  5072. if (argc < 3) {
  5073. cmd_usage(cmdtp);
  5074. return 1;
  5075. }
  5076. /* Make sure we can find the requested e1000 card */
  5077. cardnum = simple_strtoul(argv[1], NULL, 10);
  5078. #ifdef CONFIG_DM_ETH
  5079. e1000_name(name, cardnum);
  5080. ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
  5081. if (!ret) {
  5082. plat = dev_get_platdata(dev);
  5083. mac = plat->enetaddr;
  5084. }
  5085. #else
  5086. hw = e1000_find_card(cardnum);
  5087. if (hw)
  5088. mac = hw->nic->enetaddr;
  5089. #endif
  5090. if (!mac) {
  5091. printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
  5092. return 1;
  5093. }
  5094. if (!strcmp(argv[2], "print-mac-address")) {
  5095. printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
  5096. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  5097. return 0;
  5098. }
  5099. #ifdef CONFIG_E1000_SPI
  5100. #ifdef CONFIG_DM_ETH
  5101. hw = dev_get_priv(dev);
  5102. #endif
  5103. /* Handle the "SPI" subcommand */
  5104. if (!strcmp(argv[2], "spi"))
  5105. return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
  5106. #endif
  5107. cmd_usage(cmdtp);
  5108. return 1;
  5109. }
  5110. U_BOOT_CMD(
  5111. e1000, 7, 0, do_e1000,
  5112. "Intel e1000 controller management",
  5113. /* */"<card#> print-mac-address\n"
  5114. #ifdef CONFIG_E1000_SPI
  5115. "e1000 <card#> spi show [<offset> [<length>]]\n"
  5116. "e1000 <card#> spi dump <addr> <offset> <length>\n"
  5117. "e1000 <card#> spi program <addr> <offset> <length>\n"
  5118. "e1000 <card#> spi checksum [update]\n"
  5119. #endif
  5120. " - Manage the Intel E1000 PCI device"
  5121. );
  5122. #endif /* not CONFIG_CMD_E1000 */
  5123. #ifdef CONFIG_DM_ETH
  5124. static int e1000_eth_start(struct udevice *dev)
  5125. {
  5126. struct eth_pdata *plat = dev_get_platdata(dev);
  5127. struct e1000_hw *hw = dev_get_priv(dev);
  5128. return _e1000_init(hw, plat->enetaddr);
  5129. }
  5130. static void e1000_eth_stop(struct udevice *dev)
  5131. {
  5132. struct e1000_hw *hw = dev_get_priv(dev);
  5133. _e1000_disable(hw);
  5134. }
  5135. static int e1000_eth_send(struct udevice *dev, void *packet, int length)
  5136. {
  5137. struct e1000_hw *hw = dev_get_priv(dev);
  5138. int ret;
  5139. ret = _e1000_transmit(hw, packet, length);
  5140. return ret ? 0 : -ETIMEDOUT;
  5141. }
  5142. static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  5143. {
  5144. struct e1000_hw *hw = dev_get_priv(dev);
  5145. int len;
  5146. len = _e1000_poll(hw);
  5147. if (len)
  5148. *packetp = packet;
  5149. return len ? len : -EAGAIN;
  5150. }
  5151. static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
  5152. {
  5153. struct e1000_hw *hw = dev_get_priv(dev);
  5154. fill_rx(hw);
  5155. return 0;
  5156. }
  5157. static int e1000_eth_probe(struct udevice *dev)
  5158. {
  5159. struct eth_pdata *plat = dev_get_platdata(dev);
  5160. struct e1000_hw *hw = dev_get_priv(dev);
  5161. int ret;
  5162. hw->name = dev->name;
  5163. ret = e1000_init_one(hw, trailing_strtol(dev->name),
  5164. dev, plat->enetaddr);
  5165. if (ret < 0) {
  5166. printf(pr_fmt("failed to initialize card: %d\n"), ret);
  5167. return ret;
  5168. }
  5169. return 0;
  5170. }
  5171. static int e1000_eth_bind(struct udevice *dev)
  5172. {
  5173. char name[20];
  5174. /*
  5175. * A simple way to number the devices. When device tree is used this
  5176. * is unnecessary, but when the device is just discovered on the PCI
  5177. * bus we need a name. We could instead have the uclass figure out
  5178. * which devices are different and number them.
  5179. */
  5180. e1000_name(name, num_cards++);
  5181. return device_set_name(dev, name);
  5182. }
  5183. static const struct eth_ops e1000_eth_ops = {
  5184. .start = e1000_eth_start,
  5185. .send = e1000_eth_send,
  5186. .recv = e1000_eth_recv,
  5187. .stop = e1000_eth_stop,
  5188. .free_pkt = e1000_free_pkt,
  5189. };
  5190. static const struct udevice_id e1000_eth_ids[] = {
  5191. { .compatible = "intel,e1000" },
  5192. { }
  5193. };
  5194. U_BOOT_DRIVER(eth_e1000) = {
  5195. .name = "eth_e1000",
  5196. .id = UCLASS_ETH,
  5197. .of_match = e1000_eth_ids,
  5198. .bind = e1000_eth_bind,
  5199. .probe = e1000_eth_probe,
  5200. .ops = &e1000_eth_ops,
  5201. .priv_auto_alloc_size = sizeof(struct e1000_hw),
  5202. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  5203. };
  5204. U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
  5205. #endif