dwmac_socfpga.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  4. *
  5. * Altera SoCFPGA EMAC extras
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <dm.h>
  10. #include <clk.h>
  11. #include <phy.h>
  12. #include <regmap.h>
  13. #include <reset.h>
  14. #include <syscon.h>
  15. #include "designware.h"
  16. #include <dm/device_compat.h>
  17. #include <linux/err.h>
  18. #include <asm/arch/system_manager.h>
  19. struct dwmac_socfpga_platdata {
  20. struct dw_eth_pdata dw_eth_pdata;
  21. void *phy_intf;
  22. u32 reg_shift;
  23. };
  24. static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
  25. {
  26. struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
  27. struct regmap *regmap;
  28. struct ofnode_phandle_args args;
  29. void *range;
  30. int ret;
  31. ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
  32. 2, 0, &args);
  33. if (ret) {
  34. dev_err(dev, "Failed to get syscon: %d\n", ret);
  35. return ret;
  36. }
  37. if (args.args_count != 2) {
  38. dev_err(dev, "Invalid number of syscon args\n");
  39. return -EINVAL;
  40. }
  41. regmap = syscon_node_to_regmap(args.node);
  42. if (IS_ERR(regmap)) {
  43. ret = PTR_ERR(regmap);
  44. dev_err(dev, "Failed to get regmap: %d\n", ret);
  45. return ret;
  46. }
  47. range = regmap_get_range(regmap, 0);
  48. if (!range) {
  49. dev_err(dev, "Failed to get regmap range\n");
  50. return -ENOMEM;
  51. }
  52. pdata->phy_intf = range + args.args[0];
  53. pdata->reg_shift = args.args[1];
  54. return designware_eth_ofdata_to_platdata(dev);
  55. }
  56. static int dwmac_socfpga_probe(struct udevice *dev)
  57. {
  58. struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
  59. struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
  60. struct reset_ctl_bulk reset_bulk;
  61. int ret;
  62. u32 modereg;
  63. u32 modemask;
  64. switch (edata->phy_interface) {
  65. case PHY_INTERFACE_MODE_MII:
  66. case PHY_INTERFACE_MODE_GMII:
  67. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
  68. break;
  69. case PHY_INTERFACE_MODE_RMII:
  70. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
  71. break;
  72. case PHY_INTERFACE_MODE_RGMII:
  73. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
  74. break;
  75. default:
  76. dev_err(dev, "Unsupported PHY mode\n");
  77. return -EINVAL;
  78. }
  79. ret = reset_get_bulk(dev, &reset_bulk);
  80. if (ret) {
  81. dev_err(dev, "Failed to get reset: %d\n", ret);
  82. return ret;
  83. }
  84. reset_assert_bulk(&reset_bulk);
  85. modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
  86. clrsetbits_le32(pdata->phy_intf, modemask,
  87. modereg << pdata->reg_shift);
  88. reset_release_bulk(&reset_bulk);
  89. return designware_eth_probe(dev);
  90. }
  91. static const struct udevice_id dwmac_socfpga_ids[] = {
  92. { .compatible = "altr,socfpga-stmmac" },
  93. { }
  94. };
  95. U_BOOT_DRIVER(dwmac_socfpga) = {
  96. .name = "dwmac_socfpga",
  97. .id = UCLASS_ETH,
  98. .of_match = dwmac_socfpga_ids,
  99. .ofdata_to_platdata = dwmac_socfpga_ofdata_to_platdata,
  100. .probe = dwmac_socfpga_probe,
  101. .ops = &designware_eth_ops,
  102. .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
  103. .platdata_auto_alloc_size = sizeof(struct dwmac_socfpga_platdata),
  104. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  105. };