dm9000x.h 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140
  1. /*
  2. * dm9000 Ethernet
  3. */
  4. #ifdef CONFIG_DRIVER_DM9000
  5. #define DM9000_ID 0x90000A46
  6. #define DM9000_PKT_MAX 1536 /* Received packet max size */
  7. #define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
  8. /* although the registers are 16 bit, they are 32-bit aligned.
  9. */
  10. #define DM9000_NCR 0x00
  11. #define DM9000_NSR 0x01
  12. #define DM9000_TCR 0x02
  13. #define DM9000_TSR1 0x03
  14. #define DM9000_TSR2 0x04
  15. #define DM9000_RCR 0x05
  16. #define DM9000_RSR 0x06
  17. #define DM9000_ROCR 0x07
  18. #define DM9000_BPTR 0x08
  19. #define DM9000_FCTR 0x09
  20. #define DM9000_FCR 0x0A
  21. #define DM9000_EPCR 0x0B
  22. #define DM9000_EPAR 0x0C
  23. #define DM9000_EPDRL 0x0D
  24. #define DM9000_EPDRH 0x0E
  25. #define DM9000_WCR 0x0F
  26. #define DM9000_PAR 0x10
  27. #define DM9000_MAR 0x16
  28. #define DM9000_GPCR 0x1e
  29. #define DM9000_GPR 0x1f
  30. #define DM9000_TRPAL 0x22
  31. #define DM9000_TRPAH 0x23
  32. #define DM9000_RWPAL 0x24
  33. #define DM9000_RWPAH 0x25
  34. #define DM9000_VIDL 0x28
  35. #define DM9000_VIDH 0x29
  36. #define DM9000_PIDL 0x2A
  37. #define DM9000_PIDH 0x2B
  38. #define DM9000_CHIPR 0x2C
  39. #define DM9000_SMCR 0x2F
  40. #define DM9000_PHY 0x40 /* PHY address 0x01 */
  41. #define DM9000_MRCMDX 0xF0
  42. #define DM9000_MRCMD 0xF2
  43. #define DM9000_MRRL 0xF4
  44. #define DM9000_MRRH 0xF5
  45. #define DM9000_MWCMDX 0xF6
  46. #define DM9000_MWCMD 0xF8
  47. #define DM9000_MWRL 0xFA
  48. #define DM9000_MWRH 0xFB
  49. #define DM9000_TXPLL 0xFC
  50. #define DM9000_TXPLH 0xFD
  51. #define DM9000_ISR 0xFE
  52. #define DM9000_IMR 0xFF
  53. #define NCR_EXT_PHY (1<<7)
  54. #define NCR_WAKEEN (1<<6)
  55. #define NCR_FCOL (1<<4)
  56. #define NCR_FDX (1<<3)
  57. #define NCR_LBK (3<<1)
  58. #define NCR_LBK_INT_MAC (1<<1)
  59. #define NCR_LBK_INT_PHY (2<<1)
  60. #define NCR_RST (1<<0)
  61. #define NSR_SPEED (1<<7)
  62. #define NSR_LINKST (1<<6)
  63. #define NSR_WAKEST (1<<5)
  64. #define NSR_TX2END (1<<3)
  65. #define NSR_TX1END (1<<2)
  66. #define NSR_RXOV (1<<1)
  67. #define TCR_TJDIS (1<<6)
  68. #define TCR_EXCECM (1<<5)
  69. #define TCR_PAD_DIS2 (1<<4)
  70. #define TCR_CRC_DIS2 (1<<3)
  71. #define TCR_PAD_DIS1 (1<<2)
  72. #define TCR_CRC_DIS1 (1<<1)
  73. #define TCR_TXREQ (1<<0)
  74. #define TSR_TJTO (1<<7)
  75. #define TSR_LC (1<<6)
  76. #define TSR_NC (1<<5)
  77. #define TSR_LCOL (1<<4)
  78. #define TSR_COL (1<<3)
  79. #define TSR_EC (1<<2)
  80. #define RCR_WTDIS (1<<6)
  81. #define RCR_DIS_LONG (1<<5)
  82. #define RCR_DIS_CRC (1<<4)
  83. #define RCR_ALL (1<<3)
  84. #define RCR_RUNT (1<<2)
  85. #define RCR_PRMSC (1<<1)
  86. #define RCR_RXEN (1<<0)
  87. #define RSR_RF (1<<7)
  88. #define RSR_MF (1<<6)
  89. #define RSR_LCS (1<<5)
  90. #define RSR_RWTO (1<<4)
  91. #define RSR_PLE (1<<3)
  92. #define RSR_AE (1<<2)
  93. #define RSR_CE (1<<1)
  94. #define RSR_FOE (1<<0)
  95. #define EPCR_EPOS_PHY (1<<3)
  96. #define EPCR_EPOS_EE (0<<3)
  97. #define EPCR_ERPRR (1<<2)
  98. #define EPCR_ERPRW (1<<1)
  99. #define EPCR_ERRE (1<<0)
  100. #define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
  101. #define FCTR_LWOT(ot) ( ot & 0xf )
  102. #define BPTR_BPHW(x) ((x) << 4)
  103. #define BPTR_JPT_200US (0x07)
  104. #define BPTR_JPT_600US (0x0f)
  105. #define IMR_PAR (1<<7)
  106. #define IMR_ROOM (1<<3)
  107. #define IMR_ROM (1<<2)
  108. #define IMR_PTM (1<<1)
  109. #define IMR_PRM (1<<0)
  110. #define ISR_ROOS (1<<3)
  111. #define ISR_ROS (1<<2)
  112. #define ISR_PTS (1<<1)
  113. #define ISR_PRS (1<<0)
  114. #define GPCR_GPIO0_OUT (1<<0)
  115. #define GPR_PHY_PWROFF (1<<0)
  116. #endif