dm9000x.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. dm9000.c: Version 1.2 12/15/2003
  4. A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
  5. Copyright (C) 1997 Sten Wang
  6. (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
  7. V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
  8. 06/22/2001 Support DM9801 progrmming
  9. E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
  10. E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
  11. R17 = (R17 & 0xfff0) | NF + 3
  12. E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
  13. R17 = (R17 & 0xfff0) | NF
  14. v1.00 modify by simon 2001.9.5
  15. change for kernel 2.4.x
  16. v1.1 11/09/2001 fix force mode bug
  17. v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
  18. Fixed phy reset.
  19. Added tx/rx 32 bit mode.
  20. Cleaned up for kernel merge.
  21. --------------------------------------
  22. 12/15/2003 Initial port to u-boot by
  23. Sascha Hauer <saschahauer@web.de>
  24. 06/03/2008 Remy Bohmer <linux@bohmer.net>
  25. - Fixed the driver to work with DM9000A.
  26. (check on ISR receive status bit before reading the
  27. FIFO as described in DM9000 programming guide and
  28. application notes)
  29. - Added autodetect of databus width.
  30. - Made debug code compile again.
  31. - Adapt eth_send such that it matches the DM9000*
  32. application notes. Needed to make it work properly
  33. for DM9000A.
  34. - Adapted reset procedure to match DM9000 application
  35. notes (i.e. double reset)
  36. - some minor code cleanups
  37. These changes are tested with DM9000{A,EP,E} together
  38. with a 200MHz Atmel AT91SAM9261 core
  39. TODO: external MII is not functional, only internal at the moment.
  40. */
  41. #include <common.h>
  42. #include <command.h>
  43. #include <net.h>
  44. #include <asm/io.h>
  45. #include <dm9000.h>
  46. #include <linux/delay.h>
  47. #include "dm9000x.h"
  48. /* Board/System/Debug information/definition ---------------- */
  49. /* #define CONFIG_DM9000_DEBUG */
  50. #ifdef CONFIG_DM9000_DEBUG
  51. #define DM9000_DBG(fmt,args...) printf(fmt, ##args)
  52. #define DM9000_DMP_PACKET(func,packet,length) \
  53. do { \
  54. int i; \
  55. printf("%s: length: %d\n", func, length); \
  56. for (i = 0; i < length; i++) { \
  57. if (i % 8 == 0) \
  58. printf("\n%s: %02x: ", func, i); \
  59. printf("%02x ", ((unsigned char *) packet)[i]); \
  60. } printf("\n"); \
  61. } while(0)
  62. #else
  63. #define DM9000_DBG(fmt,args...)
  64. #define DM9000_DMP_PACKET(func,packet,length)
  65. #endif
  66. /* Structure/enum declaration ------------------------------- */
  67. typedef struct board_info {
  68. u32 runt_length_counter; /* counter: RX length < 64byte */
  69. u32 long_length_counter; /* counter: RX length > 1514byte */
  70. u32 reset_counter; /* counter: RESET */
  71. u32 reset_tx_timeout; /* RESET caused by TX Timeout */
  72. u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
  73. u16 tx_pkt_cnt;
  74. u16 queue_start_addr;
  75. u16 dbug_cnt;
  76. u8 phy_addr;
  77. u8 device_wait_reset; /* device state */
  78. unsigned char srom[128];
  79. void (*outblk)(volatile void *data_ptr, int count);
  80. void (*inblk)(void *data_ptr, int count);
  81. void (*rx_status)(u16 *RxStatus, u16 *RxLen);
  82. struct eth_device netdev;
  83. } board_info_t;
  84. static board_info_t dm9000_info;
  85. /* function declaration ------------------------------------- */
  86. static int dm9000_probe(void);
  87. static u16 dm9000_phy_read(int);
  88. static void dm9000_phy_write(int, u16);
  89. static u8 DM9000_ior(int);
  90. static void DM9000_iow(int reg, u8 value);
  91. /* DM9000 network board routine ---------------------------- */
  92. #ifndef CONFIG_DM9000_BYTE_SWAPPED
  93. #define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
  94. #define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
  95. #define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
  96. #define DM9000_inb(r) readb((volatile u8 *)(r))
  97. #define DM9000_inw(r) readw((volatile u16 *)(r))
  98. #define DM9000_inl(r) readl((volatile u32 *)(r))
  99. #else
  100. #define DM9000_outb(d, r) __raw_writeb(d, r)
  101. #define DM9000_outw(d, r) __raw_writew(d, r)
  102. #define DM9000_outl(d, r) __raw_writel(d, r)
  103. #define DM9000_inb(r) __raw_readb(r)
  104. #define DM9000_inw(r) __raw_readw(r)
  105. #define DM9000_inl(r) __raw_readl(r)
  106. #endif
  107. #ifdef CONFIG_DM9000_DEBUG
  108. static void
  109. dump_regs(void)
  110. {
  111. DM9000_DBG("\n");
  112. DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
  113. DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
  114. DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
  115. DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
  116. DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
  117. DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
  118. DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
  119. DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
  120. DM9000_DBG("\n");
  121. }
  122. #endif
  123. static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
  124. {
  125. int i;
  126. for (i = 0; i < count; i++)
  127. DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
  128. }
  129. static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
  130. {
  131. int i;
  132. u32 tmplen = (count + 1) / 2;
  133. for (i = 0; i < tmplen; i++)
  134. DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
  135. }
  136. static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
  137. {
  138. int i;
  139. u32 tmplen = (count + 3) / 4;
  140. for (i = 0; i < tmplen; i++)
  141. DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
  142. }
  143. static void dm9000_inblk_8bit(void *data_ptr, int count)
  144. {
  145. int i;
  146. for (i = 0; i < count; i++)
  147. ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
  148. }
  149. static void dm9000_inblk_16bit(void *data_ptr, int count)
  150. {
  151. int i;
  152. u32 tmplen = (count + 1) / 2;
  153. for (i = 0; i < tmplen; i++)
  154. ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
  155. }
  156. static void dm9000_inblk_32bit(void *data_ptr, int count)
  157. {
  158. int i;
  159. u32 tmplen = (count + 3) / 4;
  160. for (i = 0; i < tmplen; i++)
  161. ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
  162. }
  163. static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
  164. {
  165. u32 tmpdata;
  166. DM9000_outb(DM9000_MRCMD, DM9000_IO);
  167. tmpdata = DM9000_inl(DM9000_DATA);
  168. *RxStatus = __le16_to_cpu(tmpdata);
  169. *RxLen = __le16_to_cpu(tmpdata >> 16);
  170. }
  171. static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
  172. {
  173. DM9000_outb(DM9000_MRCMD, DM9000_IO);
  174. *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
  175. *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
  176. }
  177. static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
  178. {
  179. DM9000_outb(DM9000_MRCMD, DM9000_IO);
  180. *RxStatus =
  181. __le16_to_cpu(DM9000_inb(DM9000_DATA) +
  182. (DM9000_inb(DM9000_DATA) << 8));
  183. *RxLen =
  184. __le16_to_cpu(DM9000_inb(DM9000_DATA) +
  185. (DM9000_inb(DM9000_DATA) << 8));
  186. }
  187. /*
  188. Search DM9000 board, allocate space and register it
  189. */
  190. int
  191. dm9000_probe(void)
  192. {
  193. u32 id_val;
  194. id_val = DM9000_ior(DM9000_VIDL);
  195. id_val |= DM9000_ior(DM9000_VIDH) << 8;
  196. id_val |= DM9000_ior(DM9000_PIDL) << 16;
  197. id_val |= DM9000_ior(DM9000_PIDH) << 24;
  198. if (id_val == DM9000_ID) {
  199. printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
  200. id_val);
  201. return 0;
  202. } else {
  203. printf("dm9000 not found at 0x%08x id: 0x%08x\n",
  204. CONFIG_DM9000_BASE, id_val);
  205. return -1;
  206. }
  207. }
  208. /* General Purpose dm9000 reset routine */
  209. static void
  210. dm9000_reset(void)
  211. {
  212. DM9000_DBG("resetting DM9000\n");
  213. /* Reset DM9000,
  214. see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
  215. /* DEBUG: Make all GPIO0 outputs, all others inputs */
  216. DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
  217. /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
  218. DM9000_iow(DM9000_GPR, 0);
  219. /* Step 2: Software reset */
  220. DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
  221. do {
  222. DM9000_DBG("resetting the DM9000, 1st reset\n");
  223. udelay(25); /* Wait at least 20 us */
  224. } while (DM9000_ior(DM9000_NCR) & 1);
  225. DM9000_iow(DM9000_NCR, 0);
  226. DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
  227. do {
  228. DM9000_DBG("resetting the DM9000, 2nd reset\n");
  229. udelay(25); /* Wait at least 20 us */
  230. } while (DM9000_ior(DM9000_NCR) & 1);
  231. /* Check whether the ethernet controller is present */
  232. if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
  233. (DM9000_ior(DM9000_PIDH) != 0x90))
  234. printf("ERROR: resetting DM9000 -> not responding\n");
  235. }
  236. /* Initialize dm9000 board
  237. */
  238. static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
  239. {
  240. int i, oft, lnk;
  241. u8 io_mode;
  242. struct board_info *db = &dm9000_info;
  243. DM9000_DBG("%s\n", __func__);
  244. /* RESET device */
  245. dm9000_reset();
  246. if (dm9000_probe() < 0)
  247. return -1;
  248. /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
  249. io_mode = DM9000_ior(DM9000_ISR) >> 6;
  250. switch (io_mode) {
  251. case 0x0: /* 16-bit mode */
  252. printf("DM9000: running in 16 bit mode\n");
  253. db->outblk = dm9000_outblk_16bit;
  254. db->inblk = dm9000_inblk_16bit;
  255. db->rx_status = dm9000_rx_status_16bit;
  256. break;
  257. case 0x01: /* 32-bit mode */
  258. printf("DM9000: running in 32 bit mode\n");
  259. db->outblk = dm9000_outblk_32bit;
  260. db->inblk = dm9000_inblk_32bit;
  261. db->rx_status = dm9000_rx_status_32bit;
  262. break;
  263. case 0x02: /* 8 bit mode */
  264. printf("DM9000: running in 8 bit mode\n");
  265. db->outblk = dm9000_outblk_8bit;
  266. db->inblk = dm9000_inblk_8bit;
  267. db->rx_status = dm9000_rx_status_8bit;
  268. break;
  269. default:
  270. /* Assume 8 bit mode, will probably not work anyway */
  271. printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
  272. db->outblk = dm9000_outblk_8bit;
  273. db->inblk = dm9000_inblk_8bit;
  274. db->rx_status = dm9000_rx_status_8bit;
  275. break;
  276. }
  277. /* Program operating register, only internal phy supported */
  278. DM9000_iow(DM9000_NCR, 0x0);
  279. /* TX Polling clear */
  280. DM9000_iow(DM9000_TCR, 0);
  281. /* Less 3Kb, 200us */
  282. DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
  283. /* Flow Control : High/Low Water */
  284. DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
  285. /* SH FIXME: This looks strange! Flow Control */
  286. DM9000_iow(DM9000_FCR, 0x0);
  287. /* Special Mode */
  288. DM9000_iow(DM9000_SMCR, 0);
  289. /* clear TX status */
  290. DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
  291. /* Clear interrupt status */
  292. DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
  293. printf("MAC: %pM\n", dev->enetaddr);
  294. if (!is_valid_ethaddr(dev->enetaddr)) {
  295. printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
  296. }
  297. /* fill device MAC address registers */
  298. for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
  299. DM9000_iow(oft, dev->enetaddr[i]);
  300. for (i = 0, oft = 0x16; i < 8; i++, oft++)
  301. DM9000_iow(oft, 0xff);
  302. /* read back mac, just to be sure */
  303. for (i = 0, oft = 0x10; i < 6; i++, oft++)
  304. DM9000_DBG("%02x:", DM9000_ior(oft));
  305. DM9000_DBG("\n");
  306. /* Activate DM9000 */
  307. /* RX enable */
  308. DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
  309. /* Enable TX/RX interrupt mask */
  310. DM9000_iow(DM9000_IMR, IMR_PAR);
  311. i = 0;
  312. while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */
  313. udelay(1000);
  314. i++;
  315. if (i == 10000) {
  316. printf("could not establish link\n");
  317. return 0;
  318. }
  319. }
  320. /* see what we've got */
  321. lnk = dm9000_phy_read(17) >> 12;
  322. printf("operating at ");
  323. switch (lnk) {
  324. case 1:
  325. printf("10M half duplex ");
  326. break;
  327. case 2:
  328. printf("10M full duplex ");
  329. break;
  330. case 4:
  331. printf("100M half duplex ");
  332. break;
  333. case 8:
  334. printf("100M full duplex ");
  335. break;
  336. default:
  337. printf("unknown: %d ", lnk);
  338. break;
  339. }
  340. printf("mode\n");
  341. return 0;
  342. }
  343. /*
  344. Hardware start transmission.
  345. Send a packet to media from the upper layer.
  346. */
  347. static int dm9000_send(struct eth_device *netdev, void *packet, int length)
  348. {
  349. int tmo;
  350. struct board_info *db = &dm9000_info;
  351. DM9000_DMP_PACKET(__func__ , packet, length);
  352. DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
  353. /* Move data to DM9000 TX RAM */
  354. DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
  355. /* push the data to the TX-fifo */
  356. (db->outblk)(packet, length);
  357. /* Set TX length to DM9000 */
  358. DM9000_iow(DM9000_TXPLL, length & 0xff);
  359. DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
  360. /* Issue TX polling command */
  361. DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
  362. /* wait for end of transmission */
  363. tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
  364. while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
  365. !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
  366. if (get_timer(0) >= tmo) {
  367. printf("transmission timeout\n");
  368. break;
  369. }
  370. }
  371. DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
  372. DM9000_DBG("transmit done\n\n");
  373. return 0;
  374. }
  375. /*
  376. Stop the interface.
  377. The interface is stopped when it is brought.
  378. */
  379. static void dm9000_halt(struct eth_device *netdev)
  380. {
  381. DM9000_DBG("%s\n", __func__);
  382. /* RESET devie */
  383. dm9000_phy_write(0, 0x8000); /* PHY RESET */
  384. DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
  385. DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
  386. DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
  387. }
  388. /*
  389. Received a packet and pass to upper layer
  390. */
  391. static int dm9000_rx(struct eth_device *netdev)
  392. {
  393. u8 rxbyte;
  394. u8 *rdptr = (u8 *)net_rx_packets[0];
  395. u16 RxStatus, RxLen = 0;
  396. struct board_info *db = &dm9000_info;
  397. /* Check packet ready or not, we must check
  398. the ISR status first for DM9000A */
  399. if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
  400. return 0;
  401. DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
  402. /* There is _at least_ 1 package in the fifo, read them all */
  403. for (;;) {
  404. DM9000_ior(DM9000_MRCMDX); /* Dummy read */
  405. /* Get most updated data,
  406. only look at bits 0:1, See application notes DM9000 */
  407. rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
  408. /* Status check: this byte must be 0 or 1 */
  409. if (rxbyte > DM9000_PKT_RDY) {
  410. DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
  411. DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
  412. printf("DM9000 error: status check fail: 0x%x\n",
  413. rxbyte);
  414. return 0;
  415. }
  416. if (rxbyte != DM9000_PKT_RDY)
  417. return 0; /* No packet received, ignore */
  418. DM9000_DBG("receiving packet\n");
  419. /* A packet ready now & Get status/length */
  420. (db->rx_status)(&RxStatus, &RxLen);
  421. DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
  422. /* Move data from DM9000 */
  423. /* Read received packet from RX SRAM */
  424. (db->inblk)(rdptr, RxLen);
  425. if ((RxStatus & 0xbf00) || (RxLen < 0x40)
  426. || (RxLen > DM9000_PKT_MAX)) {
  427. if (RxStatus & 0x100) {
  428. printf("rx fifo error\n");
  429. }
  430. if (RxStatus & 0x200) {
  431. printf("rx crc error\n");
  432. }
  433. if (RxStatus & 0x8000) {
  434. printf("rx length error\n");
  435. }
  436. if (RxLen > DM9000_PKT_MAX) {
  437. printf("rx length too big\n");
  438. dm9000_reset();
  439. }
  440. } else {
  441. DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
  442. DM9000_DBG("passing packet to upper layer\n");
  443. net_process_received_packet(net_rx_packets[0], RxLen);
  444. }
  445. }
  446. return 0;
  447. }
  448. /*
  449. Read a word data from SROM
  450. */
  451. #if !defined(CONFIG_DM9000_NO_SROM)
  452. void dm9000_read_srom_word(int offset, u8 *to)
  453. {
  454. DM9000_iow(DM9000_EPAR, offset);
  455. DM9000_iow(DM9000_EPCR, 0x4);
  456. udelay(8000);
  457. DM9000_iow(DM9000_EPCR, 0x0);
  458. to[0] = DM9000_ior(DM9000_EPDRL);
  459. to[1] = DM9000_ior(DM9000_EPDRH);
  460. }
  461. void dm9000_write_srom_word(int offset, u16 val)
  462. {
  463. DM9000_iow(DM9000_EPAR, offset);
  464. DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
  465. DM9000_iow(DM9000_EPDRL, (val & 0xff));
  466. DM9000_iow(DM9000_EPCR, 0x12);
  467. udelay(8000);
  468. DM9000_iow(DM9000_EPCR, 0);
  469. }
  470. #endif
  471. static void dm9000_get_enetaddr(struct eth_device *dev)
  472. {
  473. #if !defined(CONFIG_DM9000_NO_SROM)
  474. int i;
  475. for (i = 0; i < 3; i++)
  476. dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
  477. #endif
  478. }
  479. /*
  480. Read a byte from I/O port
  481. */
  482. static u8
  483. DM9000_ior(int reg)
  484. {
  485. DM9000_outb(reg, DM9000_IO);
  486. return DM9000_inb(DM9000_DATA);
  487. }
  488. /*
  489. Write a byte to I/O port
  490. */
  491. static void
  492. DM9000_iow(int reg, u8 value)
  493. {
  494. DM9000_outb(reg, DM9000_IO);
  495. DM9000_outb(value, DM9000_DATA);
  496. }
  497. /*
  498. Read a word from phyxcer
  499. */
  500. static u16
  501. dm9000_phy_read(int reg)
  502. {
  503. u16 val;
  504. /* Fill the phyxcer register into REG_0C */
  505. DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
  506. DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
  507. udelay(100); /* Wait read complete */
  508. DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
  509. val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
  510. /* The read data keeps on REG_0D & REG_0E */
  511. DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val);
  512. return val;
  513. }
  514. /*
  515. Write a word to phyxcer
  516. */
  517. static void
  518. dm9000_phy_write(int reg, u16 value)
  519. {
  520. /* Fill the phyxcer register into REG_0C */
  521. DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
  522. /* Fill the written data into REG_0D & REG_0E */
  523. DM9000_iow(DM9000_EPDRL, (value & 0xff));
  524. DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
  525. DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
  526. udelay(500); /* Wait write complete */
  527. DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
  528. DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value);
  529. }
  530. int dm9000_initialize(struct bd_info *bis)
  531. {
  532. struct eth_device *dev = &(dm9000_info.netdev);
  533. /* Load MAC address from EEPROM */
  534. dm9000_get_enetaddr(dev);
  535. dev->init = dm9000_init;
  536. dev->halt = dm9000_halt;
  537. dev->send = dm9000_send;
  538. dev->recv = dm9000_rx;
  539. strcpy(dev->name, "dm9000");
  540. eth_register(dev);
  541. return 0;
  542. }