designware.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #ifndef _DW_ETH_H
  7. #define _DW_ETH_H
  8. #include <asm/cache.h>
  9. #include <net.h>
  10. #if CONFIG_IS_ENABLED(DM_GPIO)
  11. #include <asm-generic/gpio.h>
  12. #endif
  13. #define CONFIG_TX_DESCR_NUM 16
  14. #define CONFIG_RX_DESCR_NUM 16
  15. #define CONFIG_ETH_BUFSIZE 2048
  16. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  17. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  18. //#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
  19. #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ * 10000)
  20. #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
  21. struct eth_mac_regs {
  22. u32 conf; /* 0x00 */
  23. u32 framefilt; /* 0x04 */
  24. u32 hashtablehigh; /* 0x08 */
  25. u32 hashtablelow; /* 0x0c */
  26. u32 miiaddr; /* 0x10 */
  27. u32 miidata; /* 0x14 */
  28. u32 flowcontrol; /* 0x18 */
  29. u32 vlantag; /* 0x1c */
  30. u32 version; /* 0x20 */
  31. u8 reserved_1[20];
  32. u32 intreg; /* 0x38 */
  33. u32 intmask; /* 0x3c */
  34. u32 macaddr0hi; /* 0x40 */
  35. u32 macaddr0lo; /* 0x44 */
  36. };
  37. /* MAC configuration register definitions */
  38. #define FRAMEBURSTENABLE (1 << 21)
  39. #define MII_PORTSELECT (1 << 15)
  40. #define FES_100 (1 << 14)
  41. #define DISABLERXOWN (1 << 13)
  42. #define FULLDPLXMODE (1 << 11)
  43. #define LINK_UP (1 << 8)
  44. #define RXENABLE (1 << 2)
  45. #define TXENABLE (1 << 3)
  46. /* MII address register definitions */
  47. #define MII_BUSY (1 << 0)
  48. #define MII_WRITE (1 << 1)
  49. #define MII_CLKRANGE_60_100M (0)
  50. #define MII_CLKRANGE_100_150M (0x4)
  51. #define MII_CLKRANGE_20_35M (0x8)
  52. #define MII_CLKRANGE_35_60M (0xC)
  53. #define MII_CLKRANGE_150_250M (0x10)
  54. #define MII_CLKRANGE_250_300M (0x14)
  55. #define MIIADDRSHIFT (11)
  56. #define MIIREGSHIFT (6)
  57. #define MII_REGMSK (0x1F << 6)
  58. #define MII_ADDRMSK (0x1F << 11)
  59. struct eth_dma_regs {
  60. u32 busmode; /* 0x00 */
  61. u32 txpolldemand; /* 0x04 */
  62. u32 rxpolldemand; /* 0x08 */
  63. u32 rxdesclistaddr; /* 0x0c */
  64. u32 txdesclistaddr; /* 0x10 */
  65. u32 status; /* 0x14 */
  66. u32 opmode; /* 0x18 */
  67. u32 intenable; /* 0x1c */
  68. u32 reserved1[2];
  69. u32 axibus; /* 0x28 */
  70. u32 reserved2[7];
  71. u32 currhosttxdesc; /* 0x48 */
  72. u32 currhostrxdesc; /* 0x4c */
  73. u32 currhosttxbuffaddr; /* 0x50 */
  74. u32 currhostrxbuffaddr; /* 0x54 */
  75. };
  76. #define DW_DMA_BASE_OFFSET (0x1000)
  77. /* Default DMA Burst length */
  78. #ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
  79. #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
  80. #endif
  81. /* Bus mode register definitions */
  82. #define FIXEDBURST (1 << 16)
  83. #define PRIORXTX_41 (3 << 14)
  84. #define PRIORXTX_31 (2 << 14)
  85. #define PRIORXTX_21 (1 << 14)
  86. #define PRIORXTX_11 (0 << 14)
  87. #define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
  88. #define RXHIGHPRIO (1 << 1)
  89. #define DMAMAC_SRST (1 << 0)
  90. /* Poll demand definitions */
  91. #define POLL_DATA (0xFFFFFFFF)
  92. /* Operation mode definitions */
  93. #define STOREFORWARD (1 << 21)
  94. #define FLUSHTXFIFO (1 << 20)
  95. #define TXSTART (1 << 13)
  96. #define TXSECONDFRAME (1 << 2)
  97. #define RXSTART (1 << 1)
  98. /* Descriptior related definitions */
  99. #define MAC_MAX_FRAME_SZ (1600)
  100. struct dmamacdescr {
  101. u32 txrx_status;
  102. u32 dmamac_cntl;
  103. u32 dmamac_addr;
  104. u32 dmamac_next;
  105. } __aligned(ARCH_DMA_MINALIGN);
  106. /*
  107. * txrx_status definitions
  108. */
  109. /* tx status bits definitions */
  110. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  111. #define DESC_TXSTS_OWNBYDMA (1 << 31)
  112. #define DESC_TXSTS_TXINT (1 << 30)
  113. #define DESC_TXSTS_TXLAST (1 << 29)
  114. #define DESC_TXSTS_TXFIRST (1 << 28)
  115. #define DESC_TXSTS_TXCRCDIS (1 << 27)
  116. #define DESC_TXSTS_TXPADDIS (1 << 26)
  117. #define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
  118. #define DESC_TXSTS_TXRINGEND (1 << 21)
  119. #define DESC_TXSTS_TXCHAIN (1 << 20)
  120. #define DESC_TXSTS_MSK (0x1FFFF << 0)
  121. #else
  122. #define DESC_TXSTS_OWNBYDMA (1 << 31)
  123. #define DESC_TXSTS_MSK (0x1FFFF << 0)
  124. #endif
  125. /* rx status bits definitions */
  126. #define DESC_RXSTS_OWNBYDMA (1 << 31)
  127. #define DESC_RXSTS_DAFILTERFAIL (1 << 30)
  128. #define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
  129. #define DESC_RXSTS_FRMLENSHFT (16)
  130. #define DESC_RXSTS_ERROR (1 << 15)
  131. #define DESC_RXSTS_RXTRUNCATED (1 << 14)
  132. #define DESC_RXSTS_SAFILTERFAIL (1 << 13)
  133. #define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
  134. #define DESC_RXSTS_RXDAMAGED (1 << 11)
  135. #define DESC_RXSTS_RXVLANTAG (1 << 10)
  136. #define DESC_RXSTS_RXFIRST (1 << 9)
  137. #define DESC_RXSTS_RXLAST (1 << 8)
  138. #define DESC_RXSTS_RXIPC_GIANT (1 << 7)
  139. #define DESC_RXSTS_RXCOLLISION (1 << 6)
  140. #define DESC_RXSTS_RXFRAMEETHER (1 << 5)
  141. #define DESC_RXSTS_RXWATCHDOG (1 << 4)
  142. #define DESC_RXSTS_RXMIIERROR (1 << 3)
  143. #define DESC_RXSTS_RXDRIBBLING (1 << 2)
  144. #define DESC_RXSTS_RXCRC (1 << 1)
  145. /*
  146. * dmamac_cntl definitions
  147. */
  148. /* tx control bits definitions */
  149. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  150. #define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
  151. #define DESC_TXCTRL_SIZE1SHFT (0)
  152. #define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
  153. #define DESC_TXCTRL_SIZE2SHFT (16)
  154. #else
  155. #define DESC_TXCTRL_TXINT (1 << 31)
  156. #define DESC_TXCTRL_TXLAST (1 << 30)
  157. #define DESC_TXCTRL_TXFIRST (1 << 29)
  158. #define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
  159. #define DESC_TXCTRL_TXCRCDIS (1 << 26)
  160. #define DESC_TXCTRL_TXRINGEND (1 << 25)
  161. #define DESC_TXCTRL_TXCHAIN (1 << 24)
  162. #define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
  163. #define DESC_TXCTRL_SIZE1SHFT (0)
  164. #define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
  165. #define DESC_TXCTRL_SIZE2SHFT (11)
  166. #endif
  167. /* rx control bits definitions */
  168. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  169. #define DESC_RXCTRL_RXINTDIS (1 << 31)
  170. #define DESC_RXCTRL_RXRINGEND (1 << 15)
  171. #define DESC_RXCTRL_RXCHAIN (1 << 14)
  172. #define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
  173. #define DESC_RXCTRL_SIZE1SHFT (0)
  174. #define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
  175. #define DESC_RXCTRL_SIZE2SHFT (16)
  176. #else
  177. #define DESC_RXCTRL_RXINTDIS (1 << 31)
  178. #define DESC_RXCTRL_RXRINGEND (1 << 25)
  179. #define DESC_RXCTRL_RXCHAIN (1 << 24)
  180. #define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
  181. #define DESC_RXCTRL_SIZE1SHFT (0)
  182. #define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
  183. #define DESC_RXCTRL_SIZE2SHFT (11)
  184. #endif
  185. struct dw_eth_dev {
  186. struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
  187. struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
  188. char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  189. char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  190. u32 interface;
  191. u32 max_speed;
  192. u32 tx_currdescnum;
  193. u32 rx_currdescnum;
  194. struct eth_mac_regs *mac_regs_p;
  195. struct eth_dma_regs *dma_regs_p;
  196. #ifndef CONFIG_DM_ETH
  197. struct eth_device *dev;
  198. #endif
  199. #if CONFIG_IS_ENABLED(DM_GPIO)
  200. struct gpio_desc reset_gpio;
  201. #endif
  202. #ifdef CONFIG_CLK
  203. struct clk *clocks; /* clock list */
  204. int clock_count; /* number of clock in clock list */
  205. #endif
  206. struct phy_device *phydev;
  207. struct mii_dev *bus;
  208. };
  209. #ifdef CONFIG_DM_ETH
  210. int designware_eth_ofdata_to_platdata(struct udevice *dev);
  211. int designware_eth_probe(struct udevice *dev);
  212. extern const struct eth_ops designware_eth_ops;
  213. struct dw_eth_pdata {
  214. struct eth_pdata eth_pdata;
  215. u32 reset_delays[3];
  216. };
  217. int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
  218. int designware_eth_enable(struct dw_eth_dev *priv);
  219. int designware_eth_send(struct udevice *dev, void *packet, int length);
  220. int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
  221. int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
  222. int length);
  223. void designware_eth_stop(struct udevice *dev);
  224. int designware_eth_write_hwaddr(struct udevice *dev);
  225. #endif
  226. #endif