dc2114x.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <asm/io.h>
  4. #include <dm.h>
  5. #include <malloc.h>
  6. #include <net.h>
  7. #include <netdev.h>
  8. #include <pci.h>
  9. #include <linux/bitops.h>
  10. #include <linux/delay.h>
  11. #define SROM_DLEVEL 0
  12. /* PCI Registers. */
  13. #define PCI_CFDA_PSM 0x43
  14. #define CFRV_RN 0x000000f0 /* Revision Number */
  15. #define WAKEUP 0x00 /* Power Saving Wakeup */
  16. #define SLEEP 0x80 /* Power Saving Sleep Mode */
  17. #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
  18. /* Ethernet chip registers. */
  19. #define DE4X5_BMR 0x000 /* Bus Mode Register */
  20. #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
  21. #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
  22. #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
  23. #define DE4X5_STS 0x028 /* Status Register */
  24. #define DE4X5_OMR 0x030 /* Operation Mode Register */
  25. #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
  26. #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
  27. /* Register bits. */
  28. #define BMR_SWR 0x00000001 /* Software Reset */
  29. #define STS_TS 0x00700000 /* Transmit Process State */
  30. #define STS_RS 0x000e0000 /* Receive Process State */
  31. #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
  32. #define OMR_SR 0x00000002 /* Start/Stop Receive */
  33. #define OMR_PS 0x00040000 /* Port Select */
  34. #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
  35. #define OMR_PM 0x00000080 /* Pass All Multicast */
  36. /* Descriptor bits. */
  37. #define R_OWN 0x80000000 /* Own Bit */
  38. #define RD_RER 0x02000000 /* Receive End Of Ring */
  39. #define RD_LS 0x00000100 /* Last Descriptor */
  40. #define RD_ES 0x00008000 /* Error Summary */
  41. #define TD_TER 0x02000000 /* Transmit End Of Ring */
  42. #define T_OWN 0x80000000 /* Own Bit */
  43. #define TD_LS 0x40000000 /* Last Segment */
  44. #define TD_FS 0x20000000 /* First Segment */
  45. #define TD_ES 0x00008000 /* Error Summary */
  46. #define TD_SET 0x08000000 /* Setup Packet */
  47. /* The EEPROM commands include the alway-set leading bit. */
  48. #define SROM_WRITE_CMD 5
  49. #define SROM_READ_CMD 6
  50. #define SROM_ERASE_CMD 7
  51. #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
  52. #define SROM_RD 0x00004000 /* Read from Boot ROM */
  53. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  54. #define EE_WRITE_0 0x4801
  55. #define EE_WRITE_1 0x4805
  56. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  57. #define SROM_SR 0x00000800 /* Select Serial ROM when set */
  58. #define DT_IN 0x00000004 /* Serial Data In */
  59. #define DT_CLK 0x00000002 /* Serial ROM Clock */
  60. #define DT_CS 0x00000001 /* Serial ROM Chip Select */
  61. #define POLL_DEMAND 1
  62. #if defined(CONFIG_DM_ETH)
  63. #define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
  64. #elif defined(CONFIG_E500)
  65. #define phys_to_bus(dev, a) (a)
  66. #else
  67. #define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
  68. #endif
  69. #define NUM_RX_DESC PKTBUFSRX
  70. #define NUM_TX_DESC 1 /* Number of TX descriptors */
  71. #define RX_BUFF_SZ PKTSIZE_ALIGN
  72. #define TOUT_LOOP 1000000
  73. #define SETUP_FRAME_LEN 192
  74. struct de4x5_desc {
  75. volatile s32 status;
  76. u32 des1;
  77. u32 buf;
  78. u32 next;
  79. };
  80. struct dc2114x_priv {
  81. struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
  82. struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
  83. int rx_new; /* RX descriptor ring pointer */
  84. int tx_new; /* TX descriptor ring pointer */
  85. char rx_ring_size;
  86. char tx_ring_size;
  87. #ifdef CONFIG_DM_ETH
  88. struct udevice *devno;
  89. #else
  90. struct eth_device dev;
  91. pci_dev_t devno;
  92. #endif
  93. char *name;
  94. void __iomem *iobase;
  95. u8 *enetaddr;
  96. };
  97. /* RX and TX descriptor ring */
  98. static u32 dc2114x_inl(struct dc2114x_priv *priv, u32 addr)
  99. {
  100. return le32_to_cpu(readl(priv->iobase + addr));
  101. }
  102. static void dc2114x_outl(struct dc2114x_priv *priv, u32 command, u32 addr)
  103. {
  104. writel(cpu_to_le32(command), priv->iobase + addr);
  105. }
  106. static void reset_de4x5(struct dc2114x_priv *priv)
  107. {
  108. u32 i;
  109. i = dc2114x_inl(priv, DE4X5_BMR);
  110. mdelay(1);
  111. dc2114x_outl(priv, i | BMR_SWR, DE4X5_BMR);
  112. mdelay(1);
  113. dc2114x_outl(priv, i, DE4X5_BMR);
  114. mdelay(1);
  115. for (i = 0; i < 5; i++) {
  116. dc2114x_inl(priv, DE4X5_BMR);
  117. mdelay(10);
  118. }
  119. mdelay(1);
  120. }
  121. static void start_de4x5(struct dc2114x_priv *priv)
  122. {
  123. u32 omr;
  124. omr = dc2114x_inl(priv, DE4X5_OMR);
  125. omr |= OMR_ST | OMR_SR;
  126. dc2114x_outl(priv, omr, DE4X5_OMR); /* Enable the TX and/or RX */
  127. }
  128. static void stop_de4x5(struct dc2114x_priv *priv)
  129. {
  130. u32 omr;
  131. omr = dc2114x_inl(priv, DE4X5_OMR);
  132. omr &= ~(OMR_ST | OMR_SR);
  133. dc2114x_outl(priv, omr, DE4X5_OMR); /* Disable the TX and/or RX */
  134. }
  135. /* SROM Read and write routines. */
  136. static void sendto_srom(struct dc2114x_priv *priv, u_int command, u_long addr)
  137. {
  138. dc2114x_outl(priv, command, addr);
  139. udelay(1);
  140. }
  141. static int getfrom_srom(struct dc2114x_priv *priv, u_long addr)
  142. {
  143. u32 tmp = dc2114x_inl(priv, addr);
  144. udelay(1);
  145. return tmp;
  146. }
  147. /* Note: this routine returns extra data bits for size detection. */
  148. static int do_read_eeprom(struct dc2114x_priv *priv, u_long ioaddr, int location,
  149. int addr_len)
  150. {
  151. int read_cmd = location | (SROM_READ_CMD << addr_len);
  152. unsigned int retval = 0;
  153. int i;
  154. sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
  155. sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
  156. debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
  157. /* Shift the read command bits out. */
  158. for (i = 4 + addr_len; i >= 0; i--) {
  159. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  160. sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | dataval,
  161. ioaddr);
  162. udelay(10);
  163. sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
  164. ioaddr);
  165. udelay(10);
  166. debug_cond(SROM_DLEVEL >= 2, "%X",
  167. getfrom_srom(priv, ioaddr) & 15);
  168. retval = (retval << 1) |
  169. !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
  170. }
  171. sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
  172. debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(priv, ioaddr) & 15);
  173. for (i = 16; i > 0; i--) {
  174. sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
  175. udelay(10);
  176. debug_cond(SROM_DLEVEL >= 2, "%X",
  177. getfrom_srom(priv, ioaddr) & 15);
  178. retval = (retval << 1) |
  179. !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
  180. sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
  181. udelay(10);
  182. }
  183. /* Terminate the EEPROM access. */
  184. sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
  185. debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
  186. location, retval);
  187. return retval;
  188. }
  189. /*
  190. * This executes a generic EEPROM command, typically a write or write
  191. * enable. It returns the data output from the EEPROM, and thus may
  192. * also be used for reads.
  193. */
  194. static int do_eeprom_cmd(struct dc2114x_priv *priv, u_long ioaddr, int cmd,
  195. int cmd_len)
  196. {
  197. unsigned int retval = 0;
  198. debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
  199. sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
  200. /* Shift the command bits out. */
  201. do {
  202. short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
  203. sendto_srom(priv, dataval, ioaddr);
  204. udelay(10);
  205. debug_cond(SROM_DLEVEL >= 2, "%X",
  206. getfrom_srom(priv, ioaddr) & 15);
  207. sendto_srom(priv, dataval | DT_CLK, ioaddr);
  208. udelay(10);
  209. retval = (retval << 1) |
  210. !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
  211. } while (--cmd_len >= 0);
  212. sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
  213. /* Terminate the EEPROM access. */
  214. sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
  215. debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
  216. return retval;
  217. }
  218. static int read_srom(struct dc2114x_priv *priv, u_long ioaddr, int index)
  219. {
  220. int ee_addr_size;
  221. ee_addr_size = (do_read_eeprom(priv, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
  222. return do_eeprom_cmd(priv, ioaddr, 0xffff |
  223. (((SROM_READ_CMD << ee_addr_size) | index) << 16),
  224. 3 + ee_addr_size + 16);
  225. }
  226. static void send_setup_frame(struct dc2114x_priv *priv)
  227. {
  228. char setup_frame[SETUP_FRAME_LEN];
  229. char *pa = &setup_frame[0];
  230. int i;
  231. memset(pa, 0xff, SETUP_FRAME_LEN);
  232. for (i = 0; i < ETH_ALEN; i++) {
  233. *(pa + (i & 1)) = priv->enetaddr[i];
  234. if (i & 0x01)
  235. pa += 4;
  236. }
  237. for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
  238. if (i < TOUT_LOOP)
  239. continue;
  240. printf("%s: tx error buffer not ready\n", priv->name);
  241. return;
  242. }
  243. priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
  244. (u32)&setup_frame[0]));
  245. priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
  246. priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
  247. dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
  248. for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
  249. if (i < TOUT_LOOP)
  250. continue;
  251. printf("%s: tx buffer not ready\n", priv->name);
  252. return;
  253. }
  254. if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) != 0x7FFFFFFF) {
  255. printf("TX error status2 = 0x%08X\n",
  256. le32_to_cpu(priv->tx_ring[priv->tx_new].status));
  257. }
  258. priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
  259. }
  260. static int dc21x4x_send_common(struct dc2114x_priv *priv, void *packet, int length)
  261. {
  262. int status = -1;
  263. int i;
  264. if (length <= 0) {
  265. printf("%s: bad packet size: %d\n", priv->name, length);
  266. goto done;
  267. }
  268. for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
  269. if (i < TOUT_LOOP)
  270. continue;
  271. printf("%s: tx error buffer not ready\n", priv->name);
  272. goto done;
  273. }
  274. priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
  275. (u32)packet));
  276. priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
  277. priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
  278. dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
  279. for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
  280. if (i < TOUT_LOOP)
  281. continue;
  282. printf(".%s: tx buffer not ready\n", priv->name);
  283. goto done;
  284. }
  285. if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) & TD_ES) {
  286. priv->tx_ring[priv->tx_new].status = 0x0;
  287. goto done;
  288. }
  289. status = length;
  290. done:
  291. priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
  292. return status;
  293. }
  294. static int dc21x4x_recv_check(struct dc2114x_priv *priv)
  295. {
  296. int length = 0;
  297. u32 status;
  298. status = le32_to_cpu(priv->rx_ring[priv->rx_new].status);
  299. if (status & R_OWN)
  300. return 0;
  301. if (status & RD_LS) {
  302. /* Valid frame status. */
  303. if (status & RD_ES) {
  304. /* There was an error. */
  305. printf("RX error status = 0x%08X\n", status);
  306. return -EINVAL;
  307. } else {
  308. /* A valid frame received. */
  309. length = (le32_to_cpu(priv->rx_ring[priv->rx_new].status)
  310. >> 16);
  311. return length;
  312. }
  313. }
  314. return -EAGAIN;
  315. }
  316. static int dc21x4x_init_common(struct dc2114x_priv *priv)
  317. {
  318. int i;
  319. reset_de4x5(priv);
  320. if (dc2114x_inl(priv, DE4X5_STS) & (STS_TS | STS_RS)) {
  321. printf("Error: Cannot reset ethernet controller.\n");
  322. return -1;
  323. }
  324. dc2114x_outl(priv, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
  325. for (i = 0; i < NUM_RX_DESC; i++) {
  326. priv->rx_ring[i].status = cpu_to_le32(R_OWN);
  327. priv->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
  328. priv->rx_ring[i].buf = cpu_to_le32(phys_to_bus(priv->devno,
  329. (u32)net_rx_packets[i]));
  330. priv->rx_ring[i].next = 0;
  331. }
  332. for (i = 0; i < NUM_TX_DESC; i++) {
  333. priv->tx_ring[i].status = 0;
  334. priv->tx_ring[i].des1 = 0;
  335. priv->tx_ring[i].buf = 0;
  336. priv->tx_ring[i].next = 0;
  337. }
  338. priv->rx_ring_size = NUM_RX_DESC;
  339. priv->tx_ring_size = NUM_TX_DESC;
  340. /* Write the end of list marker to the descriptor lists. */
  341. priv->rx_ring[priv->rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
  342. priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
  343. /* Tell the adapter where the TX/RX rings are located. */
  344. dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->rx_ring),
  345. DE4X5_RRBA);
  346. dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->tx_ring),
  347. DE4X5_TRBA);
  348. start_de4x5(priv);
  349. priv->tx_new = 0;
  350. priv->rx_new = 0;
  351. send_setup_frame(priv);
  352. return 0;
  353. }
  354. static void dc21x4x_halt_common(struct dc2114x_priv *priv)
  355. {
  356. stop_de4x5(priv);
  357. dc2114x_outl(priv, 0, DE4X5_SICR);
  358. }
  359. static void read_hw_addr(struct dc2114x_priv *priv)
  360. {
  361. u_short tmp, *p = (u_short *)(&priv->enetaddr[0]);
  362. int i, j = 0;
  363. for (i = 0; i < (ETH_ALEN >> 1); i++) {
  364. tmp = read_srom(priv, DE4X5_APROM, (SROM_HWADD >> 1) + i);
  365. *p = le16_to_cpu(tmp);
  366. j += *p++;
  367. }
  368. if (!j || j == 0x2fffd) {
  369. memset(priv->enetaddr, 0, ETH_ALEN);
  370. debug("Warning: can't read HW address from SROM.\n");
  371. }
  372. }
  373. static struct pci_device_id supported[] = {
  374. { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST) },
  375. { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142) },
  376. { }
  377. };
  378. #ifndef CONFIG_DM_ETH
  379. static int dc21x4x_init(struct eth_device *dev, struct bd_info *bis)
  380. {
  381. struct dc2114x_priv *priv =
  382. container_of(dev, struct dc2114x_priv, dev);
  383. /* Ensure we're not sleeping. */
  384. pci_write_config_byte(priv->devno, PCI_CFDA_PSM, WAKEUP);
  385. return dc21x4x_init_common(priv);
  386. }
  387. static void dc21x4x_halt(struct eth_device *dev)
  388. {
  389. struct dc2114x_priv *priv =
  390. container_of(dev, struct dc2114x_priv, dev);
  391. dc21x4x_halt_common(priv);
  392. pci_write_config_byte(priv->devno, PCI_CFDA_PSM, SLEEP);
  393. }
  394. static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
  395. {
  396. struct dc2114x_priv *priv =
  397. container_of(dev, struct dc2114x_priv, dev);
  398. return dc21x4x_send_common(priv, packet, length);
  399. }
  400. static int dc21x4x_recv(struct eth_device *dev)
  401. {
  402. struct dc2114x_priv *priv =
  403. container_of(dev, struct dc2114x_priv, dev);
  404. int length = 0;
  405. int ret;
  406. while (true) {
  407. ret = dc21x4x_recv_check(priv);
  408. if (!ret)
  409. break;
  410. if (ret > 0) {
  411. length = ret;
  412. /* Pass the packet up to the protocol layers */
  413. net_process_received_packet
  414. (net_rx_packets[priv->rx_new], length - 4);
  415. }
  416. /*
  417. * Change buffer ownership for this frame,
  418. * back to the adapter.
  419. */
  420. if (ret != -EAGAIN)
  421. priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN);
  422. /* Update entry information. */
  423. priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
  424. }
  425. return length;
  426. }
  427. int dc21x4x_initialize(struct bd_info *bis)
  428. {
  429. struct dc2114x_priv *priv;
  430. struct eth_device *dev;
  431. unsigned short status;
  432. unsigned char timer;
  433. unsigned int iobase;
  434. int card_number = 0;
  435. pci_dev_t devbusfn;
  436. int idx = 0;
  437. while (1) {
  438. devbusfn = pci_find_devices(supported, idx++);
  439. if (devbusfn == -1)
  440. break;
  441. pci_read_config_word(devbusfn, PCI_COMMAND, &status);
  442. status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  443. pci_write_config_word(devbusfn, PCI_COMMAND, status);
  444. pci_read_config_word(devbusfn, PCI_COMMAND, &status);
  445. if (!(status & PCI_COMMAND_MEMORY)) {
  446. printf("Error: Can not enable MEMORY access.\n");
  447. continue;
  448. }
  449. if (!(status & PCI_COMMAND_MASTER)) {
  450. printf("Error: Can not enable Bus Mastering.\n");
  451. continue;
  452. }
  453. /* Check the latency timer for values >= 0x60. */
  454. pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
  455. if (timer < 0x60) {
  456. pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
  457. 0x60);
  458. }
  459. /* read BAR for memory space access */
  460. pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
  461. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  462. debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
  463. priv = memalign(32, sizeof(*priv));
  464. if (!priv) {
  465. printf("Can not allocalte memory of dc21x4x\n");
  466. break;
  467. }
  468. memset(priv, 0, sizeof(*priv));
  469. dev = &priv->dev;
  470. sprintf(dev->name, "dc21x4x#%d", card_number);
  471. priv->devno = devbusfn;
  472. priv->name = dev->name;
  473. priv->enetaddr = dev->enetaddr;
  474. dev->iobase = pci_mem_to_phys(devbusfn, iobase);
  475. dev->priv = (void *)devbusfn;
  476. dev->init = dc21x4x_init;
  477. dev->halt = dc21x4x_halt;
  478. dev->send = dc21x4x_send;
  479. dev->recv = dc21x4x_recv;
  480. /* Ensure we're not sleeping. */
  481. pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
  482. udelay(10 * 1000);
  483. read_hw_addr(priv);
  484. eth_register(dev);
  485. card_number++;
  486. }
  487. return card_number;
  488. }
  489. #else /* DM_ETH */
  490. static int dc2114x_start(struct udevice *dev)
  491. {
  492. struct eth_pdata *plat = dev_get_platdata(dev);
  493. struct dc2114x_priv *priv = dev_get_priv(dev);
  494. memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
  495. /* Ensure we're not sleeping. */
  496. dm_pci_write_config8(dev, PCI_CFDA_PSM, WAKEUP);
  497. return dc21x4x_init_common(priv);
  498. }
  499. static void dc2114x_stop(struct udevice *dev)
  500. {
  501. struct dc2114x_priv *priv = dev_get_priv(dev);
  502. dc21x4x_halt_common(priv);
  503. dm_pci_write_config8(dev, PCI_CFDA_PSM, SLEEP);
  504. }
  505. static int dc2114x_send(struct udevice *dev, void *packet, int length)
  506. {
  507. struct dc2114x_priv *priv = dev_get_priv(dev);
  508. int ret;
  509. ret = dc21x4x_send_common(priv, packet, length);
  510. return ret ? 0 : -ETIMEDOUT;
  511. }
  512. static int dc2114x_recv(struct udevice *dev, int flags, uchar **packetp)
  513. {
  514. struct dc2114x_priv *priv = dev_get_priv(dev);
  515. int ret;
  516. ret = dc21x4x_recv_check(priv);
  517. if (ret < 0) {
  518. /* Update entry information. */
  519. priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
  520. ret = 0;
  521. }
  522. if (!ret)
  523. return 0;
  524. *packetp = net_rx_packets[priv->rx_new];
  525. return ret - 4;
  526. }
  527. static int dc2114x_free_pkt(struct udevice *dev, uchar *packet, int length)
  528. {
  529. struct dc2114x_priv *priv = dev_get_priv(dev);
  530. priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN);
  531. /* Update entry information. */
  532. priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
  533. return 0;
  534. }
  535. static int dc2114x_read_rom_hwaddr(struct udevice *dev)
  536. {
  537. struct dc2114x_priv *priv = dev_get_priv(dev);
  538. read_hw_addr(priv);
  539. return 0;
  540. }
  541. static int dc2114x_bind(struct udevice *dev)
  542. {
  543. static int card_number;
  544. char name[16];
  545. sprintf(name, "dc2114x#%u", card_number++);
  546. return device_set_name(dev, name);
  547. }
  548. static int dc2114x_probe(struct udevice *dev)
  549. {
  550. struct eth_pdata *plat = dev_get_platdata(dev);
  551. struct dc2114x_priv *priv = dev_get_priv(dev);
  552. u16 command, status;
  553. u32 iobase;
  554. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
  555. iobase &= ~0xf;
  556. debug("dc2114x: DEC 2114x PCI Device @0x%x\n", iobase);
  557. priv->devno = dev;
  558. priv->enetaddr = plat->enetaddr;
  559. priv->iobase = (void __iomem *)dm_pci_mem_to_phys(dev, iobase);
  560. command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  561. dm_pci_write_config16(dev, PCI_COMMAND, command);
  562. dm_pci_read_config16(dev, PCI_COMMAND, &status);
  563. if ((status & command) != command) {
  564. printf("dc2114x: Couldn't enable IO access or Bus Mastering\n");
  565. return -EINVAL;
  566. }
  567. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x60);
  568. return 0;
  569. }
  570. static const struct eth_ops dc2114x_ops = {
  571. .start = dc2114x_start,
  572. .send = dc2114x_send,
  573. .recv = dc2114x_recv,
  574. .stop = dc2114x_stop,
  575. .free_pkt = dc2114x_free_pkt,
  576. .read_rom_hwaddr = dc2114x_read_rom_hwaddr,
  577. };
  578. U_BOOT_DRIVER(eth_dc2114x) = {
  579. .name = "eth_dc2114x",
  580. .id = UCLASS_ETH,
  581. .bind = dc2114x_bind,
  582. .probe = dc2114x_probe,
  583. .ops = &dc2114x_ops,
  584. .priv_auto_alloc_size = sizeof(struct dc2114x_priv),
  585. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  586. };
  587. U_BOOT_PCI_DEVICE(eth_dc2114x, supported);
  588. #endif