cs8900.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Cirrus Logic CS8900A Ethernet
  4. *
  5. * (C) 2009 Ben Warren , biggerbadderben@gmail.com
  6. * Converted to use CONFIG_NET_MULTI API
  7. *
  8. * (C) 2003 Wolfgang Denk, wd@denx.de
  9. * Extension to synchronize ethaddr environment variable
  10. * against value in EEPROM
  11. *
  12. * (C) Copyright 2002
  13. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  14. * Marius Groeger <mgroeger@sysgo.de>
  15. *
  16. * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
  17. *
  18. * This program is loaded into SRAM in bootstrap mode, where it waits
  19. * for commands on UART1 to read and write memory, jump to code etc.
  20. * A design goal for this program is to be entirely independent of the
  21. * target board. Anything with a CL-PS7111 or EP7211 should be able to run
  22. * this code in bootstrap mode. All the board specifics can be handled on
  23. * the host.
  24. */
  25. #include <common.h>
  26. #include <command.h>
  27. #include <log.h>
  28. #include <asm/io.h>
  29. #include <net.h>
  30. #include <malloc.h>
  31. #include <linux/delay.h>
  32. #include "cs8900.h"
  33. #undef DEBUG
  34. /* packet page register access functions */
  35. #ifdef CONFIG_CS8900_BUS32
  36. #define REG_WRITE(v, a) writel((v),(a))
  37. #define REG_READ(a) readl((a))
  38. /* we don't need 16 bit initialisation on 32 bit bus */
  39. #define get_reg_init_bus(r,d) get_reg((r),(d))
  40. #else
  41. #define REG_WRITE(v, a) writew((v),(a))
  42. #define REG_READ(a) readw((a))
  43. static u16 get_reg_init_bus(struct eth_device *dev, int regno)
  44. {
  45. /* force 16 bit busmode */
  46. struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
  47. uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
  48. readb(iob);
  49. readb(iob + 1);
  50. readb(iob);
  51. readb(iob + 1);
  52. readb(iob);
  53. REG_WRITE(regno, &priv->regs->pptr);
  54. return REG_READ(&priv->regs->pdata);
  55. }
  56. #endif
  57. static u16 get_reg(struct eth_device *dev, int regno)
  58. {
  59. struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
  60. REG_WRITE(regno, &priv->regs->pptr);
  61. return REG_READ(&priv->regs->pdata);
  62. }
  63. static void put_reg(struct eth_device *dev, int regno, u16 val)
  64. {
  65. struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
  66. REG_WRITE(regno, &priv->regs->pptr);
  67. REG_WRITE(val, &priv->regs->pdata);
  68. }
  69. static void cs8900_reset(struct eth_device *dev)
  70. {
  71. int tmo;
  72. u16 us;
  73. /* reset NIC */
  74. put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
  75. /* wait for 200ms */
  76. udelay(200000);
  77. /* Wait until the chip is reset */
  78. tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
  79. while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
  80. PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
  81. /*NOP*/;
  82. }
  83. static void cs8900_reginit(struct eth_device *dev)
  84. {
  85. /* receive only error free packets addressed to this card */
  86. put_reg(dev, PP_RxCTL,
  87. PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
  88. /* do not generate any interrupts on receive operations */
  89. put_reg(dev, PP_RxCFG, 0);
  90. /* do not generate any interrupts on transmit operations */
  91. put_reg(dev, PP_TxCFG, 0);
  92. /* do not generate any interrupts on buffer operations */
  93. put_reg(dev, PP_BufCFG, 0);
  94. /* enable transmitter/receiver mode */
  95. put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
  96. }
  97. void cs8900_get_enetaddr(struct eth_device *dev)
  98. {
  99. int i;
  100. /* verify chip id */
  101. if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
  102. return;
  103. cs8900_reset(dev);
  104. if ((get_reg(dev, PP_SelfSTAT) &
  105. (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
  106. (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
  107. /* Load the MAC from EEPROM */
  108. for (i = 0; i < 3; i++) {
  109. u32 Addr;
  110. Addr = get_reg(dev, PP_IA + i * 2);
  111. dev->enetaddr[i * 2] = Addr & 0xFF;
  112. dev->enetaddr[i * 2 + 1] = Addr >> 8;
  113. }
  114. }
  115. }
  116. void cs8900_halt(struct eth_device *dev)
  117. {
  118. /* disable transmitter/receiver mode */
  119. put_reg(dev, PP_LineCTL, 0);
  120. /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
  121. get_reg_init_bus(dev, PP_ChipID);
  122. }
  123. static int cs8900_init(struct eth_device *dev, struct bd_info * bd)
  124. {
  125. uchar *enetaddr = dev->enetaddr;
  126. u16 id;
  127. /* verify chip id */
  128. id = get_reg_init_bus(dev, PP_ChipID);
  129. if (id != 0x630e) {
  130. printf ("CS8900 Ethernet chip not found: "
  131. "ID=0x%04x instead 0x%04x\n", id, 0x630e);
  132. return 1;
  133. }
  134. cs8900_reset (dev);
  135. /* set the ethernet address */
  136. put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
  137. put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
  138. put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
  139. cs8900_reginit(dev);
  140. return 0;
  141. }
  142. /* Get a data block via Ethernet */
  143. static int cs8900_recv(struct eth_device *dev)
  144. {
  145. int i;
  146. u16 rxlen;
  147. u16 *addr;
  148. u16 status;
  149. struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
  150. status = get_reg(dev, PP_RER);
  151. if ((status & PP_RER_RxOK) == 0)
  152. return 0;
  153. status = REG_READ(&priv->regs->rtdata);
  154. rxlen = REG_READ(&priv->regs->rtdata);
  155. if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
  156. debug("packet too big!\n");
  157. for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--)
  158. *addr++ = REG_READ(&priv->regs->rtdata);
  159. if (rxlen & 1)
  160. *addr++ = REG_READ(&priv->regs->rtdata);
  161. /* Pass the packet up to the protocol layers. */
  162. net_process_received_packet(net_rx_packets[0], rxlen);
  163. return rxlen;
  164. }
  165. /* Send a data block via Ethernet. */
  166. static int cs8900_send(struct eth_device *dev, void *packet, int length)
  167. {
  168. volatile u16 *addr;
  169. int tmo;
  170. u16 s;
  171. struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
  172. retry:
  173. /* initiate a transmit sequence */
  174. REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
  175. REG_WRITE(length, &priv->regs->txlen);
  176. /* Test to see if the chip has allocated memory for the packet */
  177. if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
  178. /* Oops... this should not happen! */
  179. debug("cs: unable to send packet; retrying...\n");
  180. for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
  181. get_timer(0) < tmo;)
  182. /*NOP*/;
  183. cs8900_reset(dev);
  184. cs8900_reginit(dev);
  185. goto retry;
  186. }
  187. /* Write the contents of the packet */
  188. /* assume even number of bytes */
  189. for (addr = packet; length > 0; length -= 2)
  190. REG_WRITE(*addr++, &priv->regs->rtdata);
  191. /* wait for transfer to succeed */
  192. tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
  193. while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
  194. if (get_timer(0) >= tmo)
  195. break;
  196. }
  197. /* nothing */ ;
  198. if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
  199. debug("\ntransmission error %#x\n", s);
  200. }
  201. return 0;
  202. }
  203. static void cs8900_e2prom_ready(struct eth_device *dev)
  204. {
  205. while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
  206. ;
  207. }
  208. /***********************************************************/
  209. /* read a 16-bit word out of the EEPROM */
  210. /***********************************************************/
  211. int cs8900_e2prom_read(struct eth_device *dev,
  212. u8 addr, u16 *value)
  213. {
  214. cs8900_e2prom_ready(dev);
  215. put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
  216. cs8900_e2prom_ready(dev);
  217. *value = get_reg(dev, PP_EEData);
  218. return 0;
  219. }
  220. /***********************************************************/
  221. /* write a 16-bit word into the EEPROM */
  222. /***********************************************************/
  223. int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
  224. {
  225. cs8900_e2prom_ready(dev);
  226. put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
  227. cs8900_e2prom_ready(dev);
  228. put_reg(dev, PP_EEData, value);
  229. put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
  230. cs8900_e2prom_ready(dev);
  231. put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
  232. cs8900_e2prom_ready(dev);
  233. return 0;
  234. }
  235. int cs8900_initialize(u8 dev_num, int base_addr)
  236. {
  237. struct eth_device *dev;
  238. struct cs8900_priv *priv;
  239. dev = malloc(sizeof(*dev));
  240. if (!dev) {
  241. return 0;
  242. }
  243. memset(dev, 0, sizeof(*dev));
  244. priv = malloc(sizeof(*priv));
  245. if (!priv) {
  246. free(dev);
  247. return 0;
  248. }
  249. memset(priv, 0, sizeof(*priv));
  250. priv->regs = (struct cs8900_regs *)base_addr;
  251. dev->iobase = base_addr;
  252. dev->priv = priv;
  253. dev->init = cs8900_init;
  254. dev->halt = cs8900_halt;
  255. dev->send = cs8900_send;
  256. dev->recv = cs8900_recv;
  257. /* Load MAC address from EEPROM */
  258. cs8900_get_enetaddr(dev);
  259. sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
  260. eth_register(dev);
  261. return 0;
  262. }