calxedaxgmac.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Calxeda, Inc.
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <net.h>
  8. #include <linux/compiler.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <asm/io.h>
  12. #define TX_NUM_DESC 1
  13. #define RX_NUM_DESC 32
  14. #define MAC_TIMEOUT (5*CONFIG_SYS_HZ)
  15. #define ETH_BUF_SZ 2048
  16. #define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
  17. #define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
  18. #define RXSTART 0x00000002
  19. #define TXSTART 0x00002000
  20. #define RXENABLE 0x00000004
  21. #define TXENABLE 0x00000008
  22. #define XGMAC_CONTROL_SPD 0x40000000
  23. #define XGMAC_CONTROL_SPD_MASK 0x60000000
  24. #define XGMAC_CONTROL_SARC 0x10000000
  25. #define XGMAC_CONTROL_SARK_MASK 0x18000000
  26. #define XGMAC_CONTROL_CAR 0x04000000
  27. #define XGMAC_CONTROL_CAR_MASK 0x06000000
  28. #define XGMAC_CONTROL_CAR_SHIFT 25
  29. #define XGMAC_CONTROL_DP 0x01000000
  30. #define XGMAC_CONTROL_WD 0x00800000
  31. #define XGMAC_CONTROL_JD 0x00400000
  32. #define XGMAC_CONTROL_JE 0x00100000
  33. #define XGMAC_CONTROL_LM 0x00001000
  34. #define XGMAC_CONTROL_IPC 0x00000400
  35. #define XGMAC_CONTROL_ACS 0x00000080
  36. #define XGMAC_CONTROL_DDIC 0x00000010
  37. #define XGMAC_CONTROL_TE 0x00000008
  38. #define XGMAC_CONTROL_RE 0x00000004
  39. #define XGMAC_DMA_BUSMODE_RESET 0x00000001
  40. #define XGMAC_DMA_BUSMODE_DSL 0x00000004
  41. #define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c
  42. #define XGMAC_DMA_BUSMODE_DSL_SHIFT 2
  43. #define XGMAC_DMA_BUSMODE_ATDS 0x00000080
  44. #define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00
  45. #define XGMAC_DMA_BUSMODE_PBL_SHIFT 8
  46. #define XGMAC_DMA_BUSMODE_FB 0x00010000
  47. #define XGMAC_DMA_BUSMODE_USP 0x00800000
  48. #define XGMAC_DMA_BUSMODE_8PBL 0x01000000
  49. #define XGMAC_DMA_BUSMODE_AAL 0x02000000
  50. #define XGMAC_DMA_AXIMODE_ENLPI 0x80000000
  51. #define XGMAC_DMA_AXIMODE_MGK 0x40000000
  52. #define XGMAC_DMA_AXIMODE_WROSR 0x00100000
  53. #define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000
  54. #define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20
  55. #define XGMAC_DMA_AXIMODE_RDOSR 0x00010000
  56. #define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000
  57. #define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16
  58. #define XGMAC_DMA_AXIMODE_AAL 0x00001000
  59. #define XGMAC_DMA_AXIMODE_BLEN256 0x00000080
  60. #define XGMAC_DMA_AXIMODE_BLEN128 0x00000040
  61. #define XGMAC_DMA_AXIMODE_BLEN64 0x00000020
  62. #define XGMAC_DMA_AXIMODE_BLEN32 0x00000010
  63. #define XGMAC_DMA_AXIMODE_BLEN16 0x00000008
  64. #define XGMAC_DMA_AXIMODE_BLEN8 0x00000004
  65. #define XGMAC_DMA_AXIMODE_BLEN4 0x00000002
  66. #define XGMAC_DMA_AXIMODE_UNDEF 0x00000001
  67. #define XGMAC_CORE_OMR_RTC_SHIFT 3
  68. #define XGMAC_CORE_OMR_RTC_MASK 0x00000018
  69. #define XGMAC_CORE_OMR_RTC 0x00000010
  70. #define XGMAC_CORE_OMR_RSF 0x00000020
  71. #define XGMAC_CORE_OMR_DT 0x00000040
  72. #define XGMAC_CORE_OMR_FEF 0x00000080
  73. #define XGMAC_CORE_OMR_EFC 0x00000100
  74. #define XGMAC_CORE_OMR_RFA_SHIFT 9
  75. #define XGMAC_CORE_OMR_RFA_MASK 0x00000E00
  76. #define XGMAC_CORE_OMR_RFD_SHIFT 12
  77. #define XGMAC_CORE_OMR_RFD_MASK 0x00007000
  78. #define XGMAC_CORE_OMR_TTC_SHIFT 16
  79. #define XGMAC_CORE_OMR_TTC_MASK 0x00030000
  80. #define XGMAC_CORE_OMR_TTC 0x00020000
  81. #define XGMAC_CORE_OMR_FTF 0x00100000
  82. #define XGMAC_CORE_OMR_TSF 0x00200000
  83. #define FIFO_MINUS_1K 0x0
  84. #define FIFO_MINUS_2K 0x1
  85. #define FIFO_MINUS_3K 0x2
  86. #define FIFO_MINUS_4K 0x3
  87. #define FIFO_MINUS_6K 0x4
  88. #define FIFO_MINUS_8K 0x5
  89. #define FIFO_MINUS_12K 0x6
  90. #define FIFO_MINUS_16K 0x7
  91. #define XGMAC_CORE_FLOW_PT_SHIFT 16
  92. #define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000
  93. #define XGMAC_CORE_FLOW_PT 0x00010000
  94. #define XGMAC_CORE_FLOW_DZQP 0x00000080
  95. #define XGMAC_CORE_FLOW_PLT_SHIFT 4
  96. #define XGMAC_CORE_FLOW_PLT_MASK 0x00000030
  97. #define XGMAC_CORE_FLOW_PLT 0x00000010
  98. #define XGMAC_CORE_FLOW_UP 0x00000008
  99. #define XGMAC_CORE_FLOW_RFE 0x00000004
  100. #define XGMAC_CORE_FLOW_TFE 0x00000002
  101. #define XGMAC_CORE_FLOW_FCB 0x00000001
  102. /* XGMAC Descriptor Defines */
  103. #define MAX_DESC_BUF_SZ (0x2000 - 8)
  104. #define RXDESC_EXT_STATUS 0x00000001
  105. #define RXDESC_CRC_ERR 0x00000002
  106. #define RXDESC_RX_ERR 0x00000008
  107. #define RXDESC_RX_WDOG 0x00000010
  108. #define RXDESC_FRAME_TYPE 0x00000020
  109. #define RXDESC_GIANT_FRAME 0x00000080
  110. #define RXDESC_LAST_SEG 0x00000100
  111. #define RXDESC_FIRST_SEG 0x00000200
  112. #define RXDESC_VLAN_FRAME 0x00000400
  113. #define RXDESC_OVERFLOW_ERR 0x00000800
  114. #define RXDESC_LENGTH_ERR 0x00001000
  115. #define RXDESC_SA_FILTER_FAIL 0x00002000
  116. #define RXDESC_DESCRIPTOR_ERR 0x00004000
  117. #define RXDESC_ERROR_SUMMARY 0x00008000
  118. #define RXDESC_FRAME_LEN_OFFSET 16
  119. #define RXDESC_FRAME_LEN_MASK 0x3fff0000
  120. #define RXDESC_DA_FILTER_FAIL 0x40000000
  121. #define RXDESC1_END_RING 0x00008000
  122. #define RXDESC_IP_PAYLOAD_MASK 0x00000003
  123. #define RXDESC_IP_PAYLOAD_UDP 0x00000001
  124. #define RXDESC_IP_PAYLOAD_TCP 0x00000002
  125. #define RXDESC_IP_PAYLOAD_ICMP 0x00000003
  126. #define RXDESC_IP_HEADER_ERR 0x00000008
  127. #define RXDESC_IP_PAYLOAD_ERR 0x00000010
  128. #define RXDESC_IPV4_PACKET 0x00000040
  129. #define RXDESC_IPV6_PACKET 0x00000080
  130. #define TXDESC_UNDERFLOW_ERR 0x00000001
  131. #define TXDESC_JABBER_TIMEOUT 0x00000002
  132. #define TXDESC_LOCAL_FAULT 0x00000004
  133. #define TXDESC_REMOTE_FAULT 0x00000008
  134. #define TXDESC_VLAN_FRAME 0x00000010
  135. #define TXDESC_FRAME_FLUSHED 0x00000020
  136. #define TXDESC_IP_HEADER_ERR 0x00000040
  137. #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
  138. #define TXDESC_ERROR_SUMMARY 0x00008000
  139. #define TXDESC_SA_CTRL_INSERT 0x00040000
  140. #define TXDESC_SA_CTRL_REPLACE 0x00080000
  141. #define TXDESC_2ND_ADDR_CHAINED 0x00100000
  142. #define TXDESC_END_RING 0x00200000
  143. #define TXDESC_CSUM_IP 0x00400000
  144. #define TXDESC_CSUM_IP_PAYLD 0x00800000
  145. #define TXDESC_CSUM_ALL 0x00C00000
  146. #define TXDESC_CRC_EN_REPLACE 0x01000000
  147. #define TXDESC_CRC_EN_APPEND 0x02000000
  148. #define TXDESC_DISABLE_PAD 0x04000000
  149. #define TXDESC_FIRST_SEG 0x10000000
  150. #define TXDESC_LAST_SEG 0x20000000
  151. #define TXDESC_INTERRUPT 0x40000000
  152. #define DESC_OWN 0x80000000
  153. #define DESC_BUFFER1_SZ_MASK 0x00001fff
  154. #define DESC_BUFFER2_SZ_MASK 0x1fff0000
  155. #define DESC_BUFFER2_SZ_OFFSET 16
  156. struct xgmac_regs {
  157. u32 config;
  158. u32 framefilter;
  159. u32 resv_1[4];
  160. u32 flow_control;
  161. u32 vlantag;
  162. u32 version;
  163. u32 vlaninclude;
  164. u32 resv_2[2];
  165. u32 pacestretch;
  166. u32 vlanhash;
  167. u32 resv_3;
  168. u32 intreg;
  169. struct {
  170. u32 hi; /* 0x40 */
  171. u32 lo; /* 0x44 */
  172. } macaddr[16];
  173. u32 resv_4[0xd0];
  174. u32 core_opmode; /* 0x400 */
  175. u32 resv_5[0x2bf];
  176. u32 busmode; /* 0xf00 */
  177. u32 txpoll;
  178. u32 rxpoll;
  179. u32 rxdesclist;
  180. u32 txdesclist;
  181. u32 dma_status;
  182. u32 dma_opmode;
  183. u32 intenable;
  184. u32 resv_6[2];
  185. u32 axi_mode; /* 0xf28 */
  186. };
  187. struct xgmac_dma_desc {
  188. __le32 flags;
  189. __le32 buf_size;
  190. __le32 buf1_addr; /* Buffer 1 Address Pointer */
  191. __le32 buf2_addr; /* Buffer 2 Address Pointer */
  192. __le32 ext_status;
  193. __le32 res[3];
  194. };
  195. /* XGMAC Descriptor Access Helpers */
  196. static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
  197. {
  198. if (buf_sz > MAX_DESC_BUF_SZ)
  199. p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
  200. (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
  201. else
  202. p->buf_size = cpu_to_le32(buf_sz);
  203. }
  204. static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
  205. {
  206. u32 len = le32_to_cpu(p->buf_size);
  207. return (len & DESC_BUFFER1_SZ_MASK) +
  208. ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
  209. }
  210. static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
  211. int buf_sz)
  212. {
  213. struct xgmac_dma_desc *end = p + ring_size - 1;
  214. memset(p, 0, sizeof(*p) * ring_size);
  215. for (; p <= end; p++)
  216. desc_set_buf_len(p, buf_sz);
  217. end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
  218. }
  219. static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
  220. {
  221. memset(p, 0, sizeof(*p) * ring_size);
  222. p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
  223. }
  224. static inline int desc_get_owner(struct xgmac_dma_desc *p)
  225. {
  226. return le32_to_cpu(p->flags) & DESC_OWN;
  227. }
  228. static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
  229. {
  230. /* Clear all fields and set the owner */
  231. p->flags = cpu_to_le32(DESC_OWN);
  232. }
  233. static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
  234. {
  235. u32 tmpflags = le32_to_cpu(p->flags);
  236. tmpflags &= TXDESC_END_RING;
  237. tmpflags |= flags | DESC_OWN;
  238. p->flags = cpu_to_le32(tmpflags);
  239. }
  240. static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
  241. {
  242. return (void *)le32_to_cpu(p->buf1_addr);
  243. }
  244. static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
  245. void *paddr, int len)
  246. {
  247. p->buf1_addr = cpu_to_le32(paddr);
  248. if (len > MAX_DESC_BUF_SZ)
  249. p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
  250. }
  251. static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
  252. void *paddr, int len)
  253. {
  254. desc_set_buf_len(p, len);
  255. desc_set_buf_addr(p, paddr, len);
  256. }
  257. static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
  258. {
  259. u32 data = le32_to_cpu(p->flags);
  260. u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
  261. if (data & RXDESC_FRAME_TYPE)
  262. len -= 4;
  263. return len;
  264. }
  265. struct calxeda_eth_dev {
  266. struct xgmac_dma_desc rx_chain[RX_NUM_DESC];
  267. struct xgmac_dma_desc tx_chain[TX_NUM_DESC];
  268. char rxbuffer[RX_BUF_SZ];
  269. u32 tx_currdesc;
  270. u32 rx_currdesc;
  271. struct eth_device *dev;
  272. } __aligned(32);
  273. /*
  274. * Initialize a descriptor ring. Calxeda XGMAC is configured to use
  275. * advanced descriptors.
  276. */
  277. static void init_rx_desc(struct calxeda_eth_dev *priv)
  278. {
  279. struct xgmac_dma_desc *rxdesc = priv->rx_chain;
  280. struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
  281. void *rxbuffer = priv->rxbuffer;
  282. int i;
  283. desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
  284. writel((ulong)rxdesc, &regs->rxdesclist);
  285. for (i = 0; i < RX_NUM_DESC; i++) {
  286. desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
  287. ETH_BUF_SZ);
  288. desc_set_rx_owner(rxdesc + i);
  289. }
  290. }
  291. static void init_tx_desc(struct calxeda_eth_dev *priv)
  292. {
  293. struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
  294. desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
  295. writel((ulong)priv->tx_chain, &regs->txdesclist);
  296. }
  297. static int xgmac_reset(struct eth_device *dev)
  298. {
  299. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  300. int timeout = MAC_TIMEOUT;
  301. u32 value;
  302. value = readl(&regs->config) & XGMAC_CONTROL_SPD_MASK;
  303. writel(XGMAC_DMA_BUSMODE_RESET, &regs->busmode);
  304. while ((timeout-- >= 0) &&
  305. (readl(&regs->busmode) & XGMAC_DMA_BUSMODE_RESET))
  306. udelay(1);
  307. writel(value, &regs->config);
  308. return timeout;
  309. }
  310. static void xgmac_hwmacaddr(struct eth_device *dev)
  311. {
  312. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  313. u32 macaddr[2];
  314. memcpy(macaddr, dev->enetaddr, 6);
  315. writel(macaddr[1], &regs->macaddr[0].hi);
  316. writel(macaddr[0], &regs->macaddr[0].lo);
  317. }
  318. static int xgmac_init(struct eth_device *dev, struct bd_info * bis)
  319. {
  320. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  321. struct calxeda_eth_dev *priv = dev->priv;
  322. int value;
  323. if (xgmac_reset(dev) < 0)
  324. return -1;
  325. /* set the hardware MAC address */
  326. xgmac_hwmacaddr(dev);
  327. /* set the AXI bus modes */
  328. value = XGMAC_DMA_BUSMODE_ATDS |
  329. (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) |
  330. XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL;
  331. writel(value, &regs->busmode);
  332. value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 |
  333. XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4;
  334. writel(value, &regs->axi_mode);
  335. /* set flow control parameters and store and forward mode */
  336. value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
  337. (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
  338. XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
  339. writel(value, &regs->core_opmode);
  340. /* enable pause frames */
  341. value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) |
  342. (1 << XGMAC_CORE_FLOW_PLT_SHIFT) |
  343. XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE;
  344. writel(value, &regs->flow_control);
  345. /* Initialize the descriptor chains */
  346. init_rx_desc(priv);
  347. init_tx_desc(priv);
  348. /* must set to 0, or when started up will cause issues */
  349. priv->tx_currdesc = 0;
  350. priv->rx_currdesc = 0;
  351. /* set default core values */
  352. value = readl(&regs->config);
  353. value &= XGMAC_CONTROL_SPD_MASK;
  354. value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
  355. XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
  356. /* Everything is ready enable both mac and DMA */
  357. value |= RXENABLE | TXENABLE;
  358. writel(value, &regs->config);
  359. value = readl(&regs->dma_opmode);
  360. value |= RXSTART | TXSTART;
  361. writel(value, &regs->dma_opmode);
  362. return 0;
  363. }
  364. static int xgmac_tx(struct eth_device *dev, void *packet, int length)
  365. {
  366. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  367. struct calxeda_eth_dev *priv = dev->priv;
  368. u32 currdesc = priv->tx_currdesc;
  369. struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
  370. int timeout;
  371. desc_set_buf_addr_and_size(txdesc, packet, length);
  372. desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
  373. TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
  374. /* write poll demand */
  375. writel(1, &regs->txpoll);
  376. timeout = 1000000;
  377. while (desc_get_owner(txdesc)) {
  378. if (timeout-- < 0) {
  379. printf("xgmac: TX timeout\n");
  380. return -ETIMEDOUT;
  381. }
  382. udelay(1);
  383. }
  384. priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
  385. return 0;
  386. }
  387. static int xgmac_rx(struct eth_device *dev)
  388. {
  389. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  390. struct calxeda_eth_dev *priv = dev->priv;
  391. u32 currdesc = priv->rx_currdesc;
  392. struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
  393. int length = 0;
  394. /* check if the host has the desc */
  395. if (desc_get_owner(rxdesc))
  396. return -1; /* something bad happened */
  397. length = desc_get_rx_frame_len(rxdesc);
  398. net_process_received_packet(desc_get_buf_addr(rxdesc), length);
  399. /* set descriptor back to owned by XGMAC */
  400. desc_set_rx_owner(rxdesc);
  401. writel(1, &regs->rxpoll);
  402. priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
  403. return length;
  404. }
  405. static void xgmac_halt(struct eth_device *dev)
  406. {
  407. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  408. struct calxeda_eth_dev *priv = dev->priv;
  409. int value;
  410. /* Disable TX/RX */
  411. value = readl(&regs->config);
  412. value &= ~(RXENABLE | TXENABLE);
  413. writel(value, &regs->config);
  414. /* Disable DMA */
  415. value = readl(&regs->dma_opmode);
  416. value &= ~(RXSTART | TXSTART);
  417. writel(value, &regs->dma_opmode);
  418. /* must set to 0, or when started up will cause issues */
  419. priv->tx_currdesc = 0;
  420. priv->rx_currdesc = 0;
  421. }
  422. int calxedaxgmac_initialize(u32 id, ulong base_addr)
  423. {
  424. struct eth_device *dev;
  425. struct calxeda_eth_dev *priv;
  426. struct xgmac_regs *regs;
  427. u32 macaddr[2];
  428. regs = (struct xgmac_regs *)base_addr;
  429. /* check hardware version */
  430. if (readl(&regs->version) != 0x1012)
  431. return -1;
  432. dev = malloc(sizeof(*dev));
  433. if (!dev)
  434. return 0;
  435. memset(dev, 0, sizeof(*dev));
  436. /* Structure must be aligned, because it contains the descriptors */
  437. priv = memalign(32, sizeof(*priv));
  438. if (!priv) {
  439. free(dev);
  440. return 0;
  441. }
  442. dev->iobase = (int)base_addr;
  443. dev->priv = priv;
  444. priv->dev = dev;
  445. sprintf(dev->name, "xgmac%d", id);
  446. /* The MAC address is already configured, so read it from registers. */
  447. macaddr[1] = readl(&regs->macaddr[0].hi);
  448. macaddr[0] = readl(&regs->macaddr[0].lo);
  449. memcpy(dev->enetaddr, macaddr, 6);
  450. dev->init = xgmac_init;
  451. dev->send = xgmac_tx;
  452. dev->recv = xgmac_rx;
  453. dev->halt = xgmac_halt;
  454. eth_register(dev);
  455. return 1;
  456. }