zynq_sdhci.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 - 2015 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <linux/delay.h>
  12. #include "mmc_private.h"
  13. #include <log.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/err.h>
  16. #include <linux/libfdt.h>
  17. #include <malloc.h>
  18. #include <sdhci.h>
  19. #include <zynqmp_tap_delay.h>
  20. #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
  21. #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
  22. #define SDHCI_ITAPDLY_CHGWIN 0x200
  23. #define SDHCI_ITAPDLY_ENABLE 0x100
  24. #define SDHCI_OTAPDLY_ENABLE 0x40
  25. #define SDHCI_TUNING_LOOP_COUNT 40
  26. #define MMC_BANK2 0x2
  27. struct arasan_sdhci_clk_data {
  28. int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
  29. int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
  30. };
  31. struct arasan_sdhci_plat {
  32. struct mmc_config cfg;
  33. struct mmc mmc;
  34. };
  35. struct arasan_sdhci_priv {
  36. struct sdhci_host *host;
  37. struct arasan_sdhci_clk_data clk_data;
  38. u8 deviceid;
  39. u8 bank;
  40. u8 no_1p8;
  41. };
  42. #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
  43. /* Default settings for ZynqMP Clock Phases */
  44. const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0};
  45. const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0};
  46. /* Default settings for Versal Clock Phases */
  47. const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0};
  48. const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0};
  49. static const u8 mode2timing[] = {
  50. [MMC_LEGACY] = MMC_TIMING_LEGACY,
  51. [MMC_HS] = MMC_TIMING_MMC_HS,
  52. [SD_HS] = MMC_TIMING_SD_HS,
  53. [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
  54. [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
  55. [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
  56. [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
  57. [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
  58. [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
  59. [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
  60. [MMC_HS_200] = MMC_TIMING_MMC_HS200,
  61. };
  62. static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  63. {
  64. u16 clk;
  65. unsigned long timeout;
  66. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  67. clk &= ~(SDHCI_CLOCK_CARD_EN);
  68. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  69. /* Issue DLL Reset */
  70. zynqmp_dll_reset(deviceid);
  71. /* Wait max 20 ms */
  72. timeout = 100;
  73. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  74. & SDHCI_CLOCK_INT_STABLE)) {
  75. if (timeout == 0) {
  76. dev_err(mmc_dev(host->mmc),
  77. ": Internal clock never stabilised.\n");
  78. return;
  79. }
  80. timeout--;
  81. udelay(1000);
  82. }
  83. clk |= SDHCI_CLOCK_CARD_EN;
  84. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  85. }
  86. static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  87. {
  88. struct mmc_cmd cmd;
  89. struct mmc_data data;
  90. u32 ctrl;
  91. struct sdhci_host *host;
  92. struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  93. char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  94. u8 deviceid;
  95. debug("%s\n", __func__);
  96. host = priv->host;
  97. deviceid = priv->deviceid;
  98. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  99. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  100. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  101. mdelay(1);
  102. arasan_zynqmp_dll_reset(host, deviceid);
  103. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  104. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  105. do {
  106. cmd.cmdidx = opcode;
  107. cmd.resp_type = MMC_RSP_R1;
  108. cmd.cmdarg = 0;
  109. data.blocksize = 64;
  110. data.blocks = 1;
  111. data.flags = MMC_DATA_READ;
  112. if (tuning_loop_counter-- == 0)
  113. break;
  114. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
  115. mmc->bus_width == 8)
  116. data.blocksize = 128;
  117. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  118. data.blocksize),
  119. SDHCI_BLOCK_SIZE);
  120. sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
  121. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  122. mmc_send_cmd(mmc, &cmd, NULL);
  123. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  124. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  125. udelay(1);
  126. } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  127. if (tuning_loop_counter < 0) {
  128. ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  129. sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
  130. }
  131. if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
  132. printf("%s:Tuning failed\n", __func__);
  133. return -1;
  134. }
  135. udelay(1);
  136. arasan_zynqmp_dll_reset(host, deviceid);
  137. /* Enable only interrupts served by the SD controller */
  138. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  139. SDHCI_INT_ENABLE);
  140. /* Mask all sdhci interrupt sources */
  141. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  142. return 0;
  143. }
  144. /**
  145. * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
  146. *
  147. * Set the SD Output Clock Tap Delays for Output path
  148. *
  149. * @host: Pointer to the sdhci_host structure.
  150. * @degrees: The clock phase shift between 0 - 359.
  151. * Return: 0 on success and error value on error
  152. */
  153. static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
  154. int degrees)
  155. {
  156. struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  157. struct mmc *mmc = (struct mmc *)host->mmc;
  158. u8 tap_delay, tap_max = 0;
  159. int ret;
  160. int timing = mode2timing[mmc->selected_mode];
  161. /*
  162. * This is applicable for SDHCI_SPEC_300 and above
  163. * ZynqMP does not set phase for <=25MHz clock.
  164. * If degrees is zero, no need to do anything.
  165. */
  166. if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
  167. timing == MMC_TIMING_LEGACY ||
  168. timing == MMC_TIMING_UHS_SDR12 || !degrees)
  169. return 0;
  170. switch (timing) {
  171. case MMC_TIMING_MMC_HS:
  172. case MMC_TIMING_SD_HS:
  173. case MMC_TIMING_UHS_SDR25:
  174. case MMC_TIMING_UHS_DDR50:
  175. case MMC_TIMING_MMC_DDR52:
  176. /* For 50MHz clock, 30 Taps are available */
  177. tap_max = 30;
  178. break;
  179. case MMC_TIMING_UHS_SDR50:
  180. /* For 100MHz clock, 15 Taps are available */
  181. tap_max = 15;
  182. break;
  183. case MMC_TIMING_UHS_SDR104:
  184. case MMC_TIMING_MMC_HS200:
  185. /* For 200MHz clock, 8 Taps are available */
  186. tap_max = 8;
  187. default:
  188. break;
  189. }
  190. tap_delay = (degrees * tap_max) / 360;
  191. arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
  192. return ret;
  193. }
  194. /**
  195. * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
  196. *
  197. * Set the SD Input Clock Tap Delays for Input path
  198. *
  199. * @host: Pointer to the sdhci_host structure.
  200. * @degrees: The clock phase shift between 0 - 359.
  201. * Return: 0 on success and error value on error
  202. */
  203. static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
  204. int degrees)
  205. {
  206. struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  207. struct mmc *mmc = (struct mmc *)host->mmc;
  208. u8 tap_delay, tap_max = 0;
  209. int ret;
  210. int timing = mode2timing[mmc->selected_mode];
  211. /*
  212. * This is applicable for SDHCI_SPEC_300 and above
  213. * ZynqMP does not set phase for <=25MHz clock.
  214. * If degrees is zero, no need to do anything.
  215. */
  216. if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
  217. timing == MMC_TIMING_LEGACY ||
  218. timing == MMC_TIMING_UHS_SDR12 || !degrees)
  219. return 0;
  220. switch (timing) {
  221. case MMC_TIMING_MMC_HS:
  222. case MMC_TIMING_SD_HS:
  223. case MMC_TIMING_UHS_SDR25:
  224. case MMC_TIMING_UHS_DDR50:
  225. case MMC_TIMING_MMC_DDR52:
  226. /* For 50MHz clock, 120 Taps are available */
  227. tap_max = 120;
  228. break;
  229. case MMC_TIMING_UHS_SDR50:
  230. /* For 100MHz clock, 60 Taps are available */
  231. tap_max = 60;
  232. break;
  233. case MMC_TIMING_UHS_SDR104:
  234. case MMC_TIMING_MMC_HS200:
  235. /* For 200MHz clock, 30 Taps are available */
  236. tap_max = 30;
  237. default:
  238. break;
  239. }
  240. tap_delay = (degrees * tap_max) / 360;
  241. arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
  242. return ret;
  243. }
  244. /**
  245. * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
  246. *
  247. * Set the SD Output Clock Tap Delays for Output path
  248. *
  249. * @host: Pointer to the sdhci_host structure.
  250. * @degrees The clock phase shift between 0 - 359.
  251. * Return: 0 on success and error value on error
  252. */
  253. static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
  254. int degrees)
  255. {
  256. struct mmc *mmc = (struct mmc *)host->mmc;
  257. u8 tap_delay, tap_max = 0;
  258. int ret;
  259. int timing = mode2timing[mmc->selected_mode];
  260. /*
  261. * This is applicable for SDHCI_SPEC_300 and above
  262. * Versal does not set phase for <=25MHz clock.
  263. * If degrees is zero, no need to do anything.
  264. */
  265. if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
  266. timing == MMC_TIMING_LEGACY ||
  267. timing == MMC_TIMING_UHS_SDR12 || !degrees)
  268. return 0;
  269. switch (timing) {
  270. case MMC_TIMING_MMC_HS:
  271. case MMC_TIMING_SD_HS:
  272. case MMC_TIMING_UHS_SDR25:
  273. case MMC_TIMING_UHS_DDR50:
  274. case MMC_TIMING_MMC_DDR52:
  275. /* For 50MHz clock, 30 Taps are available */
  276. tap_max = 30;
  277. break;
  278. case MMC_TIMING_UHS_SDR50:
  279. /* For 100MHz clock, 15 Taps are available */
  280. tap_max = 15;
  281. break;
  282. case MMC_TIMING_UHS_SDR104:
  283. case MMC_TIMING_MMC_HS200:
  284. /* For 200MHz clock, 8 Taps are available */
  285. tap_max = 8;
  286. default:
  287. break;
  288. }
  289. tap_delay = (degrees * tap_max) / 360;
  290. /* Set the Clock Phase */
  291. if (tap_delay) {
  292. u32 regval;
  293. regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
  294. regval |= SDHCI_OTAPDLY_ENABLE;
  295. sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
  296. regval |= tap_delay;
  297. sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
  298. }
  299. return ret;
  300. }
  301. /**
  302. * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
  303. *
  304. * Set the SD Input Clock Tap Delays for Input path
  305. *
  306. * @host: Pointer to the sdhci_host structure.
  307. * @degrees The clock phase shift between 0 - 359.
  308. * Return: 0 on success and error value on error
  309. */
  310. static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
  311. int degrees)
  312. {
  313. struct mmc *mmc = (struct mmc *)host->mmc;
  314. u8 tap_delay, tap_max = 0;
  315. int ret;
  316. int timing = mode2timing[mmc->selected_mode];
  317. /*
  318. * This is applicable for SDHCI_SPEC_300 and above
  319. * Versal does not set phase for <=25MHz clock.
  320. * If degrees is zero, no need to do anything.
  321. */
  322. if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
  323. timing == MMC_TIMING_LEGACY ||
  324. timing == MMC_TIMING_UHS_SDR12 || !degrees)
  325. return 0;
  326. switch (timing) {
  327. case MMC_TIMING_MMC_HS:
  328. case MMC_TIMING_SD_HS:
  329. case MMC_TIMING_UHS_SDR25:
  330. case MMC_TIMING_UHS_DDR50:
  331. case MMC_TIMING_MMC_DDR52:
  332. /* For 50MHz clock, 120 Taps are available */
  333. tap_max = 120;
  334. break;
  335. case MMC_TIMING_UHS_SDR50:
  336. /* For 100MHz clock, 60 Taps are available */
  337. tap_max = 60;
  338. break;
  339. case MMC_TIMING_UHS_SDR104:
  340. case MMC_TIMING_MMC_HS200:
  341. /* For 200MHz clock, 30 Taps are available */
  342. tap_max = 30;
  343. default:
  344. break;
  345. }
  346. tap_delay = (degrees * tap_max) / 360;
  347. /* Set the Clock Phase */
  348. if (tap_delay) {
  349. u32 regval;
  350. regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
  351. regval |= SDHCI_ITAPDLY_CHGWIN;
  352. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  353. regval |= SDHCI_ITAPDLY_ENABLE;
  354. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  355. regval |= tap_delay;
  356. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  357. regval &= ~SDHCI_ITAPDLY_CHGWIN;
  358. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  359. }
  360. return ret;
  361. }
  362. static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
  363. {
  364. struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  365. struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
  366. struct mmc *mmc = (struct mmc *)host->mmc;
  367. struct udevice *dev = mmc->dev;
  368. u8 timing = mode2timing[mmc->selected_mode];
  369. u32 iclk_phase = clk_data->clk_phase_in[timing];
  370. u32 oclk_phase = clk_data->clk_phase_out[timing];
  371. dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
  372. if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
  373. device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
  374. sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
  375. sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
  376. } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
  377. device_is_compatible(dev, "xlnx,versal-8.9a")) {
  378. sdhci_versal_sampleclk_set_phase(host, iclk_phase);
  379. sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
  380. }
  381. }
  382. static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
  383. const char *prop)
  384. {
  385. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  386. struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
  387. u32 clk_phase[2] = {0};
  388. /*
  389. * Read Tap Delay values from DT, if the DT does not contain the
  390. * Tap Values then use the pre-defined values
  391. */
  392. if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
  393. dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
  394. prop, clk_data->clk_phase_in[timing],
  395. clk_data->clk_phase_out[timing]);
  396. return;
  397. }
  398. /* The values read are Input and Output Clock Delays in order */
  399. clk_data->clk_phase_in[timing] = clk_phase[0];
  400. clk_data->clk_phase_out[timing] = clk_phase[1];
  401. }
  402. /**
  403. * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
  404. *
  405. * Called at initialization to parse the values of Tap Delays.
  406. *
  407. * @dev: Pointer to our struct udevice.
  408. */
  409. static void arasan_dt_parse_clk_phases(struct udevice *dev)
  410. {
  411. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  412. struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
  413. int i;
  414. if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
  415. device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
  416. for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
  417. clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
  418. clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
  419. }
  420. if (priv->bank == MMC_BANK2) {
  421. clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
  422. clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
  423. }
  424. }
  425. if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
  426. device_is_compatible(dev, "xlnx,versal-8.9a")) {
  427. for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
  428. clk_data->clk_phase_in[i] = versal_iclk_phases[i];
  429. clk_data->clk_phase_out[i] = versal_oclk_phases[i];
  430. }
  431. }
  432. arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
  433. "clk-phase-legacy");
  434. arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
  435. "clk-phase-mmc-hs");
  436. arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
  437. "clk-phase-sd-hs");
  438. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
  439. "clk-phase-uhs-sdr12");
  440. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
  441. "clk-phase-uhs-sdr25");
  442. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
  443. "clk-phase-uhs-sdr50");
  444. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
  445. "clk-phase-uhs-sdr104");
  446. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
  447. "clk-phase-uhs-ddr50");
  448. arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
  449. "clk-phase-mmc-ddr52");
  450. arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
  451. "clk-phase-mmc-hs200");
  452. arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
  453. "clk-phase-mmc-hs400");
  454. }
  455. static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
  456. {
  457. struct mmc *mmc = (struct mmc *)host->mmc;
  458. u32 reg;
  459. if (!IS_SD(mmc))
  460. return;
  461. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  462. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  463. reg |= SDHCI_CTRL_VDD_180;
  464. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  465. }
  466. if (mmc->selected_mode > SD_HS &&
  467. mmc->selected_mode <= MMC_HS_200)
  468. sdhci_set_uhs_timing(host);
  469. }
  470. const struct sdhci_ops arasan_ops = {
  471. .platform_execute_tuning = &arasan_sdhci_execute_tuning,
  472. .set_delay = &arasan_sdhci_set_tapdelay,
  473. .set_control_reg = &arasan_sdhci_set_control_reg,
  474. };
  475. #endif
  476. static int arasan_sdhci_probe(struct udevice *dev)
  477. {
  478. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  479. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  480. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  481. struct sdhci_host *host;
  482. struct clk clk;
  483. unsigned long clock;
  484. int ret;
  485. host = priv->host;
  486. ret = clk_get_by_index(dev, 0, &clk);
  487. if (ret < 0) {
  488. dev_err(dev, "failed to get clock\n");
  489. return ret;
  490. }
  491. clock = clk_get_rate(&clk);
  492. if (IS_ERR_VALUE(clock)) {
  493. dev_err(dev, "failed to get rate\n");
  494. return clock;
  495. }
  496. debug("%s: CLK %ld\n", __func__, clock);
  497. ret = clk_enable(&clk);
  498. if (ret && ret != -ENOSYS) {
  499. dev_err(dev, "failed to enable clock\n");
  500. return ret;
  501. }
  502. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
  503. SDHCI_QUIRK_BROKEN_R1B;
  504. #ifdef CONFIG_ZYNQ_HISPD_BROKEN
  505. host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
  506. #endif
  507. if (priv->no_1p8)
  508. host->quirks |= SDHCI_QUIRK_NO_1_8_V;
  509. plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
  510. ret = mmc_of_parse(dev, &plat->cfg);
  511. if (ret)
  512. return ret;
  513. host->max_clk = clock;
  514. host->mmc = &plat->mmc;
  515. host->mmc->dev = dev;
  516. host->mmc->priv = host;
  517. ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
  518. CONFIG_ZYNQ_SDHCI_MIN_FREQ);
  519. if (ret)
  520. return ret;
  521. upriv->mmc = host->mmc;
  522. return sdhci_probe(dev);
  523. }
  524. static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
  525. {
  526. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  527. priv->host = calloc(1, sizeof(struct sdhci_host));
  528. if (!priv->host)
  529. return -1;
  530. priv->host->name = dev->name;
  531. #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
  532. priv->host->ops = &arasan_ops;
  533. arasan_dt_parse_clk_phases(dev);
  534. #endif
  535. priv->host->ioaddr = (void *)dev_read_addr(dev);
  536. if (IS_ERR(priv->host->ioaddr))
  537. return PTR_ERR(priv->host->ioaddr);
  538. priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
  539. priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
  540. priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
  541. return 0;
  542. }
  543. static int arasan_sdhci_bind(struct udevice *dev)
  544. {
  545. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  546. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  547. }
  548. static const struct udevice_id arasan_sdhci_ids[] = {
  549. { .compatible = "arasan,sdhci-8.9a" },
  550. { }
  551. };
  552. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  553. .name = "arasan_sdhci",
  554. .id = UCLASS_MMC,
  555. .of_match = arasan_sdhci_ids,
  556. .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
  557. .ops = &sdhci_ops,
  558. .bind = arasan_sdhci_bind,
  559. .probe = arasan_sdhci_probe,
  560. .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
  561. .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
  562. };