tegra_mmc.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 SAMSUNG Electronics
  4. * Minkyu Kang <mk7.kang@samsung.com>
  5. * Jaehoon Chung <jh80.chung@samsung.com>
  6. * Portions Copyright 2011-2019 NVIDIA Corporation
  7. */
  8. #include <bouncebuf.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <log.h>
  13. #include <mmc.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-tegra/tegra_mmc.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/err.h>
  20. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
  21. #include <asm/arch/clock.h>
  22. #endif
  23. struct tegra_mmc_plat {
  24. struct mmc_config cfg;
  25. struct mmc mmc;
  26. };
  27. struct tegra_mmc_priv {
  28. struct tegra_mmc *reg;
  29. struct reset_ctl reset_ctl;
  30. struct clk clk;
  31. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  32. struct gpio_desc pwr_gpio; /* Power GPIO */
  33. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  34. unsigned int version; /* SDHCI spec. version */
  35. unsigned int clock; /* Current clock (MHz) */
  36. int mmc_id; /* peripheral id */
  37. };
  38. static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
  39. unsigned short power)
  40. {
  41. u8 pwr = 0;
  42. debug("%s: power = %x\n", __func__, power);
  43. if (power != (unsigned short)-1) {
  44. switch (1 << power) {
  45. case MMC_VDD_165_195:
  46. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  47. break;
  48. case MMC_VDD_29_30:
  49. case MMC_VDD_30_31:
  50. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  51. break;
  52. case MMC_VDD_32_33:
  53. case MMC_VDD_33_34:
  54. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  55. break;
  56. }
  57. }
  58. debug("%s: pwr = %X\n", __func__, pwr);
  59. /* Set the bus voltage first (if any) */
  60. writeb(pwr, &priv->reg->pwrcon);
  61. if (pwr == 0)
  62. return;
  63. /* Now enable bus power */
  64. pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  65. writeb(pwr, &priv->reg->pwrcon);
  66. }
  67. static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
  68. struct mmc_data *data,
  69. struct bounce_buffer *bbstate)
  70. {
  71. unsigned char ctrl;
  72. debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  73. bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  74. data->blocksize);
  75. writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
  76. /*
  77. * DMASEL[4:3]
  78. * 00 = Selects SDMA
  79. * 01 = Reserved
  80. * 10 = Selects 32-bit Address ADMA2
  81. * 11 = Selects 64-bit Address ADMA2
  82. */
  83. ctrl = readb(&priv->reg->hostctl);
  84. ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  85. ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  86. writeb(ctrl, &priv->reg->hostctl);
  87. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  88. writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
  89. writew(data->blocks, &priv->reg->blkcnt);
  90. }
  91. static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
  92. struct mmc_data *data)
  93. {
  94. unsigned short mode;
  95. debug(" mmc_set_transfer_mode called\n");
  96. /*
  97. * TRNMOD
  98. * MUL1SIN0[5] : Multi/Single Block Select
  99. * RD1WT0[4] : Data Transfer Direction Select
  100. * 1 = read
  101. * 0 = write
  102. * ENACMD12[2] : Auto CMD12 Enable
  103. * ENBLKCNT[1] : Block Count Enable
  104. * ENDMA[0] : DMA Enable
  105. */
  106. mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
  107. TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
  108. if (data->blocks > 1)
  109. mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
  110. if (data->flags & MMC_DATA_READ)
  111. mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
  112. writew(mode, &priv->reg->trnmod);
  113. }
  114. static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
  115. struct mmc_cmd *cmd,
  116. struct mmc_data *data,
  117. unsigned int timeout)
  118. {
  119. /*
  120. * PRNSTS
  121. * CMDINHDAT[1] : Command Inhibit (DAT)
  122. * CMDINHCMD[0] : Command Inhibit (CMD)
  123. */
  124. unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
  125. /*
  126. * We shouldn't wait for data inhibit for stop commands, even
  127. * though they might use busy signaling
  128. */
  129. if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
  130. mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
  131. while (readl(&priv->reg->prnsts) & mask) {
  132. if (timeout == 0) {
  133. printf("%s: timeout error\n", __func__);
  134. return -1;
  135. }
  136. timeout--;
  137. udelay(1000);
  138. }
  139. return 0;
  140. }
  141. static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
  142. struct mmc_data *data,
  143. struct bounce_buffer *bbstate)
  144. {
  145. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  146. int flags, i;
  147. int result;
  148. unsigned int mask = 0;
  149. unsigned int retry = 0x100000;
  150. debug(" mmc_send_cmd called\n");
  151. result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
  152. if (result < 0)
  153. return result;
  154. if (data)
  155. tegra_mmc_prepare_data(priv, data, bbstate);
  156. debug("cmd->arg: %08x\n", cmd->cmdarg);
  157. writel(cmd->cmdarg, &priv->reg->argument);
  158. if (data)
  159. tegra_mmc_set_transfer_mode(priv, data);
  160. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
  161. return -1;
  162. /*
  163. * CMDREG
  164. * CMDIDX[13:8] : Command index
  165. * DATAPRNT[5] : Data Present Select
  166. * ENCMDIDX[4] : Command Index Check Enable
  167. * ENCMDCRC[3] : Command CRC Check Enable
  168. * RSPTYP[1:0]
  169. * 00 = No Response
  170. * 01 = Length 136
  171. * 10 = Length 48
  172. * 11 = Length 48 Check busy after response
  173. */
  174. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  175. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
  176. else if (cmd->resp_type & MMC_RSP_136)
  177. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
  178. else if (cmd->resp_type & MMC_RSP_BUSY)
  179. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
  180. else
  181. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
  182. if (cmd->resp_type & MMC_RSP_CRC)
  183. flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
  184. if (cmd->resp_type & MMC_RSP_OPCODE)
  185. flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
  186. if (data)
  187. flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
  188. debug("cmd: %d\n", cmd->cmdidx);
  189. writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
  190. for (i = 0; i < retry; i++) {
  191. mask = readl(&priv->reg->norintsts);
  192. /* Command Complete */
  193. if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
  194. if (!data)
  195. writel(mask, &priv->reg->norintsts);
  196. break;
  197. }
  198. }
  199. if (i == retry) {
  200. printf("%s: waiting for status update\n", __func__);
  201. writel(mask, &priv->reg->norintsts);
  202. return -ETIMEDOUT;
  203. }
  204. if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
  205. /* Timeout Error */
  206. debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
  207. writel(mask, &priv->reg->norintsts);
  208. return -ETIMEDOUT;
  209. } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
  210. /* Error Interrupt */
  211. debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
  212. writel(mask, &priv->reg->norintsts);
  213. return -1;
  214. }
  215. if (cmd->resp_type & MMC_RSP_PRESENT) {
  216. if (cmd->resp_type & MMC_RSP_136) {
  217. /* CRC is stripped so we need to do some shifting. */
  218. for (i = 0; i < 4; i++) {
  219. unsigned long offset = (unsigned long)
  220. (&priv->reg->rspreg3 - i);
  221. cmd->response[i] = readl(offset) << 8;
  222. if (i != 3) {
  223. cmd->response[i] |=
  224. readb(offset - 1);
  225. }
  226. debug("cmd->resp[%d]: %08x\n",
  227. i, cmd->response[i]);
  228. }
  229. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  230. for (i = 0; i < retry; i++) {
  231. /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
  232. if (readl(&priv->reg->prnsts)
  233. & (1 << 20)) /* DAT[0] */
  234. break;
  235. }
  236. if (i == retry) {
  237. printf("%s: card is still busy\n", __func__);
  238. writel(mask, &priv->reg->norintsts);
  239. return -ETIMEDOUT;
  240. }
  241. cmd->response[0] = readl(&priv->reg->rspreg0);
  242. debug("cmd->resp[0]: %08x\n", cmd->response[0]);
  243. } else {
  244. cmd->response[0] = readl(&priv->reg->rspreg0);
  245. debug("cmd->resp[0]: %08x\n", cmd->response[0]);
  246. }
  247. }
  248. if (data) {
  249. unsigned long start = get_timer(0);
  250. while (1) {
  251. mask = readl(&priv->reg->norintsts);
  252. if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
  253. /* Error Interrupt */
  254. writel(mask, &priv->reg->norintsts);
  255. printf("%s: error during transfer: 0x%08x\n",
  256. __func__, mask);
  257. return -1;
  258. } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
  259. /*
  260. * DMA Interrupt, restart the transfer where
  261. * it was interrupted.
  262. */
  263. unsigned int address = readl(&priv->reg->sysad);
  264. debug("DMA end\n");
  265. writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
  266. &priv->reg->norintsts);
  267. writel(address, &priv->reg->sysad);
  268. } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
  269. /* Transfer Complete */
  270. debug("r/w is done\n");
  271. break;
  272. } else if (get_timer(start) > 8000UL) {
  273. writel(mask, &priv->reg->norintsts);
  274. printf("%s: MMC Timeout\n"
  275. " Interrupt status 0x%08x\n"
  276. " Interrupt status enable 0x%08x\n"
  277. " Interrupt signal enable 0x%08x\n"
  278. " Present status 0x%08x\n",
  279. __func__, mask,
  280. readl(&priv->reg->norintstsen),
  281. readl(&priv->reg->norintsigen),
  282. readl(&priv->reg->prnsts));
  283. return -1;
  284. }
  285. }
  286. writel(mask, &priv->reg->norintsts);
  287. }
  288. udelay(1000);
  289. return 0;
  290. }
  291. static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  292. struct mmc_data *data)
  293. {
  294. void *buf;
  295. unsigned int bbflags;
  296. size_t len;
  297. struct bounce_buffer bbstate;
  298. int ret;
  299. if (data) {
  300. if (data->flags & MMC_DATA_READ) {
  301. buf = data->dest;
  302. bbflags = GEN_BB_WRITE;
  303. } else {
  304. buf = (void *)data->src;
  305. bbflags = GEN_BB_READ;
  306. }
  307. len = data->blocks * data->blocksize;
  308. bounce_buffer_start(&bbstate, buf, len, bbflags);
  309. }
  310. ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
  311. if (data)
  312. bounce_buffer_stop(&bbstate);
  313. return ret;
  314. }
  315. static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
  316. {
  317. ulong rate;
  318. int div;
  319. unsigned short clk;
  320. unsigned long timeout;
  321. debug(" mmc_change_clock called\n");
  322. /*
  323. * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
  324. */
  325. if (clock == 0)
  326. goto out;
  327. rate = clk_set_rate(&priv->clk, clock);
  328. div = (rate + clock - 1) / clock;
  329. #if defined(CONFIG_TEGRA210)
  330. if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
  331. /* clock_adjust_periph_pll_div() chooses a 'bad' clock
  332. * on SDMMC1 T210, so skip it here and force a clock
  333. * that's been spec'd in the table in the TRM for
  334. * card-detect (400KHz).
  335. */
  336. uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
  337. CLOCK_ID_PERIPH, 24727273, NULL);
  338. div = 62;
  339. debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
  340. __func__, effective_rate, div, clock);
  341. } else {
  342. clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
  343. clock, &div);
  344. }
  345. #endif
  346. debug("div = %d\n", div);
  347. writew(0, &priv->reg->clkcon);
  348. /*
  349. * CLKCON
  350. * SELFREQ[15:8] : base clock divided by value
  351. * ENSDCLK[2] : SD Clock Enable
  352. * STBLINTCLK[1] : Internal Clock Stable
  353. * ENINTCLK[0] : Internal Clock Enable
  354. */
  355. div >>= 1;
  356. clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
  357. TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
  358. writew(clk, &priv->reg->clkcon);
  359. /* Wait max 10 ms */
  360. timeout = 10;
  361. while (!(readw(&priv->reg->clkcon) &
  362. TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
  363. if (timeout == 0) {
  364. printf("%s: timeout error\n", __func__);
  365. return;
  366. }
  367. timeout--;
  368. udelay(1000);
  369. }
  370. clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
  371. writew(clk, &priv->reg->clkcon);
  372. debug("mmc_change_clock: clkcon = %08X\n", clk);
  373. out:
  374. priv->clock = clock;
  375. }
  376. static int tegra_mmc_set_ios(struct udevice *dev)
  377. {
  378. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  379. struct mmc *mmc = mmc_get_mmc_dev(dev);
  380. unsigned char ctrl;
  381. debug(" mmc_set_ios called\n");
  382. debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
  383. /* Change clock first */
  384. tegra_mmc_change_clock(priv, mmc->clock);
  385. ctrl = readb(&priv->reg->hostctl);
  386. /*
  387. * WIDE8[5]
  388. * 0 = Depend on WIDE4
  389. * 1 = 8-bit mode
  390. * WIDE4[1]
  391. * 1 = 4-bit mode
  392. * 0 = 1-bit mode
  393. */
  394. if (mmc->bus_width == 8)
  395. ctrl |= (1 << 5);
  396. else if (mmc->bus_width == 4)
  397. ctrl |= (1 << 1);
  398. else
  399. ctrl &= ~(1 << 1 | 1 << 5);
  400. writeb(ctrl, &priv->reg->hostctl);
  401. debug("mmc_set_ios: hostctl = %08X\n", ctrl);
  402. return 0;
  403. }
  404. static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
  405. {
  406. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
  407. u32 val;
  408. u16 clk_con;
  409. int timeout;
  410. int id = priv->mmc_id;
  411. debug("%s: sdmmc address = %p, id = %d\n", __func__,
  412. priv->reg, id);
  413. /* Set the pad drive strength for SDMMC1 or 3 only */
  414. if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
  415. debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
  416. __func__);
  417. return;
  418. }
  419. val = readl(&priv->reg->sdmemcmppadctl);
  420. val &= 0xFFFFFFF0;
  421. val |= MEMCOMP_PADCTRL_VREF;
  422. writel(val, &priv->reg->sdmemcmppadctl);
  423. /* Disable SD Clock Enable before running auto-cal as per TRM */
  424. clk_con = readw(&priv->reg->clkcon);
  425. debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
  426. clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
  427. writew(clk_con, &priv->reg->clkcon);
  428. val = readl(&priv->reg->autocalcfg);
  429. val &= 0xFFFF0000;
  430. val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
  431. writel(val, &priv->reg->autocalcfg);
  432. val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
  433. writel(val, &priv->reg->autocalcfg);
  434. debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
  435. udelay(1);
  436. timeout = 100; /* 10 mSec max (100*100uS) */
  437. do {
  438. val = readl(&priv->reg->autocalsts);
  439. udelay(100);
  440. } while ((val & AUTO_CAL_ACTIVE) && --timeout);
  441. val = readl(&priv->reg->autocalsts);
  442. debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
  443. __func__, val, timeout);
  444. /* Re-enable SD Clock Enable when auto-cal is done */
  445. clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
  446. writew(clk_con, &priv->reg->clkcon);
  447. clk_con = readw(&priv->reg->clkcon);
  448. debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
  449. if (timeout == 0) {
  450. printf("%s: Warning: Autocal timed out!\n", __func__);
  451. /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
  452. }
  453. #if defined(CONFIG_TEGRA210)
  454. u32 tap_value, trim_value;
  455. /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
  456. val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */
  457. val &= IO_TRIM_BYPASS_MASK;
  458. if (id == PERIPH_ID_SDMMC1) {
  459. tap_value = 4; /* default */
  460. if (val)
  461. tap_value = 3;
  462. trim_value = 2;
  463. } else { /* SDMMC3 */
  464. tap_value = 3;
  465. trim_value = 3;
  466. }
  467. val = readl(&priv->reg->venclkctl);
  468. val &= ~TRIM_VAL_MASK;
  469. val |= (trim_value << TRIM_VAL_SHIFT);
  470. val &= ~TAP_VAL_MASK;
  471. val |= (tap_value << TAP_VAL_SHIFT);
  472. writel(val, &priv->reg->venclkctl);
  473. debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
  474. #endif /* T210 */
  475. #endif /* T30/T210 */
  476. }
  477. static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
  478. {
  479. unsigned int timeout;
  480. debug(" mmc_reset called\n");
  481. /*
  482. * RSTALL[0] : Software reset for all
  483. * 1 = reset
  484. * 0 = work
  485. */
  486. writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
  487. priv->clock = 0;
  488. /* Wait max 100 ms */
  489. timeout = 100;
  490. /* hw clears the bit when it's done */
  491. while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
  492. if (timeout == 0) {
  493. printf("%s: timeout error\n", __func__);
  494. return;
  495. }
  496. timeout--;
  497. udelay(1000);
  498. }
  499. /* Set SD bus voltage & enable bus power */
  500. tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
  501. debug("%s: power control = %02X, host control = %02X\n", __func__,
  502. readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
  503. /* Make sure SDIO pads are set up */
  504. tegra_mmc_pad_init(priv);
  505. }
  506. static int tegra_mmc_init(struct udevice *dev)
  507. {
  508. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  509. struct mmc *mmc = mmc_get_mmc_dev(dev);
  510. unsigned int mask;
  511. debug(" tegra_mmc_init called\n");
  512. #if defined(CONFIG_TEGRA210)
  513. priv->mmc_id = clock_decode_periph_id(dev);
  514. if (priv->mmc_id == PERIPH_ID_NONE) {
  515. printf("%s: Missing/invalid peripheral ID\n", __func__);
  516. return -EINVAL;
  517. }
  518. #endif
  519. tegra_mmc_reset(priv, mmc);
  520. #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
  521. /*
  522. * Disable the external clock loopback and use the internal one on
  523. * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
  524. * bits being set to 0xfffd according to the TRM.
  525. *
  526. * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
  527. * approach once proper kernel integration made it mainline.
  528. */
  529. if (priv->reg == (void *)0x700b0400) {
  530. mask = readl(&priv->reg->venmiscctl);
  531. mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
  532. writel(mask, &priv->reg->venmiscctl);
  533. }
  534. #endif
  535. priv->version = readw(&priv->reg->hcver);
  536. debug("host version = %x\n", priv->version);
  537. /* mask all */
  538. writel(0xffffffff, &priv->reg->norintstsen);
  539. writel(0xffffffff, &priv->reg->norintsigen);
  540. writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
  541. /*
  542. * NORMAL Interrupt Status Enable Register init
  543. * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
  544. * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
  545. * [3] ENSTADMAINT : DMA boundary interrupt
  546. * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
  547. * [0] ENSTACMDCMPLT : Command Complete Status Enable
  548. */
  549. mask = readl(&priv->reg->norintstsen);
  550. mask &= ~(0xffff);
  551. mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
  552. TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
  553. TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
  554. TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
  555. TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
  556. writel(mask, &priv->reg->norintstsen);
  557. /*
  558. * NORMAL Interrupt Signal Enable Register init
  559. * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
  560. */
  561. mask = readl(&priv->reg->norintsigen);
  562. mask &= ~(0xffff);
  563. mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
  564. writel(mask, &priv->reg->norintsigen);
  565. return 0;
  566. }
  567. static int tegra_mmc_getcd(struct udevice *dev)
  568. {
  569. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  570. debug("tegra_mmc_getcd called\n");
  571. if (dm_gpio_is_valid(&priv->cd_gpio))
  572. return dm_gpio_get_value(&priv->cd_gpio);
  573. return 1;
  574. }
  575. static const struct dm_mmc_ops tegra_mmc_ops = {
  576. .send_cmd = tegra_mmc_send_cmd,
  577. .set_ios = tegra_mmc_set_ios,
  578. .get_cd = tegra_mmc_getcd,
  579. };
  580. static int tegra_mmc_probe(struct udevice *dev)
  581. {
  582. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  583. struct tegra_mmc_plat *plat = dev_get_platdata(dev);
  584. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  585. struct mmc_config *cfg = &plat->cfg;
  586. int bus_width, ret;
  587. cfg->name = dev->name;
  588. bus_width = dev_read_u32_default(dev, "bus-width", 1);
  589. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  590. cfg->host_caps = 0;
  591. if (bus_width == 8)
  592. cfg->host_caps |= MMC_MODE_8BIT;
  593. if (bus_width >= 4)
  594. cfg->host_caps |= MMC_MODE_4BIT;
  595. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  596. /*
  597. * min freq is for card identification, and is the highest
  598. * low-speed SDIO card frequency (actually 400KHz)
  599. * max freq is highest HS eMMC clock as per the SD/MMC spec
  600. * (actually 52MHz)
  601. */
  602. cfg->f_min = 375000;
  603. cfg->f_max = 48000000;
  604. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  605. priv->reg = (void *)dev_read_addr(dev);
  606. ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
  607. if (ret) {
  608. debug("reset_get_by_name() failed: %d\n", ret);
  609. return ret;
  610. }
  611. ret = clk_get_by_index(dev, 0, &priv->clk);
  612. if (ret) {
  613. debug("clk_get_by_index() failed: %d\n", ret);
  614. return ret;
  615. }
  616. ret = reset_assert(&priv->reset_ctl);
  617. if (ret)
  618. return ret;
  619. ret = clk_enable(&priv->clk);
  620. if (ret)
  621. return ret;
  622. ret = clk_set_rate(&priv->clk, 20000000);
  623. if (IS_ERR_VALUE(ret))
  624. return ret;
  625. ret = reset_deassert(&priv->reset_ctl);
  626. if (ret)
  627. return ret;
  628. /* These GPIOs are optional */
  629. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  630. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  631. gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
  632. GPIOD_IS_OUT);
  633. if (dm_gpio_is_valid(&priv->pwr_gpio))
  634. dm_gpio_set_value(&priv->pwr_gpio, 1);
  635. upriv->mmc = &plat->mmc;
  636. return tegra_mmc_init(dev);
  637. }
  638. static int tegra_mmc_bind(struct udevice *dev)
  639. {
  640. struct tegra_mmc_plat *plat = dev_get_platdata(dev);
  641. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  642. }
  643. static const struct udevice_id tegra_mmc_ids[] = {
  644. { .compatible = "nvidia,tegra20-sdhci" },
  645. { .compatible = "nvidia,tegra30-sdhci" },
  646. { .compatible = "nvidia,tegra114-sdhci" },
  647. { .compatible = "nvidia,tegra124-sdhci" },
  648. { .compatible = "nvidia,tegra210-sdhci" },
  649. { .compatible = "nvidia,tegra186-sdhci" },
  650. { }
  651. };
  652. U_BOOT_DRIVER(tegra_mmc_drv) = {
  653. .name = "tegra_mmc",
  654. .id = UCLASS_MMC,
  655. .of_match = tegra_mmc_ids,
  656. .bind = tegra_mmc_bind,
  657. .probe = tegra_mmc_probe,
  658. .ops = &tegra_mmc_ops,
  659. .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
  660. .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
  661. };