socfpga_dw_mmc.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/arch/clock_manager.h>
  8. #include <asm/arch/system_manager.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <dwmmc.h>
  12. #include <errno.h>
  13. #include <fdtdec.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/libfdt.h>
  16. #include <linux/err.h>
  17. #include <malloc.h>
  18. #include <reset.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. struct socfpga_dwmci_plat {
  21. struct mmc_config cfg;
  22. struct mmc mmc;
  23. };
  24. /* socfpga implmentation specific driver private data */
  25. struct dwmci_socfpga_priv_data {
  26. struct dwmci_host host;
  27. unsigned int drvsel;
  28. unsigned int smplsel;
  29. };
  30. static void socfpga_dwmci_reset(struct udevice *dev)
  31. {
  32. struct reset_ctl_bulk reset_bulk;
  33. int ret;
  34. ret = reset_get_bulk(dev, &reset_bulk);
  35. if (ret) {
  36. dev_warn(dev, "Can't get reset: %d\n", ret);
  37. return;
  38. }
  39. reset_deassert_bulk(&reset_bulk);
  40. }
  41. static void socfpga_dwmci_clksel(struct dwmci_host *host)
  42. {
  43. struct dwmci_socfpga_priv_data *priv = host->priv;
  44. u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
  45. ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
  46. /* Disable SDMMC clock. */
  47. clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  48. CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  49. debug("%s: drvsel %d smplsel %d\n", __func__,
  50. priv->drvsel, priv->smplsel);
  51. writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
  52. debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  53. readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
  54. /* Enable SDMMC clock */
  55. setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  56. CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  57. }
  58. static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
  59. {
  60. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  61. struct dwmci_host *host = &priv->host;
  62. #if CONFIG_IS_ENABLED(CLK)
  63. struct clk clk;
  64. int ret;
  65. ret = clk_get_by_index(dev, 1, &clk);
  66. if (ret)
  67. return ret;
  68. host->bus_hz = clk_get_rate(&clk);
  69. clk_free(&clk);
  70. #else
  71. /* Fixed clock divide by 4 which due to the SDMMC wrapper */
  72. host->bus_hz = cm_get_mmc_controller_clk_hz();
  73. #endif
  74. if (host->bus_hz == 0) {
  75. printf("DWMMC: MMC clock is zero!");
  76. return -EINVAL;
  77. }
  78. return 0;
  79. }
  80. static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
  81. {
  82. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  83. struct dwmci_host *host = &priv->host;
  84. int fifo_depth;
  85. fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  86. "fifo-depth", 0);
  87. if (fifo_depth < 0) {
  88. printf("DWMMC: Can't get FIFO depth\n");
  89. return -EINVAL;
  90. }
  91. host->name = dev->name;
  92. host->ioaddr = dev_read_addr_ptr(dev);
  93. host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  94. "bus-width", 4);
  95. host->clksel = socfpga_dwmci_clksel;
  96. /*
  97. * TODO(sjg@chromium.org): Remove the need for this hack.
  98. * We only have one dwmmc block on gen5 SoCFPGA.
  99. */
  100. host->dev_index = 0;
  101. host->fifoth_val = MSIZE(0x2) |
  102. RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
  103. priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  104. "drvsel", 3);
  105. priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  106. "smplsel", 0);
  107. host->priv = priv;
  108. return 0;
  109. }
  110. static int socfpga_dwmmc_probe(struct udevice *dev)
  111. {
  112. #ifdef CONFIG_BLK
  113. struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
  114. #endif
  115. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  116. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  117. struct dwmci_host *host = &priv->host;
  118. int ret;
  119. ret = socfpga_dwmmc_get_clk_rate(dev);
  120. if (ret)
  121. return ret;
  122. socfpga_dwmci_reset(dev);
  123. #ifdef CONFIG_BLK
  124. dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
  125. host->mmc = &plat->mmc;
  126. #else
  127. ret = add_dwmci(host, host->bus_hz, 400000);
  128. if (ret)
  129. return ret;
  130. #endif
  131. host->mmc->priv = &priv->host;
  132. upriv->mmc = host->mmc;
  133. host->mmc->dev = dev;
  134. return dwmci_probe(dev);
  135. }
  136. static int socfpga_dwmmc_bind(struct udevice *dev)
  137. {
  138. #ifdef CONFIG_BLK
  139. struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
  140. int ret;
  141. ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
  142. if (ret)
  143. return ret;
  144. #endif
  145. return 0;
  146. }
  147. static const struct udevice_id socfpga_dwmmc_ids[] = {
  148. { .compatible = "altr,socfpga-dw-mshc" },
  149. { }
  150. };
  151. U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
  152. .name = "socfpga_dwmmc",
  153. .id = UCLASS_MMC,
  154. .of_match = socfpga_dwmmc_ids,
  155. .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
  156. .ops = &dm_dwmci_ops,
  157. .bind = socfpga_dwmmc_bind,
  158. .probe = socfpga_dwmmc_probe,
  159. .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
  160. .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
  161. };