sh_mmcif.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * MMCIF driver.
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. */
  7. #ifndef _SH_MMCIF_H_
  8. #define _SH_MMCIF_H_
  9. struct sh_mmcif_regs {
  10. unsigned long ce_cmd_set;
  11. unsigned long reserved;
  12. unsigned long ce_arg;
  13. unsigned long ce_arg_cmd12;
  14. unsigned long ce_cmd_ctrl;
  15. unsigned long ce_block_set;
  16. unsigned long ce_clk_ctrl;
  17. unsigned long ce_buf_acc;
  18. unsigned long ce_resp3;
  19. unsigned long ce_resp2;
  20. unsigned long ce_resp1;
  21. unsigned long ce_resp0;
  22. unsigned long ce_resp_cmd12;
  23. unsigned long ce_data;
  24. unsigned long reserved2[2];
  25. unsigned long ce_int;
  26. unsigned long ce_int_mask;
  27. unsigned long ce_host_sts1;
  28. unsigned long ce_host_sts2;
  29. unsigned long reserved3[11];
  30. unsigned long ce_version;
  31. };
  32. /* CE_CMD_SET */
  33. #define CMD_MASK 0x3f000000
  34. #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
  35. /* R1/R1b/R3/R4/R5 */
  36. #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22))
  37. /* R2 */
  38. #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22))
  39. /* R1b */
  40. #define CMD_SET_RBSY (1 << 21)
  41. #define CMD_SET_CCSEN (1 << 20)
  42. /* 1: on data, 0: no data */
  43. #define CMD_SET_WDAT (1 << 19)
  44. /* 1: write to card, 0: read from card */
  45. #define CMD_SET_DWEN (1 << 18)
  46. /* 1: multi block trans, 0: single */
  47. #define CMD_SET_CMLTE (1 << 17)
  48. /* 1: CMD12 auto issue */
  49. #define CMD_SET_CMD12EN (1 << 16)
  50. /* index check */
  51. #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14))
  52. /* check bits check */
  53. #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14))
  54. /* no check */
  55. #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14))
  56. /* 1: CRC7 check*/
  57. #define CMD_SET_CRC7C ((0 << 13) | (0 << 12))
  58. /* 1: check bits check*/
  59. #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12))
  60. /* 1: internal CRC7 check*/
  61. #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12))
  62. /* 1: CRC16 check*/
  63. #define CMD_SET_CRC16C (1 << 10)
  64. /* 1: not receive CRC status */
  65. #define CMD_SET_CRCSTE (1 << 8)
  66. /* 1: tran mission bit "Low" */
  67. #define CMD_SET_TBIT (1 << 7)
  68. /* 1: open/drain */
  69. #define CMD_SET_OPDM (1 << 6)
  70. #define CMD_SET_CCSH (1 << 5)
  71. /* 1bit */
  72. #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0))
  73. /* 4bit */
  74. #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0))
  75. /* 8bit */
  76. #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0))
  77. /* CE_CMD_CTRL */
  78. #define CMD_CTRL_BREAK (1 << 0)
  79. /* CE_BLOCK_SET */
  80. #define BLOCK_SIZE_MASK 0x0000ffff
  81. /* CE_CLK_CTRL */
  82. #define CLK_ENABLE (1 << 24)
  83. #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
  84. #define CLK_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
  85. /* respons timeout */
  86. #define SRSPTO_256 ((1 << 13) | (0 << 12))
  87. /* respons busy timeout */
  88. #define SRBSYTO_29 ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
  89. /* read/write timeout */
  90. #define SRWDTO_29 ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
  91. /* ccs timeout */
  92. #define SCCSTO_29 ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0))
  93. /* CE_BUF_ACC */
  94. #define BUF_ACC_DMAWEN (1 << 25)
  95. #define BUF_ACC_DMAREN (1 << 24)
  96. #define BUF_ACC_BUSW_32 (0 << 17)
  97. #define BUF_ACC_BUSW_16 (1 << 17)
  98. #define BUF_ACC_ATYP (1 << 16)
  99. /* CE_INT */
  100. #define INT_CCSDE (1 << 29)
  101. #define INT_CMD12DRE (1 << 26)
  102. #define INT_CMD12RBE (1 << 25)
  103. #define INT_CMD12CRE (1 << 24)
  104. #define INT_DTRANE (1 << 23)
  105. #define INT_BUFRE (1 << 22)
  106. #define INT_BUFWEN (1 << 21)
  107. #define INT_BUFREN (1 << 20)
  108. #define INT_CCSRCV (1 << 19)
  109. #define INT_RBSYE (1 << 17)
  110. #define INT_CRSPE (1 << 16)
  111. #define INT_CMDVIO (1 << 15)
  112. #define INT_BUFVIO (1 << 14)
  113. #define INT_WDATERR (1 << 11)
  114. #define INT_RDATERR (1 << 10)
  115. #define INT_RIDXERR (1 << 9)
  116. #define INT_RSPERR (1 << 8)
  117. #define INT_CCSTO (1 << 5)
  118. #define INT_CRCSTO (1 << 4)
  119. #define INT_WDATTO (1 << 3)
  120. #define INT_RDATTO (1 << 2)
  121. #define INT_RBSYTO (1 << 1)
  122. #define INT_RSPTO (1 << 0)
  123. #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
  124. INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
  125. INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
  126. INT_RDATTO | INT_RBSYTO | INT_RSPTO)
  127. #define INT_START_MAGIC 0xD80430C0
  128. /* CE_INT_MASK */
  129. #define MASK_ALL 0x00000000
  130. #define MASK_MCCSDE (1 << 29)
  131. #define MASK_MCMD12DRE (1 << 26)
  132. #define MASK_MCMD12RBE (1 << 25)
  133. #define MASK_MCMD12CRE (1 << 24)
  134. #define MASK_MDTRANE (1 << 23)
  135. #define MASK_MBUFRE (1 << 22)
  136. #define MASK_MBUFWEN (1 << 21)
  137. #define MASK_MBUFREN (1 << 20)
  138. #define MASK_MCCSRCV (1 << 19)
  139. #define MASK_MRBSYE (1 << 17)
  140. #define MASK_MCRSPE (1 << 16)
  141. #define MASK_MCMDVIO (1 << 15)
  142. #define MASK_MBUFVIO (1 << 14)
  143. #define MASK_MWDATERR (1 << 11)
  144. #define MASK_MRDATERR (1 << 10)
  145. #define MASK_MRIDXERR (1 << 9)
  146. #define MASK_MRSPERR (1 << 8)
  147. #define MASK_MCCSTO (1 << 5)
  148. #define MASK_MCRCSTO (1 << 4)
  149. #define MASK_MWDATTO (1 << 3)
  150. #define MASK_MRDATTO (1 << 2)
  151. #define MASK_MRBSYTO (1 << 1)
  152. #define MASK_MRSPTO (1 << 0)
  153. /* CE_HOST_STS1 */
  154. #define STS1_CMDSEQ (1 << 31)
  155. /* CE_HOST_STS2 */
  156. #define STS2_CRCSTE (1 << 31)
  157. #define STS2_CRC16E (1 << 30)
  158. #define STS2_AC12CRCE (1 << 29)
  159. #define STS2_RSPCRC7E (1 << 28)
  160. #define STS2_CRCSTEBE (1 << 27)
  161. #define STS2_RDATEBE (1 << 26)
  162. #define STS2_AC12REBE (1 << 25)
  163. #define STS2_RSPEBE (1 << 24)
  164. #define STS2_AC12IDXE (1 << 23)
  165. #define STS2_RSPIDXE (1 << 22)
  166. #define STS2_CCSTO (1 << 15)
  167. #define STS2_RDATTO (1 << 14)
  168. #define STS2_DATBSYTO (1 << 13)
  169. #define STS2_CRCSTTO (1 << 12)
  170. #define STS2_AC12BSYTO (1 << 11)
  171. #define STS2_RSPBSYTO (1 << 10)
  172. #define STS2_AC12RSPTO (1 << 9)
  173. #define STS2_RSPTO (1 << 8)
  174. #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
  175. STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
  176. #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
  177. STS2_DATBSYTO | STS2_CRCSTTO | \
  178. STS2_AC12BSYTO | STS2_RSPBSYTO | \
  179. STS2_AC12RSPTO | STS2_RSPTO)
  180. /* CE_VERSION */
  181. #define SOFT_RST_ON (1 << 31)
  182. #define SOFT_RST_OFF (0 << 31)
  183. #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
  184. #ifdef CONFIG_ARCH_RMOBILE
  185. #define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9))
  186. #define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1))
  187. #else
  188. #define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8))
  189. #define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA
  190. #endif
  191. #define MMC_BUS_WIDTH_1 0
  192. #define MMC_BUS_WIDTH_4 2
  193. #define MMC_BUS_WIDTH_8 3
  194. struct sh_mmcif_host {
  195. struct mmc_data *data;
  196. struct sh_mmcif_regs *regs;
  197. unsigned int clk;
  198. int bus_width;
  199. u16 wait_int;
  200. u16 sd_error;
  201. u8 last_cmd;
  202. };
  203. static inline u32 sh_mmcif_read(unsigned long *reg)
  204. {
  205. return readl(reg);
  206. }
  207. static inline void sh_mmcif_write(u32 val, unsigned long *reg)
  208. {
  209. writel(val, reg);
  210. }
  211. static inline void sh_mmcif_bitset(u32 val, unsigned long *reg)
  212. {
  213. sh_mmcif_write(val | sh_mmcif_read(reg), reg);
  214. }
  215. static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg)
  216. {
  217. sh_mmcif_write(~val & sh_mmcif_read(reg), reg);
  218. }
  219. #endif /* _SH_MMCIF_H_ */