s5p_sdhci.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Jaehoon Chung <jh80.chung@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <sdhci.h>
  11. #include <fdtdec.h>
  12. #include <linux/libfdt.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/mmc.h>
  15. #include <asm/arch/clk.h>
  16. #include <errno.h>
  17. #include <asm/arch/pinmux.h>
  18. #ifdef CONFIG_DM_MMC
  19. struct s5p_sdhci_plat {
  20. struct mmc_config cfg;
  21. struct mmc mmc;
  22. };
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #endif
  25. static char *S5P_NAME = "SAMSUNG SDHCI";
  26. static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
  27. {
  28. unsigned long val, ctrl;
  29. /*
  30. * SELCLKPADDS[17:16]
  31. * 00 = 2mA
  32. * 01 = 4mA
  33. * 10 = 7mA
  34. * 11 = 9mA
  35. */
  36. sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
  37. val = sdhci_readl(host, SDHCI_CONTROL2);
  38. val &= SDHCI_CTRL2_SELBASECLK_MASK(3);
  39. val |= SDHCI_CTRL2_ENSTAASYNCCLR |
  40. SDHCI_CTRL2_ENCMDCNFMSK |
  41. SDHCI_CTRL2_ENFBCLKRX |
  42. SDHCI_CTRL2_ENCLKOUTHOLD;
  43. sdhci_writel(host, val, SDHCI_CONTROL2);
  44. /*
  45. * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
  46. * FCSel[1:0] : Rx Feedback Clock Delay Control
  47. * Inverter delay means10ns delay if SDCLK 50MHz setting
  48. * 01 = Delay1 (basic delay)
  49. * 11 = Delay2 (basic delay + 2ns)
  50. * 00 = Delay3 (inverter delay)
  51. * 10 = Delay4 (inverter delay + 2ns)
  52. */
  53. val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
  54. sdhci_writel(host, val, SDHCI_CONTROL3);
  55. /*
  56. * SELBASECLK[5:4]
  57. * 00/01 = HCLK
  58. * 10 = EPLL
  59. * 11 = XTI or XEXTCLK
  60. */
  61. ctrl = sdhci_readl(host, SDHCI_CONTROL2);
  62. ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
  63. ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
  64. sdhci_writel(host, ctrl, SDHCI_CONTROL2);
  65. }
  66. static void s5p_set_clock(struct sdhci_host *host, u32 div)
  67. {
  68. /* ToDo : Use the Clock Framework */
  69. set_mmc_clk(host->index, div);
  70. }
  71. static const struct sdhci_ops s5p_sdhci_ops = {
  72. .set_clock = &s5p_set_clock,
  73. .set_control_reg = &s5p_sdhci_set_control_reg,
  74. };
  75. static int s5p_sdhci_core_init(struct sdhci_host *host)
  76. {
  77. host->name = S5P_NAME;
  78. host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
  79. SDHCI_QUIRK_32BIT_DMA_ADDR |
  80. SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
  81. host->max_clk = 52000000;
  82. host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  83. host->ops = &s5p_sdhci_ops;
  84. if (host->bus_width == 8)
  85. host->host_caps |= MMC_MODE_8BIT;
  86. #ifndef CONFIG_BLK
  87. return add_sdhci(host, 0, 400000);
  88. #else
  89. return 0;
  90. #endif
  91. }
  92. int s5p_sdhci_init(u32 regbase, int index, int bus_width)
  93. {
  94. struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host));
  95. if (!host) {
  96. printf("sdhci__host allocation fail!\n");
  97. return -ENOMEM;
  98. }
  99. host->ioaddr = (void *)regbase;
  100. host->index = index;
  101. host->bus_width = bus_width;
  102. return s5p_sdhci_core_init(host);
  103. }
  104. static int do_sdhci_init(struct sdhci_host *host)
  105. {
  106. int dev_id, flag, ret;
  107. flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
  108. dev_id = host->index + PERIPH_ID_SDMMC0;
  109. ret = exynos_pinmux_config(dev_id, flag);
  110. if (ret) {
  111. printf("external SD not configured\n");
  112. return ret;
  113. }
  114. if (dm_gpio_is_valid(&host->pwr_gpio)) {
  115. dm_gpio_set_value(&host->pwr_gpio, 1);
  116. ret = exynos_pinmux_config(dev_id, flag);
  117. if (ret) {
  118. debug("MMC not configured\n");
  119. return ret;
  120. }
  121. }
  122. if (dm_gpio_is_valid(&host->cd_gpio)) {
  123. ret = dm_gpio_get_value(&host->cd_gpio);
  124. if (ret) {
  125. debug("no SD card detected (%d)\n", ret);
  126. return -ENODEV;
  127. }
  128. }
  129. return s5p_sdhci_core_init(host);
  130. }
  131. static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
  132. {
  133. int bus_width, dev_id;
  134. unsigned int base;
  135. /* Get device id */
  136. dev_id = pinmux_decode_periph_id(blob, node);
  137. if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) {
  138. debug("MMC: Can't get device id\n");
  139. return -EINVAL;
  140. }
  141. host->index = dev_id - PERIPH_ID_SDMMC0;
  142. /* Get bus width */
  143. bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
  144. if (bus_width <= 0) {
  145. debug("MMC: Can't get bus-width\n");
  146. return -EINVAL;
  147. }
  148. host->bus_width = bus_width;
  149. /* Get the base address from the device node */
  150. base = fdtdec_get_addr(blob, node, "reg");
  151. if (!base) {
  152. debug("MMC: Can't get base address\n");
  153. return -EINVAL;
  154. }
  155. host->ioaddr = (void *)base;
  156. gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0,
  157. &host->pwr_gpio, GPIOD_IS_OUT);
  158. gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0,
  159. &host->cd_gpio, GPIOD_IS_IN);
  160. return 0;
  161. }
  162. #ifdef CONFIG_DM_MMC
  163. static int s5p_sdhci_probe(struct udevice *dev)
  164. {
  165. struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
  166. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  167. struct sdhci_host *host = dev_get_priv(dev);
  168. int ret;
  169. ret = sdhci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
  170. if (ret)
  171. return ret;
  172. ret = do_sdhci_init(host);
  173. if (ret)
  174. return ret;
  175. ret = mmc_of_parse(dev, &plat->cfg);
  176. if (ret)
  177. return ret;
  178. host->mmc = &plat->mmc;
  179. host->mmc->dev = dev;
  180. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000);
  181. if (ret)
  182. return ret;
  183. host->mmc->priv = host;
  184. upriv->mmc = host->mmc;
  185. return sdhci_probe(dev);
  186. }
  187. static int s5p_sdhci_bind(struct udevice *dev)
  188. {
  189. struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
  190. int ret;
  191. ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
  192. if (ret)
  193. return ret;
  194. return 0;
  195. }
  196. static const struct udevice_id s5p_sdhci_ids[] = {
  197. { .compatible = "samsung,exynos4412-sdhci"},
  198. { }
  199. };
  200. U_BOOT_DRIVER(s5p_sdhci_drv) = {
  201. .name = "s5p_sdhci",
  202. .id = UCLASS_MMC,
  203. .of_match = s5p_sdhci_ids,
  204. .bind = s5p_sdhci_bind,
  205. .ops = &sdhci_ops,
  206. .probe = s5p_sdhci_probe,
  207. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  208. .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat),
  209. };
  210. #endif /* CONFIG_DM_MMC */