renesas-sdhi.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <bouncebuf.h>
  7. #include <clk.h>
  8. #include <fdtdec.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <mmc.h>
  12. #include <dm.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/bitops.h>
  15. #include <linux/compat.h>
  16. #include <linux/delay.h>
  17. #include <linux/dma-direction.h>
  18. #include <linux/io.h>
  19. #include <linux/sizes.h>
  20. #include <power/regulator.h>
  21. #include <asm/unaligned.h>
  22. #include "tmio-common.h"
  23. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  24. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  25. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  26. /* SCC registers */
  27. #define RENESAS_SDHI_SCC_DTCNTL 0x800
  28. #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
  29. #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
  30. #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
  31. #define RENESAS_SDHI_SCC_TAPSET 0x804
  32. #define RENESAS_SDHI_SCC_DT2FF 0x808
  33. #define RENESAS_SDHI_SCC_CKSEL 0x80c
  34. #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
  35. #define RENESAS_SDHI_SCC_RVSCNTL 0x810
  36. #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
  37. #define RENESAS_SDHI_SCC_RVSREQ 0x814
  38. #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
  39. #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
  40. #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
  41. #define RENESAS_SDHI_SCC_SMPCMP 0x818
  42. #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
  43. #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
  44. #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
  45. #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
  46. #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
  47. #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
  48. #define RENESAS_SDHI_SCC_TMPPORT3 0x828
  49. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
  50. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
  51. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
  52. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
  53. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
  54. #define RENESAS_SDHI_SCC_TMPPORT4 0x82c
  55. #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  56. #define RENESAS_SDHI_SCC_TMPPORT5 0x830
  57. #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
  58. #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
  59. #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
  60. #define RENESAS_SDHI_SCC_TMPPORT6 0x834
  61. #define RENESAS_SDHI_SCC_TMPPORT7 0x838
  62. #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
  63. #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
  64. #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
  65. #define RENESAS_SDHI_MAX_TAP 3
  66. #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
  67. static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
  68. { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
  69. 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
  70. { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
  71. 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
  72. };
  73. static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
  74. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
  75. 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
  76. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
  77. 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
  78. };
  79. static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
  80. { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
  81. 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
  82. { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
  83. 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
  84. };
  85. static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
  86. { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
  87. 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
  88. { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
  89. 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
  90. };
  91. static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
  92. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  93. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  94. { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
  95. 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
  96. };
  97. static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
  98. {
  99. /* On R-Car Gen3, MMC0 is at 0xee140000 */
  100. return (uintptr_t)(priv->regbase) == 0xee140000;
  101. }
  102. static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
  103. {
  104. /* read mode */
  105. tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
  106. (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  107. RENESAS_SDHI_SCC_TMPPORT5);
  108. /* access start and stop */
  109. tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  110. RENESAS_SDHI_SCC_TMPPORT4);
  111. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  112. return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
  113. }
  114. static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
  115. {
  116. /* write mode */
  117. tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
  118. (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  119. RENESAS_SDHI_SCC_TMPPORT5);
  120. tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
  121. /* access start and stop */
  122. tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  123. RENESAS_SDHI_SCC_TMPPORT4);
  124. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  125. }
  126. static bool renesas_sdhi_check_scc_error(struct udevice *dev)
  127. {
  128. struct tmio_sd_priv *priv = dev_get_priv(dev);
  129. struct mmc *mmc = mmc_get_mmc_dev(dev);
  130. unsigned long new_tap = priv->tap_set;
  131. unsigned long error_tap = priv->tap_set;
  132. u32 reg, smpcmp;
  133. if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
  134. (mmc->selected_mode != UHS_SDR104) &&
  135. (mmc->selected_mode != MMC_HS_200) &&
  136. (mmc->selected_mode != MMC_HS_400) &&
  137. (priv->nrtaps != 4))
  138. return false;
  139. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  140. /* Handle automatic tuning correction */
  141. if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
  142. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
  143. if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
  144. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
  145. return true;
  146. }
  147. return false;
  148. }
  149. /* Handle manual tuning correction */
  150. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
  151. if (!reg) /* No error */
  152. return false;
  153. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
  154. if (mmc->selected_mode == MMC_HS_400) {
  155. /*
  156. * Correction Error Status contains CMD and DAT signal status.
  157. * In HS400, DAT signal based on DS signal, not CLK.
  158. * Therefore, use only CMD status.
  159. */
  160. smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
  161. RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
  162. switch (smpcmp) {
  163. case 0:
  164. return false; /* No error in CMD signal */
  165. case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
  166. new_tap = (priv->tap_set +
  167. priv->tap_num + 1) % priv->tap_num;
  168. error_tap = (priv->tap_set +
  169. priv->tap_num - 1) % priv->tap_num;
  170. break;
  171. case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
  172. new_tap = (priv->tap_set +
  173. priv->tap_num - 1) % priv->tap_num;
  174. error_tap = (priv->tap_set +
  175. priv->tap_num + 1) % priv->tap_num;
  176. break;
  177. default:
  178. return true; /* Need re-tune */
  179. }
  180. if (priv->hs400_bad_tap & BIT(new_tap)) {
  181. /*
  182. * New tap is bad tap (cannot change).
  183. * Compare with HS200 tuning result.
  184. * In HS200 tuning, when smpcmp[error_tap]
  185. * is OK, retune is executed.
  186. */
  187. if (priv->smpcmp & BIT(error_tap))
  188. return true; /* Need retune */
  189. return false; /* cannot change */
  190. }
  191. priv->tap_set = new_tap;
  192. } else {
  193. if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
  194. return true; /* Need re-tune */
  195. else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
  196. priv->tap_set = (priv->tap_set +
  197. priv->tap_num + 1) % priv->tap_num;
  198. else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
  199. priv->tap_set = (priv->tap_set +
  200. priv->tap_num - 1) % priv->tap_num;
  201. else
  202. return false;
  203. }
  204. /* Set TAP position */
  205. tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
  206. RENESAS_SDHI_SCC_TAPSET);
  207. return false;
  208. }
  209. static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
  210. {
  211. u32 calib_code;
  212. if (!priv->adjust_hs400_enable)
  213. return;
  214. if (!priv->needs_adjust_hs400)
  215. return;
  216. if (!priv->adjust_hs400_calib_table)
  217. return;
  218. /*
  219. * Enabled Manual adjust HS400 mode
  220. *
  221. * 1) Disabled Write Protect
  222. * W(addr=0x00, WP_DISABLE_CODE)
  223. *
  224. * 2) Read Calibration code
  225. * read_value = R(addr=0x26)
  226. * 3) Refer to calibration table
  227. * Calibration code = table[read_value]
  228. * 4) Enabled Manual Calibration
  229. * W(addr=0x22, manual mode | Calibration code)
  230. * 5) Set Offset value to TMPPORT3 Reg
  231. */
  232. sd_scc_tmpport_write32(priv, 0x00,
  233. RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
  234. calib_code = sd_scc_tmpport_read32(priv, 0x26);
  235. calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
  236. sd_scc_tmpport_write32(priv, 0x22,
  237. RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
  238. priv->adjust_hs400_calib_table[calib_code]);
  239. tmio_sd_writel(priv, priv->adjust_hs400_offset,
  240. RENESAS_SDHI_SCC_TMPPORT3);
  241. /* Clear flag */
  242. priv->needs_adjust_hs400 = false;
  243. }
  244. static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
  245. {
  246. /* Disabled Manual adjust HS400 mode
  247. *
  248. * 1) Disabled Write Protect
  249. * W(addr=0x00, WP_DISABLE_CODE)
  250. * 2) Disabled Manual Calibration
  251. * W(addr=0x22, 0)
  252. * 3) Clear offset value to TMPPORT3 Reg
  253. */
  254. sd_scc_tmpport_write32(priv, 0x00,
  255. RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
  256. sd_scc_tmpport_write32(priv, 0x22, 0);
  257. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
  258. }
  259. static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
  260. {
  261. u32 reg;
  262. /* Initialize SCC */
  263. tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  264. reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  265. reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  266. tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  267. /* Set sampling clock selection range */
  268. tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
  269. RENESAS_SDHI_SCC_DTCNTL_TAPEN,
  270. RENESAS_SDHI_SCC_DTCNTL);
  271. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  272. reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
  273. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  274. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  275. reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  276. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  277. tmio_sd_writel(priv, 0x300 /* scc_tappos */,
  278. RENESAS_SDHI_SCC_DT2FF);
  279. reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  280. reg |= TMIO_SD_CLKCTL_SCLKEN;
  281. tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  282. /* Read TAPNUM */
  283. return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
  284. RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
  285. RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
  286. }
  287. static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
  288. {
  289. u32 reg;
  290. /* Reset SCC */
  291. reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  292. reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  293. tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  294. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  295. reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
  296. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  297. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
  298. reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  299. RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
  300. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
  301. /* Disable HS400 mode adjustment */
  302. renesas_sdhi_adjust_hs400_mode_disable(priv);
  303. reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  304. reg |= TMIO_SD_CLKCTL_SCLKEN;
  305. tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  306. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  307. reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  308. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  309. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  310. reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  311. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  312. }
  313. static int renesas_sdhi_hs400(struct udevice *dev)
  314. {
  315. struct tmio_sd_priv *priv = dev_get_priv(dev);
  316. struct mmc *mmc = mmc_get_mmc_dev(dev);
  317. bool hs400 = (mmc->selected_mode == MMC_HS_400);
  318. int ret, taps = hs400 ? priv->nrtaps : 8;
  319. unsigned long new_tap;
  320. u32 reg;
  321. if (taps == 4) /* HS400 on 4tap SoC needs different clock */
  322. ret = clk_set_rate(&priv->clk, 400000000);
  323. else
  324. ret = clk_set_rate(&priv->clk, 200000000);
  325. if (ret < 0)
  326. return ret;
  327. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  328. reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  329. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  330. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
  331. if (hs400) {
  332. reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  333. RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
  334. } else {
  335. reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  336. RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
  337. }
  338. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
  339. /* Disable HS400 mode adjustment */
  340. if (!hs400)
  341. renesas_sdhi_adjust_hs400_mode_disable(priv);
  342. tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
  343. RENESAS_SDHI_SCC_DTCNTL_TAPEN,
  344. RENESAS_SDHI_SCC_DTCNTL);
  345. /* Avoid bad TAP */
  346. if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
  347. new_tap = (priv->tap_set +
  348. priv->tap_num + 1) % priv->tap_num;
  349. if (priv->hs400_bad_tap & BIT(new_tap))
  350. new_tap = (priv->tap_set +
  351. priv->tap_num - 1) % priv->tap_num;
  352. if (priv->hs400_bad_tap & BIT(new_tap)) {
  353. new_tap = priv->tap_set;
  354. debug("Three consecutive bad tap is prohibited\n");
  355. }
  356. priv->tap_set = new_tap;
  357. tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
  358. }
  359. if (taps == 4) {
  360. tmio_sd_writel(priv, priv->tap_set >> 1,
  361. RENESAS_SDHI_SCC_TAPSET);
  362. tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
  363. RENESAS_SDHI_SCC_DT2FF);
  364. } else {
  365. tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
  366. tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
  367. }
  368. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  369. reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
  370. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  371. /* Execute adjust hs400 offset after setting to HS400 mode */
  372. if (hs400)
  373. priv->needs_adjust_hs400 = true;
  374. return 0;
  375. }
  376. static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
  377. unsigned long tap)
  378. {
  379. /* Set sampling clock position */
  380. tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
  381. }
  382. static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
  383. {
  384. /* Get comparison of sampling data */
  385. return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
  386. }
  387. static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
  388. unsigned int taps)
  389. {
  390. unsigned long tap_cnt; /* counter of tuning success */
  391. unsigned long tap_start;/* start position of tuning success */
  392. unsigned long tap_end; /* end position of tuning success */
  393. unsigned long ntap; /* temporary counter of tuning success */
  394. unsigned long match_cnt;/* counter of matching data */
  395. unsigned long i;
  396. bool select = false;
  397. u32 reg;
  398. priv->needs_adjust_hs400 = false;
  399. /* Clear SCC_RVSREQ */
  400. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
  401. /* Merge the results */
  402. for (i = 0; i < priv->tap_num * 2; i++) {
  403. if (!(taps & BIT(i))) {
  404. taps &= ~BIT(i % priv->tap_num);
  405. taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
  406. }
  407. if (!(priv->smpcmp & BIT(i))) {
  408. priv->smpcmp &= ~BIT(i % priv->tap_num);
  409. priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
  410. }
  411. }
  412. /*
  413. * Find the longest consecutive run of successful probes. If that
  414. * is more than RENESAS_SDHI_MAX_TAP probes long then use the
  415. * center index as the tap.
  416. */
  417. tap_cnt = 0;
  418. ntap = 0;
  419. tap_start = 0;
  420. tap_end = 0;
  421. for (i = 0; i < priv->tap_num * 2; i++) {
  422. if (taps & BIT(i))
  423. ntap++;
  424. else {
  425. if (ntap > tap_cnt) {
  426. tap_start = i - ntap;
  427. tap_end = i - 1;
  428. tap_cnt = ntap;
  429. }
  430. ntap = 0;
  431. }
  432. }
  433. if (ntap > tap_cnt) {
  434. tap_start = i - ntap;
  435. tap_end = i - 1;
  436. tap_cnt = ntap;
  437. }
  438. /*
  439. * If all of the TAP is OK, the sampling clock position is selected by
  440. * identifying the change point of data.
  441. */
  442. if (tap_cnt == priv->tap_num * 2) {
  443. match_cnt = 0;
  444. ntap = 0;
  445. tap_start = 0;
  446. tap_end = 0;
  447. for (i = 0; i < priv->tap_num * 2; i++) {
  448. if (priv->smpcmp & BIT(i))
  449. ntap++;
  450. else {
  451. if (ntap > match_cnt) {
  452. tap_start = i - ntap;
  453. tap_end = i - 1;
  454. match_cnt = ntap;
  455. }
  456. ntap = 0;
  457. }
  458. }
  459. if (ntap > match_cnt) {
  460. tap_start = i - ntap;
  461. tap_end = i - 1;
  462. match_cnt = ntap;
  463. }
  464. if (match_cnt)
  465. select = true;
  466. } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
  467. select = true;
  468. if (select)
  469. priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
  470. else
  471. return -EIO;
  472. /* Set SCC */
  473. tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
  474. /* Enable auto re-tuning */
  475. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  476. reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  477. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  478. return 0;
  479. }
  480. int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
  481. {
  482. struct tmio_sd_priv *priv = dev_get_priv(dev);
  483. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  484. struct mmc *mmc = upriv->mmc;
  485. unsigned int tap_num;
  486. unsigned int taps = 0;
  487. int i, ret = 0;
  488. u32 caps;
  489. /* Only supported on Renesas RCar */
  490. if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
  491. return -EINVAL;
  492. /* clock tuning is not needed for upto 52MHz */
  493. if (!((mmc->selected_mode == MMC_HS_200) ||
  494. (mmc->selected_mode == MMC_HS_400) ||
  495. (mmc->selected_mode == UHS_SDR104) ||
  496. (mmc->selected_mode == UHS_SDR50)))
  497. return 0;
  498. tap_num = renesas_sdhi_init_tuning(priv);
  499. if (!tap_num)
  500. /* Tuning is not supported */
  501. goto out;
  502. priv->tap_num = tap_num;
  503. if (priv->tap_num * 2 >= sizeof(taps) * 8) {
  504. dev_err(dev,
  505. "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
  506. goto out;
  507. }
  508. priv->smpcmp = 0;
  509. /* Issue CMD19 twice for each tap */
  510. for (i = 0; i < 2 * priv->tap_num; i++) {
  511. renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
  512. /* Force PIO for the tuning */
  513. caps = priv->caps;
  514. priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
  515. ret = mmc_send_tuning(mmc, opcode, NULL);
  516. priv->caps = caps;
  517. if (ret == 0)
  518. taps |= BIT(i);
  519. ret = renesas_sdhi_compare_scc_data(priv);
  520. if (ret == 0)
  521. priv->smpcmp |= BIT(i);
  522. mdelay(1);
  523. }
  524. ret = renesas_sdhi_select_tuning(priv, taps);
  525. out:
  526. if (ret < 0) {
  527. dev_warn(dev, "Tuning procedure failed\n");
  528. renesas_sdhi_reset_tuning(priv);
  529. }
  530. return ret;
  531. }
  532. #else
  533. static int renesas_sdhi_hs400(struct udevice *dev)
  534. {
  535. return 0;
  536. }
  537. #endif
  538. static int renesas_sdhi_set_ios(struct udevice *dev)
  539. {
  540. struct tmio_sd_priv *priv = dev_get_priv(dev);
  541. u32 tmp;
  542. int ret;
  543. /* Stop the clock before changing its rate to avoid a glitch signal */
  544. tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  545. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  546. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  547. ret = renesas_sdhi_hs400(dev);
  548. if (ret)
  549. return ret;
  550. ret = tmio_sd_set_ios(dev);
  551. mdelay(10);
  552. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  553. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  554. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  555. struct mmc *mmc = mmc_get_mmc_dev(dev);
  556. if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
  557. (mmc->selected_mode != UHS_SDR104) &&
  558. (mmc->selected_mode != MMC_HS_200) &&
  559. (mmc->selected_mode != MMC_HS_400)) {
  560. renesas_sdhi_reset_tuning(priv);
  561. }
  562. #endif
  563. return ret;
  564. }
  565. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  566. static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
  567. int timeout_us)
  568. {
  569. int ret = -ETIMEDOUT;
  570. bool dat0_high;
  571. bool target_dat0_high = !!state;
  572. struct tmio_sd_priv *priv = dev_get_priv(dev);
  573. timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
  574. while (timeout_us--) {
  575. dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
  576. if (dat0_high == target_dat0_high) {
  577. ret = 0;
  578. break;
  579. }
  580. udelay(10);
  581. }
  582. return ret;
  583. }
  584. #endif
  585. #define RENESAS_SDHI_DMA_ALIGNMENT 128
  586. static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
  587. size_t len, size_t len_aligned)
  588. {
  589. /* Check if start is aligned */
  590. if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
  591. debug("Unaligned buffer address %lx\n", ubuf);
  592. return 0;
  593. }
  594. /* Check if length is aligned */
  595. if (len != len_aligned) {
  596. debug("Unaligned buffer length %zu\n", len);
  597. return 0;
  598. }
  599. #ifdef CONFIG_PHYS_64BIT
  600. /* Check if below 32bit boundary */
  601. if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
  602. debug("Buffer above 32bit boundary %lx-%lx\n",
  603. ubuf, ubuf + len_aligned);
  604. return 0;
  605. }
  606. #endif
  607. /* Aligned */
  608. return 1;
  609. }
  610. static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
  611. {
  612. uintptr_t ubuf = (uintptr_t)state->user_buffer;
  613. return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
  614. state->len_aligned);
  615. }
  616. static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  617. struct mmc_data *data)
  618. {
  619. struct bounce_buffer bbstate;
  620. unsigned int bbflags;
  621. bool bbok = false;
  622. size_t len;
  623. void *buf;
  624. int ret;
  625. if (data) {
  626. if (data->flags & MMC_DATA_READ) {
  627. buf = data->dest;
  628. bbflags = GEN_BB_WRITE;
  629. } else {
  630. buf = (void *)data->src;
  631. bbflags = GEN_BB_READ;
  632. }
  633. len = data->blocks * data->blocksize;
  634. ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
  635. RENESAS_SDHI_DMA_ALIGNMENT,
  636. renesas_sdhi_addr_aligned);
  637. /*
  638. * If the amount of data to transfer is too large, we can get
  639. * -ENOMEM when starting the bounce buffer. If that happens,
  640. * fall back to PIO as it was before, otherwise use the BB.
  641. */
  642. if (!ret) {
  643. bbok = true;
  644. if (data->flags & MMC_DATA_READ)
  645. data->dest = bbstate.bounce_buffer;
  646. else
  647. data->src = bbstate.bounce_buffer;
  648. }
  649. }
  650. ret = tmio_sd_send_cmd(dev, cmd, data);
  651. if (data && bbok) {
  652. buf = bbstate.user_buffer;
  653. bounce_buffer_stop(&bbstate);
  654. if (data->flags & MMC_DATA_READ)
  655. data->dest = buf;
  656. else
  657. data->src = buf;
  658. }
  659. if (ret)
  660. return ret;
  661. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  662. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  663. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  664. struct tmio_sd_priv *priv = dev_get_priv(dev);
  665. renesas_sdhi_check_scc_error(dev);
  666. if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
  667. renesas_sdhi_adjust_hs400_mode_enable(priv);
  668. #endif
  669. return 0;
  670. }
  671. int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
  672. {
  673. struct tmio_sd_priv *priv = dev_get_priv(dev);
  674. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  675. struct mmc *mmc = upriv->mmc;
  676. size_t len = blkcnt * mmc->read_bl_len;
  677. size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
  678. if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
  679. if (priv->quirks & TMIO_SD_CAP_16BIT)
  680. return U16_MAX;
  681. else
  682. return U32_MAX;
  683. } else {
  684. return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
  685. }
  686. }
  687. static const struct dm_mmc_ops renesas_sdhi_ops = {
  688. .send_cmd = renesas_sdhi_send_cmd,
  689. .set_ios = renesas_sdhi_set_ios,
  690. .get_cd = tmio_sd_get_cd,
  691. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  692. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  693. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  694. .execute_tuning = renesas_sdhi_execute_tuning,
  695. #endif
  696. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  697. .wait_dat0 = renesas_sdhi_wait_dat0,
  698. #endif
  699. .get_b_max = renesas_sdhi_get_b_max,
  700. };
  701. #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
  702. #define RENESAS_GEN3_QUIRKS \
  703. TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
  704. static const struct udevice_id renesas_sdhi_match[] = {
  705. { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
  706. { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
  707. { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
  708. { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
  709. { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
  710. { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
  711. { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
  712. { .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
  713. { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
  714. { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
  715. { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
  716. { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
  717. { /* sentinel */ }
  718. };
  719. static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
  720. {
  721. return clk_get_rate(&priv->clk);
  722. }
  723. static void renesas_sdhi_filter_caps(struct udevice *dev)
  724. {
  725. struct tmio_sd_priv *priv = dev_get_priv(dev);
  726. if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
  727. return;
  728. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  729. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  730. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  731. struct tmio_sd_plat *plat = dev_get_platdata(dev);
  732. /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
  733. if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  734. (rmobile_get_cpu_rev_integer() <= 1)) ||
  735. ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  736. (rmobile_get_cpu_rev_integer() == 1) &&
  737. (rmobile_get_cpu_rev_fraction() < 2)))
  738. plat->cfg.host_caps &= ~MMC_MODE_HS400;
  739. /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
  740. if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  741. (rmobile_get_cpu_rev_integer() >= 2)) ||
  742. ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  743. (rmobile_get_cpu_rev_integer() == 1) &&
  744. (rmobile_get_cpu_rev_fraction() == 2)) ||
  745. (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
  746. priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
  747. /* H3 ES3.0 can use HS400 with manual adjustment */
  748. if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  749. (rmobile_get_cpu_rev_integer() >= 3)) {
  750. priv->adjust_hs400_enable = true;
  751. priv->adjust_hs400_offset = 0;
  752. priv->adjust_hs400_calib_table =
  753. r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
  754. }
  755. /* M3W ES1.2 can use HS400 with manual adjustment */
  756. if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  757. (rmobile_get_cpu_rev_integer() == 1) &&
  758. (rmobile_get_cpu_rev_fraction() == 2)) {
  759. priv->adjust_hs400_enable = true;
  760. priv->adjust_hs400_offset = 3;
  761. priv->adjust_hs400_calib_table =
  762. r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
  763. }
  764. /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
  765. if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  766. (rmobile_get_cpu_rev_integer() == 1) &&
  767. (rmobile_get_cpu_rev_fraction() > 2)) {
  768. priv->adjust_hs400_enable = true;
  769. priv->adjust_hs400_offset = 0;
  770. priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
  771. priv->adjust_hs400_calib_table =
  772. r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
  773. }
  774. /* M3N can use HS400 with manual adjustment */
  775. if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
  776. priv->adjust_hs400_enable = true;
  777. priv->adjust_hs400_offset = 3;
  778. priv->adjust_hs400_calib_table =
  779. r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
  780. }
  781. /* E3 can use HS400 with manual adjustment */
  782. if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
  783. priv->adjust_hs400_enable = true;
  784. priv->adjust_hs400_offset = 3;
  785. priv->adjust_hs400_calib_table =
  786. r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
  787. }
  788. /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
  789. if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  790. (rmobile_get_cpu_rev_integer() <= 2)) ||
  791. ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  792. (rmobile_get_cpu_rev_integer() == 1) &&
  793. (rmobile_get_cpu_rev_fraction() <= 2)))
  794. priv->nrtaps = 4;
  795. else
  796. priv->nrtaps = 8;
  797. #endif
  798. /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
  799. if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  800. (rmobile_get_cpu_rev_integer() <= 1)) ||
  801. ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  802. (rmobile_get_cpu_rev_integer() == 1) &&
  803. (rmobile_get_cpu_rev_fraction() == 0)))
  804. priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
  805. else
  806. priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
  807. }
  808. static int renesas_sdhi_probe(struct udevice *dev)
  809. {
  810. struct tmio_sd_priv *priv = dev_get_priv(dev);
  811. u32 quirks = dev_get_driver_data(dev);
  812. struct fdt_resource reg_res;
  813. DECLARE_GLOBAL_DATA_PTR;
  814. int ret;
  815. priv->clk_get_rate = renesas_sdhi_clk_get_rate;
  816. if (quirks == RENESAS_GEN2_QUIRKS) {
  817. ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
  818. "reg", 0, &reg_res);
  819. if (ret < 0) {
  820. dev_err(dev, "\"reg\" resource not found, ret=%i\n",
  821. ret);
  822. return ret;
  823. }
  824. if (fdt_resource_size(&reg_res) == 0x100)
  825. quirks |= TMIO_SD_CAP_16BIT;
  826. }
  827. ret = clk_get_by_index(dev, 0, &priv->clk);
  828. if (ret < 0) {
  829. dev_err(dev, "failed to get host clock\n");
  830. return ret;
  831. }
  832. /* set to max rate */
  833. ret = clk_set_rate(&priv->clk, 200000000);
  834. if (ret < 0) {
  835. dev_err(dev, "failed to set rate for host clock\n");
  836. clk_free(&priv->clk);
  837. return ret;
  838. }
  839. ret = clk_enable(&priv->clk);
  840. if (ret) {
  841. dev_err(dev, "failed to enable host clock\n");
  842. return ret;
  843. }
  844. priv->quirks = quirks;
  845. ret = tmio_sd_probe(dev, quirks);
  846. renesas_sdhi_filter_caps(dev);
  847. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  848. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  849. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  850. if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
  851. renesas_sdhi_reset_tuning(priv);
  852. #endif
  853. return ret;
  854. }
  855. U_BOOT_DRIVER(renesas_sdhi) = {
  856. .name = "renesas-sdhi",
  857. .id = UCLASS_MMC,
  858. .of_match = renesas_sdhi_match,
  859. .bind = tmio_sd_bind,
  860. .probe = renesas_sdhi_probe,
  861. .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
  862. .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
  863. .ops = &renesas_sdhi_ops,
  864. };