octeontx_hsmmc.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2019 Marvell International Ltd.
  4. *
  5. * https://spdx.org/licenses
  6. */
  7. #ifndef __OCTEONTX_HSMMC_H__
  8. #define __OCTEONTX_HSMMC_H__
  9. #include <asm/gpio.h>
  10. /** Name of our driver */
  11. #define OCTEONTX_MMC_DRIVER_NAME "octeontx-hsmmc"
  12. /** Maximum supported MMC slots */
  13. #define OCTEONTX_MAX_MMC_SLOT 3
  14. #define POWER_ON_TIME 40 /** See SD 4.1 spec figure 6-5 */
  15. /**
  16. * Timeout used when waiting for commands to complete. We need to keep this
  17. * above the hardware watchdog timeout which is usually limited to 1000ms
  18. */
  19. #define WATCHDOG_COUNT (1100) /* in msecs */
  20. /**
  21. * Long timeout for commands which might take a while to complete.
  22. */
  23. #define MMC_TIMEOUT_LONG 1000
  24. /**
  25. * Short timeout used for most commands in msecs
  26. */
  27. #define MMC_TIMEOUT_SHORT 20
  28. #define NSEC_PER_SEC 1000000000L
  29. #define MAX_NO_OF_TAPS 64
  30. #define EXT_CSD_POWER_CLASS 187 /* R/W */
  31. /* default HS400 tuning block number */
  32. #define DEFAULT_HS400_TUNING_BLOCK 1
  33. struct octeontx_mmc_host;
  34. /** MMC/SD slot data structure */
  35. struct octeontx_mmc_slot {
  36. struct mmc mmc;
  37. struct mmc_config cfg;
  38. struct octeontx_mmc_host *host;
  39. struct udevice *dev;
  40. void *base_addr; /** Same as host base_addr */
  41. u64 clock;
  42. int bus_id; /** slot number */
  43. uint bus_width;
  44. uint max_width;
  45. int hs200_tap_adj;
  46. int hs400_tap_adj;
  47. int hs400_tuning_block;
  48. struct gpio_desc cd_gpio;
  49. struct gpio_desc wp_gpio;
  50. struct gpio_desc power_gpio;
  51. enum bus_mode mode;
  52. union mio_emm_switch cached_switch;
  53. union mio_emm_switch want_switch;
  54. union mio_emm_rca cached_rca;
  55. union mio_emm_timing taps; /* otx2: MIO_EMM_TIMING */
  56. union mio_emm_timing hs200_taps;
  57. union mio_emm_timing hs400_taps;
  58. /* These are used to see if our tuning is still valid or not */
  59. enum bus_mode last_mode;
  60. u32 last_clock;
  61. u32 block_len;
  62. u32 block_count;
  63. int cmd_clk_skew;
  64. int dat_clk_skew;
  65. uint cmd_cnt; /* otx: sample cmd in delay */
  66. uint dat_cnt; /* otx: sample data in delay */
  67. uint drive; /* Current drive */
  68. uint slew; /* clock skew */
  69. uint cmd_out_hs200_delay;
  70. uint data_out_hs200_delay;
  71. uint cmd_out_hs400_delay;
  72. uint data_out_hs400_delay;
  73. uint clk_period;
  74. bool valid:1;
  75. bool is_acmd:1;
  76. bool tuned:1;
  77. bool hs200_tuned:1;
  78. bool hs400_tuned:1;
  79. bool is_1_8v:1;
  80. bool is_3_3v:1;
  81. bool is_ddr:1;
  82. bool is_asim:1;
  83. bool is_emul:1;
  84. bool cd_inverted:1;
  85. bool wp_inverted:1;
  86. bool disable_ddr:1;
  87. bool non_removable:1;
  88. };
  89. struct octeontx_mmc_cr_mods {
  90. u8 ctype_xor;
  91. u8 rtype_xor;
  92. };
  93. struct octeontx_mmc_cr {
  94. u8 c;
  95. u8 r;
  96. };
  97. struct octeontx_sd_mods {
  98. struct octeontx_mmc_cr mmc;
  99. struct octeontx_mmc_cr sd;
  100. struct octeontx_mmc_cr sdacmd;
  101. };
  102. /** Host controller data structure */
  103. struct octeontx_mmc_host {
  104. struct udevice *dev;
  105. void *base_addr;
  106. struct octeontx_mmc_slot slots[OCTEONTX_MAX_MMC_SLOT + 1];
  107. pci_dev_t pdev;
  108. u64 sys_freq;
  109. union mio_emm_cfg emm_cfg;
  110. u64 timing_taps;
  111. struct mmc *last_mmc; /** Last mmc used */
  112. ofnode node;
  113. int cur_slotid;
  114. int last_slotid;
  115. int max_width;
  116. uint per_tap_delay;
  117. uint num_slots;
  118. uint dma_wait_delay; /* Delay before polling DMA in usecs */
  119. bool initialized:1;
  120. bool timing_calibrated:1;
  121. bool is_asim:1;
  122. bool is_emul:1;
  123. bool calibrate_glitch:1;
  124. bool cond_clock_glitch:1;
  125. bool tap_requires_noclk:1;
  126. bool hs400_skew_needed:1;
  127. };
  128. /*
  129. * NOTE: This was copied from the Linux kernel.
  130. *
  131. * MMC status in R1, for native mode (SPI bits are different)
  132. * Type
  133. * e:error bit
  134. * s:status bit
  135. * r:detected and set for the actual command response
  136. * x:detected and set during command execution. the host must poll
  137. * the card by sending status command in order to read these bits.
  138. * Clear condition
  139. * a:according to the card state
  140. * b:always related to the previous command. Reception of
  141. * a valid command will clear it (with a delay of one command)
  142. * c:clear by read
  143. */
  144. #define R1_OUT_OF_RANGE BIT(31) /* er, c */
  145. #define R1_ADDRESS_ERROR BIT(30) /* erx, c */
  146. #define R1_BLOCK_LEN_ERROR BIT(29) /* er, c */
  147. #define R1_ERASE_SEQ_ERROR BIT(28) /* er, c */
  148. #define R1_ERASE_PARAM BIT(27) /* ex, c */
  149. #define R1_WP_VIOLATION BIT(26) /* erx, c */
  150. #define R1_CARD_IS_LOCKED BIT(25) /* sx, a */
  151. #define R1_LOCK_UNLOCK_FAILED BIT(24) /* erx, c */
  152. #define R1_COM_CRC_ERROR BIT(23) /* er, b */
  153. /*#define R1_ILLEGAL_COMMAND BIT(22)*/ /* er, b */
  154. #define R1_CARD_ECC_FAILED BIT(21) /* ex, c */
  155. #define R1_CC_ERROR BIT(20) /* erx, c */
  156. #define R1_ERROR BIT(19) /* erx, c */
  157. #define R1_UNDERRUN BIT(18) /* ex, c */
  158. #define R1_OVERRUN BIT(17) /* ex, c */
  159. #define R1_CID_CSD_OVERWRITE BIT(16) /* erx, c, CID/CSD overwrite */
  160. #define R1_WP_ERASE_SKIP BIT(15) /* sx, c */
  161. #define R1_CARD_ECC_DISABLED BIT(14) /* sx, a */
  162. #define R1_ERASE_RESET BIT(13) /* sr, c */
  163. #define R1_STATUS(x) ((x) & 0xFFFFE000)
  164. #define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */
  165. #define R1_READY_FOR_DATA BIT(8) /* sx, a */
  166. #define R1_SWITCH_ERROR BIT(7) /* sx, c */
  167. #define R1_BLOCK_READ_MASK R1_OUT_OF_RANGE | \
  168. R1_ADDRESS_ERROR | \
  169. R1_BLOCK_LEN_ERROR | \
  170. R1_CARD_IS_LOCKED | \
  171. R1_COM_CRC_ERROR | \
  172. R1_ILLEGAL_COMMAND | \
  173. R1_CARD_ECC_FAILED | \
  174. R1_CC_ERROR | \
  175. R1_ERROR
  176. #define R1_BLOCK_WRITE_MASK R1_OUT_OF_RANGE | \
  177. R1_ADDRESS_ERROR | \
  178. R1_BLOCK_LEN_ERROR | \
  179. R1_WP_VIOLATION | \
  180. R1_CARD_IS_LOCKED | \
  181. R1_COM_CRC_ERROR | \
  182. R1_ILLEGAL_COMMAND | \
  183. R1_CARD_ECC_FAILED | \
  184. R1_CC_ERROR | \
  185. R1_ERROR | \
  186. R1_UNDERRUN | \
  187. R1_OVERRUN
  188. #endif /* __OCTEONTX_HSMMC_H__ */