mxsmmc.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 SSP MMC driver
  4. *
  5. * Copyright (C) 2019 DENX Software Engineering
  6. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  7. *
  8. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  9. * on behalf of DENX Software Engineering GmbH
  10. *
  11. * Based on code from LTIB:
  12. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  13. * Terry Lv
  14. *
  15. * Copyright 2007, Freescale Semiconductor, Inc
  16. * Andy Fleming
  17. *
  18. * Based vaguely on the pxa mmc code:
  19. * (C) Copyright 2003
  20. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  21. */
  22. #include <common.h>
  23. #include <log.h>
  24. #include <malloc.h>
  25. #include <mmc.h>
  26. #include <linux/bitops.h>
  27. #include <linux/delay.h>
  28. #include <linux/errno.h>
  29. #include <asm/io.h>
  30. #include <asm/arch/clock.h>
  31. #include <asm/arch/imx-regs.h>
  32. #include <asm/arch/sys_proto.h>
  33. #include <asm/mach-imx/dma.h>
  34. #include <bouncebuf.h>
  35. #define MXSMMC_MAX_TIMEOUT 10000
  36. #define MXSMMC_SMALL_TRANSFER 512
  37. #if !CONFIG_IS_ENABLED(DM_MMC)
  38. struct mxsmmc_priv {
  39. int id;
  40. int (*mmc_is_wp)(int);
  41. int (*mmc_cd)(int);
  42. struct mmc_config cfg; /* mmc configuration */
  43. struct mxs_dma_desc *desc;
  44. uint32_t buswidth;
  45. struct mxs_ssp_regs *regs;
  46. };
  47. #else /* CONFIG_IS_ENABLED(DM_MMC) */
  48. #include <dm/device.h>
  49. #include <dm/read.h>
  50. #include <dt-structs.h>
  51. struct mxsmmc_platdata {
  52. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  53. struct dtd_fsl_imx23_mmc dtplat;
  54. #endif
  55. struct mmc_config cfg;
  56. struct mmc mmc;
  57. fdt_addr_t base;
  58. int non_removable;
  59. int buswidth;
  60. int dma_id;
  61. int clk_id;
  62. };
  63. struct mxsmmc_priv {
  64. int clkid;
  65. struct mxs_dma_desc *desc;
  66. u32 buswidth;
  67. struct mxs_ssp_regs *regs;
  68. unsigned int dma_channel;
  69. };
  70. #endif
  71. #if !CONFIG_IS_ENABLED(DM_MMC)
  72. static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  73. struct mmc_data *data);
  74. static int mxsmmc_cd(struct mxsmmc_priv *priv)
  75. {
  76. struct mxs_ssp_regs *ssp_regs = priv->regs;
  77. if (priv->mmc_cd)
  78. return priv->mmc_cd(priv->id);
  79. return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  80. }
  81. static int mxsmmc_set_ios(struct mmc *mmc)
  82. {
  83. struct mxsmmc_priv *priv = mmc->priv;
  84. struct mxs_ssp_regs *ssp_regs = priv->regs;
  85. /* Set the clock speed */
  86. if (mmc->clock)
  87. mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
  88. switch (mmc->bus_width) {
  89. case 1:
  90. priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
  91. break;
  92. case 4:
  93. priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
  94. break;
  95. case 8:
  96. priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
  97. break;
  98. }
  99. /* Set the bus width */
  100. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  101. SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
  102. debug("MMC%d: Set %d bits bus width\n",
  103. mmc->block_dev.devnum, mmc->bus_width);
  104. return 0;
  105. }
  106. static int mxsmmc_init(struct mmc *mmc)
  107. {
  108. struct mxsmmc_priv *priv = mmc->priv;
  109. struct mxs_ssp_regs *ssp_regs = priv->regs;
  110. /* Reset SSP */
  111. mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  112. /* Reconfigure the SSP block for MMC operation */
  113. writel(SSP_CTRL1_SSP_MODE_SD_MMC |
  114. SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
  115. SSP_CTRL1_DMA_ENABLE |
  116. SSP_CTRL1_POLARITY |
  117. SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  118. SSP_CTRL1_DATA_CRC_IRQ_EN |
  119. SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  120. SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  121. SSP_CTRL1_RESP_ERR_IRQ_EN,
  122. &ssp_regs->hw_ssp_ctrl1_set);
  123. /* Set initial bit clock 400 KHz */
  124. mxs_set_ssp_busclock(priv->id, 400);
  125. /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
  126. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
  127. udelay(200);
  128. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
  129. return 0;
  130. }
  131. static const struct mmc_ops mxsmmc_ops = {
  132. .send_cmd = mxsmmc_send_cmd,
  133. .set_ios = mxsmmc_set_ios,
  134. .init = mxsmmc_init,
  135. };
  136. int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
  137. int (*cd)(int))
  138. {
  139. struct mmc *mmc = NULL;
  140. struct mxsmmc_priv *priv = NULL;
  141. int ret;
  142. const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
  143. if (!mxs_ssp_bus_id_valid(id))
  144. return -ENODEV;
  145. priv = malloc(sizeof(struct mxsmmc_priv));
  146. if (!priv)
  147. return -ENOMEM;
  148. priv->desc = mxs_dma_desc_alloc();
  149. if (!priv->desc) {
  150. free(priv);
  151. return -ENOMEM;
  152. }
  153. ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
  154. if (ret)
  155. return ret;
  156. priv->mmc_is_wp = wp;
  157. priv->mmc_cd = cd;
  158. priv->id = id;
  159. priv->regs = mxs_ssp_regs_by_bus(id);
  160. priv->cfg.name = "MXS MMC";
  161. priv->cfg.ops = &mxsmmc_ops;
  162. priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  163. priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
  164. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  165. /*
  166. * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
  167. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  168. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  169. * CLOCK_RATE could be any integer from 0 to 255.
  170. */
  171. priv->cfg.f_min = 400000;
  172. priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id)
  173. * 1000 / 2;
  174. priv->cfg.b_max = 0x20;
  175. mmc = mmc_create(&priv->cfg, priv);
  176. if (!mmc) {
  177. mxs_dma_desc_free(priv->desc);
  178. free(priv);
  179. return -ENOMEM;
  180. }
  181. return 0;
  182. }
  183. #endif /* CONFIG_IS_ENABLED(DM_MMC) */
  184. static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
  185. {
  186. struct mxs_ssp_regs *ssp_regs = priv->regs;
  187. uint32_t *data_ptr;
  188. int timeout = MXSMMC_MAX_TIMEOUT;
  189. uint32_t reg;
  190. uint32_t data_count = data->blocksize * data->blocks;
  191. if (data->flags & MMC_DATA_READ) {
  192. data_ptr = (uint32_t *)data->dest;
  193. while (data_count && --timeout) {
  194. reg = readl(&ssp_regs->hw_ssp_status);
  195. if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
  196. *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
  197. data_count -= 4;
  198. timeout = MXSMMC_MAX_TIMEOUT;
  199. } else
  200. udelay(1000);
  201. }
  202. } else {
  203. data_ptr = (uint32_t *)data->src;
  204. timeout *= 100;
  205. while (data_count && --timeout) {
  206. reg = readl(&ssp_regs->hw_ssp_status);
  207. if (!(reg & SSP_STATUS_FIFO_FULL)) {
  208. writel(*data_ptr++, &ssp_regs->hw_ssp_data);
  209. data_count -= 4;
  210. timeout = MXSMMC_MAX_TIMEOUT;
  211. } else
  212. udelay(1000);
  213. }
  214. }
  215. return timeout ? 0 : -ECOMM;
  216. }
  217. static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
  218. {
  219. uint32_t data_count = data->blocksize * data->blocks;
  220. int dmach;
  221. struct mxs_dma_desc *desc = priv->desc;
  222. void *addr;
  223. unsigned int flags;
  224. struct bounce_buffer bbstate;
  225. memset(desc, 0, sizeof(struct mxs_dma_desc));
  226. desc->address = (dma_addr_t)desc;
  227. if (data->flags & MMC_DATA_READ) {
  228. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
  229. addr = data->dest;
  230. flags = GEN_BB_WRITE;
  231. } else {
  232. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
  233. addr = (void *)data->src;
  234. flags = GEN_BB_READ;
  235. }
  236. bounce_buffer_start(&bbstate, addr, data_count, flags);
  237. priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
  238. priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
  239. (data_count << MXS_DMA_DESC_BYTES_OFFSET);
  240. #if !CONFIG_IS_ENABLED(DM_MMC)
  241. dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
  242. #else
  243. dmach = priv->dma_channel;
  244. #endif
  245. mxs_dma_desc_append(dmach, priv->desc);
  246. if (mxs_dma_go(dmach)) {
  247. bounce_buffer_stop(&bbstate);
  248. return -ECOMM;
  249. }
  250. bounce_buffer_stop(&bbstate);
  251. return 0;
  252. }
  253. #if !CONFIG_IS_ENABLED(DM_MMC)
  254. /*
  255. * Sends a command out on the bus. Takes the mmc pointer,
  256. * a command pointer, and an optional data pointer.
  257. */
  258. static int
  259. mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  260. {
  261. struct mxsmmc_priv *priv = mmc->priv;
  262. struct mxs_ssp_regs *ssp_regs = priv->regs;
  263. #else
  264. static int
  265. mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
  266. {
  267. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  268. struct mxsmmc_priv *priv = dev_get_priv(dev);
  269. struct mxs_ssp_regs *ssp_regs = priv->regs;
  270. struct mmc *mmc = &plat->mmc;
  271. #endif
  272. uint32_t reg;
  273. int timeout;
  274. uint32_t ctrl0;
  275. int ret;
  276. #if !CONFIG_IS_ENABLED(DM_MMC)
  277. int devnum = mmc->block_dev.devnum;
  278. #else
  279. int devnum = mmc_get_blk_desc(mmc)->devnum;
  280. #endif
  281. debug("MMC%d: CMD%d\n", devnum, cmd->cmdidx);
  282. /* Check bus busy */
  283. timeout = MXSMMC_MAX_TIMEOUT;
  284. while (--timeout) {
  285. udelay(1000);
  286. reg = readl(&ssp_regs->hw_ssp_status);
  287. if (!(reg &
  288. (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
  289. SSP_STATUS_CMD_BUSY))) {
  290. break;
  291. }
  292. }
  293. if (!timeout) {
  294. printf("MMC%d: Bus busy timeout!\n", devnum);
  295. return -ETIMEDOUT;
  296. }
  297. #if !CONFIG_IS_ENABLED(DM_MMC)
  298. /* See if card is present */
  299. if (!mxsmmc_cd(priv)) {
  300. printf("MMC%d: No card detected!\n", devnum);
  301. return -ENOMEDIUM;
  302. }
  303. #endif
  304. /* Start building CTRL0 contents */
  305. ctrl0 = priv->buswidth;
  306. /* Set up command */
  307. if (!(cmd->resp_type & MMC_RSP_CRC))
  308. ctrl0 |= SSP_CTRL0_IGNORE_CRC;
  309. if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
  310. ctrl0 |= SSP_CTRL0_GET_RESP;
  311. if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
  312. ctrl0 |= SSP_CTRL0_LONG_RESP;
  313. if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
  314. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
  315. else
  316. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
  317. /* Command index */
  318. reg = readl(&ssp_regs->hw_ssp_cmd0);
  319. reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
  320. reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
  321. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  322. reg |= SSP_CMD0_APPEND_8CYC;
  323. writel(reg, &ssp_regs->hw_ssp_cmd0);
  324. /* Command argument */
  325. writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
  326. /* Set up data */
  327. if (data) {
  328. /* READ or WRITE */
  329. if (data->flags & MMC_DATA_READ) {
  330. ctrl0 |= SSP_CTRL0_READ;
  331. #if !CONFIG_IS_ENABLED(DM_MMC)
  332. } else if (priv->mmc_is_wp &&
  333. priv->mmc_is_wp(devnum)) {
  334. printf("MMC%d: Can not write a locked card!\n", devnum);
  335. return -EOPNOTSUPP;
  336. #endif
  337. }
  338. ctrl0 |= SSP_CTRL0_DATA_XFER;
  339. reg = data->blocksize * data->blocks;
  340. #if defined(CONFIG_MX23)
  341. ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
  342. clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
  343. SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
  344. ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
  345. ((ffs(data->blocksize) - 1) <<
  346. SSP_CMD0_BLOCK_SIZE_OFFSET));
  347. #elif defined(CONFIG_MX28)
  348. writel(reg, &ssp_regs->hw_ssp_xfer_size);
  349. reg = ((data->blocks - 1) <<
  350. SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
  351. ((ffs(data->blocksize) - 1) <<
  352. SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
  353. writel(reg, &ssp_regs->hw_ssp_block_size);
  354. #endif
  355. }
  356. /* Kick off the command */
  357. ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
  358. writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
  359. /* Wait for the command to complete */
  360. timeout = MXSMMC_MAX_TIMEOUT;
  361. while (--timeout) {
  362. udelay(1000);
  363. reg = readl(&ssp_regs->hw_ssp_status);
  364. if (!(reg & SSP_STATUS_CMD_BUSY))
  365. break;
  366. }
  367. if (!timeout) {
  368. printf("MMC%d: Command %d busy\n", devnum, cmd->cmdidx);
  369. return -ETIMEDOUT;
  370. }
  371. /* Check command timeout */
  372. if (reg & SSP_STATUS_RESP_TIMEOUT) {
  373. debug("MMC%d: Command %d timeout (status 0x%08x)\n",
  374. devnum, cmd->cmdidx, reg);
  375. return -ETIMEDOUT;
  376. }
  377. /* Check command errors */
  378. if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
  379. printf("MMC%d: Command %d error (status 0x%08x)!\n",
  380. devnum, cmd->cmdidx, reg);
  381. return -ECOMM;
  382. }
  383. /* Copy response to response buffer */
  384. if (cmd->resp_type & MMC_RSP_136) {
  385. cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
  386. cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
  387. cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
  388. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
  389. } else
  390. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
  391. /* Return if no data to process */
  392. if (!data)
  393. return 0;
  394. if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
  395. ret = mxsmmc_send_cmd_pio(priv, data);
  396. if (ret) {
  397. printf("MMC%d: Data timeout with command %d "
  398. "(status 0x%08x)!\n", devnum, cmd->cmdidx, reg);
  399. return ret;
  400. }
  401. } else {
  402. ret = mxsmmc_send_cmd_dma(priv, data);
  403. if (ret) {
  404. printf("MMC%d: DMA transfer failed\n", devnum);
  405. return ret;
  406. }
  407. }
  408. /* Check data errors */
  409. reg = readl(&ssp_regs->hw_ssp_status);
  410. if (reg &
  411. (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
  412. SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
  413. printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
  414. devnum, cmd->cmdidx, reg);
  415. return -ECOMM;
  416. }
  417. return 0;
  418. }
  419. #if CONFIG_IS_ENABLED(DM_MMC)
  420. /* Base numbers of i.MX2[38] clk for ssp0 IP block */
  421. #define MXS_SSP_IMX23_CLKID_SSP0 33
  422. #define MXS_SSP_IMX28_CLKID_SSP0 46
  423. static int mxsmmc_get_cd(struct udevice *dev)
  424. {
  425. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  426. struct mxsmmc_priv *priv = dev_get_priv(dev);
  427. struct mxs_ssp_regs *ssp_regs = priv->regs;
  428. if (plat->non_removable)
  429. return 1;
  430. return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  431. }
  432. static int mxsmmc_set_ios(struct udevice *dev)
  433. {
  434. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  435. struct mxsmmc_priv *priv = dev_get_priv(dev);
  436. struct mxs_ssp_regs *ssp_regs = priv->regs;
  437. struct mmc *mmc = &plat->mmc;
  438. /* Set the clock speed */
  439. if (mmc->clock)
  440. mxs_set_ssp_busclock(priv->clkid, mmc->clock / 1000);
  441. switch (mmc->bus_width) {
  442. case 1:
  443. priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
  444. break;
  445. case 4:
  446. priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
  447. break;
  448. case 8:
  449. priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
  450. break;
  451. }
  452. /* Set the bus width */
  453. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  454. SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
  455. debug("MMC%d: Set %d bits bus width\n", mmc_get_blk_desc(mmc)->devnum,
  456. mmc->bus_width);
  457. return 0;
  458. }
  459. static int mxsmmc_init(struct udevice *dev)
  460. {
  461. struct mxsmmc_priv *priv = dev_get_priv(dev);
  462. struct mxs_ssp_regs *ssp_regs = priv->regs;
  463. /* Reset SSP */
  464. mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  465. /* Reconfigure the SSP block for MMC operation */
  466. writel(SSP_CTRL1_SSP_MODE_SD_MMC |
  467. SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
  468. SSP_CTRL1_DMA_ENABLE |
  469. SSP_CTRL1_POLARITY |
  470. SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  471. SSP_CTRL1_DATA_CRC_IRQ_EN |
  472. SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  473. SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  474. SSP_CTRL1_RESP_ERR_IRQ_EN,
  475. &ssp_regs->hw_ssp_ctrl1_set);
  476. /* Set initial bit clock 400 KHz */
  477. mxs_set_ssp_busclock(priv->clkid, 400);
  478. /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
  479. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
  480. udelay(200);
  481. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
  482. return 0;
  483. }
  484. static int mxsmmc_probe(struct udevice *dev)
  485. {
  486. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  487. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  488. struct mxsmmc_priv *priv = dev_get_priv(dev);
  489. struct blk_desc *bdesc;
  490. struct mmc *mmc;
  491. int ret, clkid;
  492. debug("%s: probe\n", __func__);
  493. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  494. struct dtd_fsl_imx23_mmc *dtplat = &plat->dtplat;
  495. struct phandle_1_arg *p1a = &dtplat->clocks[0];
  496. priv->buswidth = dtplat->bus_width;
  497. priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
  498. priv->dma_channel = dtplat->dmas[1];
  499. clkid = p1a->arg[0];
  500. plat->non_removable = dtplat->non_removable;
  501. debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d non_removable: %d\n",
  502. priv->regs, priv->buswidth, clkid, plat->non_removable);
  503. #else
  504. priv->regs = (struct mxs_ssp_regs *)plat->base;
  505. priv->dma_channel = plat->dma_id;
  506. clkid = plat->clk_id;
  507. #endif
  508. #ifdef CONFIG_MX28
  509. priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0;
  510. #else /* CONFIG_MX23 */
  511. priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
  512. #endif
  513. mmc = &plat->mmc;
  514. mmc->cfg = &plat->cfg;
  515. mmc->dev = dev;
  516. priv->desc = mxs_dma_desc_alloc();
  517. if (!priv->desc) {
  518. printf("%s: Cannot allocate DMA descriptor\n", __func__);
  519. return -ENOMEM;
  520. }
  521. ret = mxs_dma_init_channel(priv->dma_channel);
  522. if (ret)
  523. return ret;
  524. plat->cfg.name = "MXS MMC";
  525. plat->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  526. plat->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
  527. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  528. /*
  529. * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
  530. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  531. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  532. * CLOCK_RATE could be any integer from 0 to 255.
  533. */
  534. plat->cfg.f_min = 400000;
  535. plat->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + priv->clkid) * 1000 / 2;
  536. plat->cfg.b_max = 0x20;
  537. bdesc = mmc_get_blk_desc(mmc);
  538. if (!bdesc) {
  539. printf("%s: No block device descriptor!\n", __func__);
  540. return -ENODEV;
  541. }
  542. if (plat->non_removable)
  543. bdesc->removable = 0;
  544. ret = mxsmmc_init(dev);
  545. if (ret)
  546. printf("%s: MMC%d init error %d\n", __func__,
  547. bdesc->devnum, ret);
  548. /* Set the initial clock speed */
  549. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  550. upriv->mmc = mmc;
  551. return 0;
  552. };
  553. #if CONFIG_IS_ENABLED(BLK)
  554. static int mxsmmc_bind(struct udevice *dev)
  555. {
  556. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  557. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  558. }
  559. #endif
  560. static const struct dm_mmc_ops mxsmmc_ops = {
  561. .get_cd = mxsmmc_get_cd,
  562. .send_cmd = mxsmmc_send_cmd,
  563. .set_ios = mxsmmc_set_ios,
  564. };
  565. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  566. static int mxsmmc_ofdata_to_platdata(struct udevice *bus)
  567. {
  568. struct mxsmmc_platdata *plat = bus->platdata;
  569. u32 prop[2];
  570. int ret;
  571. plat->base = dev_read_addr(bus);
  572. plat->buswidth =
  573. dev_read_u32_default(bus, "bus-width", 1);
  574. plat->non_removable = dev_read_bool(bus, "non-removable");
  575. ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
  576. if (ret) {
  577. printf("%s: Reading 'dmas' property failed!\n", __func__);
  578. return ret;
  579. }
  580. plat->dma_id = prop[1];
  581. ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
  582. if (ret) {
  583. printf("%s: Reading 'clocks' property failed!\n", __func__);
  584. return ret;
  585. }
  586. plat->clk_id = prop[1];
  587. debug("%s: base=0x%x, bus_width=%d %s dma_id=%d clk_id=%d\n",
  588. __func__, (uint)plat->base, plat->buswidth,
  589. plat->non_removable ? "non-removable" : NULL,
  590. plat->dma_id, plat->clk_id);
  591. return 0;
  592. }
  593. static const struct udevice_id mxsmmc_ids[] = {
  594. { .compatible = "fsl,imx23-mmc", },
  595. { .compatible = "fsl,imx28-mmc", },
  596. { /* sentinel */ }
  597. };
  598. #endif
  599. U_BOOT_DRIVER(fsl_imx23_mmc) = {
  600. .name = "fsl_imx23_mmc",
  601. .id = UCLASS_MMC,
  602. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  603. .of_match = mxsmmc_ids,
  604. .ofdata_to_platdata = mxsmmc_ofdata_to_platdata,
  605. #endif
  606. .ops = &mxsmmc_ops,
  607. #if CONFIG_IS_ENABLED(BLK)
  608. .bind = mxsmmc_bind,
  609. #endif
  610. .probe = mxsmmc_probe,
  611. .priv_auto_alloc_size = sizeof(struct mxsmmc_priv),
  612. .platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata),
  613. };
  614. U_BOOT_DRIVER_ALIAS(fsl_imx23_mmc, fsl_imx28_mmc)
  615. #endif /* CONFIG_DM_MMC */