mvebu_mmc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell MMC/SD/SDIO driver
  4. *
  5. * (C) Copyright 2012-2014
  6. * Marvell Semiconductor <www.marvell.com>
  7. * Written-by: Maen Suleiman, Gerald Kerma
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <part.h>
  14. #include <mmc.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/soc.h>
  18. #include <mvebu_mmc.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define DRIVER_NAME "MVEBU_MMC"
  21. #define MVEBU_TARGET_DRAM 0
  22. #define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
  23. static void mvebu_mmc_write(u32 offs, u32 val)
  24. {
  25. writel(val, CONFIG_SYS_MMC_BASE + (offs));
  26. }
  27. static u32 mvebu_mmc_read(u32 offs)
  28. {
  29. return readl(CONFIG_SYS_MMC_BASE + (offs));
  30. }
  31. static int mvebu_mmc_setup_data(struct mmc_data *data)
  32. {
  33. u32 ctrl_reg;
  34. debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
  35. (data->flags & MMC_DATA_READ) ? "read" : "write",
  36. data->blocks, data->blocksize);
  37. /* default to maximum timeout */
  38. ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
  39. ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
  40. mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
  41. if (data->flags & MMC_DATA_READ) {
  42. mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
  43. mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
  44. } else {
  45. mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
  46. mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
  47. }
  48. mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
  49. mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
  50. return 0;
  51. }
  52. static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  53. struct mmc_data *data)
  54. {
  55. ulong start;
  56. ushort waittype = 0;
  57. ushort resptype = 0;
  58. ushort xfertype = 0;
  59. ushort resp_indx = 0;
  60. debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
  61. DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
  62. debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
  63. cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
  64. /*
  65. * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
  66. * register is sometimes not set before a while when some
  67. * "unusual" data block sizes are used (such as with the SWITCH
  68. * command), even despite the fact that the XFER_DONE interrupt
  69. * was raised. And if another data transfer starts before
  70. * this bit comes to good sense (which eventually happens by
  71. * itself) then the new transfer simply fails with a timeout.
  72. */
  73. if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
  74. ushort hw_state, count = 0;
  75. start = get_timer(0);
  76. do {
  77. hw_state = mvebu_mmc_read(SDIO_HW_STATE);
  78. if ((get_timer(0) - start) > TIMEOUT_DELAY) {
  79. printf("%s : FIFO_EMPTY bit missing\n",
  80. DRIVER_NAME);
  81. break;
  82. }
  83. count++;
  84. } while (!(hw_state & CMD_FIFO_EMPTY));
  85. debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
  86. DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
  87. }
  88. /* Clear status */
  89. mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
  90. mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
  91. resptype = SDIO_CMD_INDEX(cmd->cmdidx);
  92. /* Analyzing resptype/xfertype/waittype for the command */
  93. if (cmd->resp_type & MMC_RSP_BUSY)
  94. resptype |= SDIO_CMD_RSP_48BUSY;
  95. else if (cmd->resp_type & MMC_RSP_136)
  96. resptype |= SDIO_CMD_RSP_136;
  97. else if (cmd->resp_type & MMC_RSP_PRESENT)
  98. resptype |= SDIO_CMD_RSP_48;
  99. else
  100. resptype |= SDIO_CMD_RSP_NONE;
  101. if (cmd->resp_type & MMC_RSP_CRC)
  102. resptype |= SDIO_CMD_CHECK_CMDCRC;
  103. if (cmd->resp_type & MMC_RSP_OPCODE)
  104. resptype |= SDIO_CMD_INDX_CHECK;
  105. if (cmd->resp_type & MMC_RSP_PRESENT) {
  106. resptype |= SDIO_UNEXPECTED_RESP;
  107. waittype |= SDIO_NOR_UNEXP_RSP;
  108. }
  109. if (data) {
  110. int err = mvebu_mmc_setup_data(data);
  111. if (err) {
  112. debug("%s: command DATA error :%x\n",
  113. DRIVER_NAME, err);
  114. return err;
  115. }
  116. resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
  117. xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
  118. if (data->flags & MMC_DATA_READ) {
  119. xfertype |= SDIO_XFER_MODE_TO_HOST;
  120. waittype = SDIO_NOR_DMA_INI;
  121. } else {
  122. waittype |= SDIO_NOR_XFER_DONE;
  123. }
  124. } else {
  125. waittype |= SDIO_NOR_CMD_DONE;
  126. }
  127. /* Setting cmd arguments */
  128. mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
  129. mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
  130. /* Setting Xfer mode */
  131. mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
  132. /* Sending command */
  133. mvebu_mmc_write(SDIO_CMD, resptype);
  134. start = get_timer(0);
  135. while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
  136. if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
  137. debug("%s: error! cmdidx : %d, err reg: %04x\n",
  138. DRIVER_NAME, cmd->cmdidx,
  139. mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
  140. if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
  141. (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
  142. debug("%s: command READ timed out\n",
  143. DRIVER_NAME);
  144. return -ETIMEDOUT;
  145. }
  146. debug("%s: command READ error\n", DRIVER_NAME);
  147. return -ECOMM;
  148. }
  149. if ((get_timer(0) - start) > TIMEOUT_DELAY) {
  150. debug("%s: command timed out\n", DRIVER_NAME);
  151. return -ETIMEDOUT;
  152. }
  153. }
  154. /* Handling response */
  155. if (cmd->resp_type & MMC_RSP_136) {
  156. uint response[8];
  157. for (resp_indx = 0; resp_indx < 8; resp_indx++)
  158. response[resp_indx]
  159. = mvebu_mmc_read(SDIO_RSP(resp_indx));
  160. cmd->response[0] = ((response[0] & 0x03ff) << 22) |
  161. ((response[1] & 0xffff) << 6) |
  162. ((response[2] & 0xfc00) >> 10);
  163. cmd->response[1] = ((response[2] & 0x03ff) << 22) |
  164. ((response[3] & 0xffff) << 6) |
  165. ((response[4] & 0xfc00) >> 10);
  166. cmd->response[2] = ((response[4] & 0x03ff) << 22) |
  167. ((response[5] & 0xffff) << 6) |
  168. ((response[6] & 0xfc00) >> 10);
  169. cmd->response[3] = ((response[6] & 0x03ff) << 22) |
  170. ((response[7] & 0x3fff) << 8);
  171. } else if (cmd->resp_type & MMC_RSP_PRESENT) {
  172. uint response[3];
  173. for (resp_indx = 0; resp_indx < 3; resp_indx++)
  174. response[resp_indx]
  175. = mvebu_mmc_read(SDIO_RSP(resp_indx));
  176. cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
  177. ((response[1] & 0xffff) << (14 - 8)) |
  178. ((response[0] & 0x03ff) << (30 - 8));
  179. cmd->response[1] = ((response[0] & 0xfc00) >> 10);
  180. cmd->response[2] = 0;
  181. cmd->response[3] = 0;
  182. } else {
  183. cmd->response[0] = 0;
  184. cmd->response[1] = 0;
  185. cmd->response[2] = 0;
  186. cmd->response[3] = 0;
  187. }
  188. debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
  189. debug("[0x%x] ", cmd->response[0]);
  190. debug("[0x%x] ", cmd->response[1]);
  191. debug("[0x%x] ", cmd->response[2]);
  192. debug("[0x%x] ", cmd->response[3]);
  193. debug("\n");
  194. if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
  195. (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
  196. return -ETIMEDOUT;
  197. return 0;
  198. }
  199. static void mvebu_mmc_power_up(void)
  200. {
  201. debug("%s: power up\n", DRIVER_NAME);
  202. /* disable interrupts */
  203. mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
  204. mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
  205. /* SW reset */
  206. mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
  207. mvebu_mmc_write(SDIO_XFER_MODE, 0);
  208. /* enable status */
  209. mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
  210. mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
  211. /* enable interrupts status */
  212. mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
  213. mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
  214. }
  215. static void mvebu_mmc_set_clk(unsigned int clock)
  216. {
  217. unsigned int m;
  218. if (clock == 0) {
  219. debug("%s: clock off\n", DRIVER_NAME);
  220. mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
  221. mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
  222. } else {
  223. m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
  224. if (m > MVEBU_MMC_BASE_DIV_MAX)
  225. m = MVEBU_MMC_BASE_DIV_MAX;
  226. mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
  227. debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
  228. }
  229. }
  230. static void mvebu_mmc_set_bus(unsigned int bus)
  231. {
  232. u32 ctrl_reg = 0;
  233. ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
  234. ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
  235. switch (bus) {
  236. case 4:
  237. ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
  238. break;
  239. case 1:
  240. default:
  241. ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
  242. }
  243. /* default transfer mode */
  244. ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
  245. ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
  246. /* default to maximum timeout */
  247. ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
  248. ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
  249. ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
  250. ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
  251. debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
  252. (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
  253. "push-pull" : "open-drain",
  254. (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
  255. "4bit-width" : "1bit-width",
  256. (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
  257. "high-speed" : "");
  258. mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
  259. }
  260. static int mvebu_mmc_set_ios(struct mmc *mmc)
  261. {
  262. debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
  263. mmc->bus_width, mmc->clock);
  264. mvebu_mmc_set_bus(mmc->bus_width);
  265. mvebu_mmc_set_clk(mmc->clock);
  266. return 0;
  267. }
  268. /*
  269. * Set window register.
  270. */
  271. static void mvebu_window_setup(void)
  272. {
  273. int i;
  274. for (i = 0; i < 4; i++) {
  275. mvebu_mmc_write(WINDOW_CTRL(i), 0);
  276. mvebu_mmc_write(WINDOW_BASE(i), 0);
  277. }
  278. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  279. u32 size, base, attrib;
  280. /* Enable DRAM bank */
  281. switch (i) {
  282. case 0:
  283. attrib = KWCPU_ATTR_DRAM_CS0;
  284. break;
  285. case 1:
  286. attrib = KWCPU_ATTR_DRAM_CS1;
  287. break;
  288. case 2:
  289. attrib = KWCPU_ATTR_DRAM_CS2;
  290. break;
  291. case 3:
  292. attrib = KWCPU_ATTR_DRAM_CS3;
  293. break;
  294. default:
  295. /* invalide bank, disable access */
  296. attrib = 0;
  297. break;
  298. }
  299. size = gd->bd->bi_dram[i].size;
  300. base = gd->bd->bi_dram[i].start;
  301. if (size && attrib) {
  302. mvebu_mmc_write(WINDOW_CTRL(i),
  303. MVCPU_WIN_CTRL_DATA(size,
  304. MVEBU_TARGET_DRAM,
  305. attrib,
  306. MVCPU_WIN_ENABLE));
  307. } else {
  308. mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
  309. }
  310. mvebu_mmc_write(WINDOW_BASE(i), base);
  311. }
  312. }
  313. static int mvebu_mmc_initialize(struct mmc *mmc)
  314. {
  315. debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
  316. /*
  317. * Setting host parameters
  318. * Initial Host Ctrl : Timeout : max , Normal Speed mode,
  319. * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
  320. */
  321. mvebu_mmc_write(SDIO_HOST_CTRL,
  322. SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
  323. SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
  324. SDIO_HOST_CTRL_BIG_ENDIAN |
  325. SDIO_HOST_CTRL_PUSH_PULL_EN |
  326. SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
  327. mvebu_mmc_write(SDIO_CLK_CTRL, 0);
  328. /* enable status */
  329. mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
  330. mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
  331. /* disable interrupts */
  332. mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
  333. mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
  334. mvebu_window_setup();
  335. /* SW reset */
  336. mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
  337. return 0;
  338. }
  339. static const struct mmc_ops mvebu_mmc_ops = {
  340. .send_cmd = mvebu_mmc_send_cmd,
  341. .set_ios = mvebu_mmc_set_ios,
  342. .init = mvebu_mmc_initialize,
  343. };
  344. static struct mmc_config mvebu_mmc_cfg = {
  345. .name = DRIVER_NAME,
  346. .ops = &mvebu_mmc_ops,
  347. .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
  348. .f_max = MVEBU_MMC_CLOCKRATE_MAX,
  349. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  350. .host_caps = MMC_MODE_4BIT | MMC_MODE_HS |
  351. MMC_MODE_HS_52MHz,
  352. .part_type = PART_TYPE_DOS,
  353. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  354. };
  355. int mvebu_mmc_init(struct bd_info *bis)
  356. {
  357. struct mmc *mmc;
  358. mvebu_mmc_power_up();
  359. mmc = mmc_create(&mvebu_mmc_cfg, bis);
  360. if (mmc == NULL)
  361. return -1;
  362. return 0;
  363. }