mmc_spi.c 11 KB

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  1. /*
  2. * generic mmc spi driver
  3. *
  4. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  5. * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <part.h>
  14. #include <mmc.h>
  15. #include <stdlib.h>
  16. #include <linux/bitops.h>
  17. #include <u-boot/crc.h>
  18. #include <linux/crc7.h>
  19. #include <asm/byteorder.h>
  20. #include <dm.h>
  21. #include <spi.h>
  22. /* MMC/SD in SPI mode reports R1 status always */
  23. #define R1_SPI_IDLE BIT(0)
  24. #define R1_SPI_ERASE_RESET BIT(1)
  25. #define R1_SPI_ILLEGAL_COMMAND BIT(2)
  26. #define R1_SPI_COM_CRC BIT(3)
  27. #define R1_SPI_ERASE_SEQ BIT(4)
  28. #define R1_SPI_ADDRESS BIT(5)
  29. #define R1_SPI_PARAMETER BIT(6)
  30. /* R1 bit 7 is always zero, reuse this bit for error */
  31. #define R1_SPI_ERROR BIT(7)
  32. /* Response tokens used to ack each block written: */
  33. #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
  34. #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
  35. #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
  36. #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
  37. /* Read and write blocks start with these tokens and end with crc;
  38. * on error, read tokens act like a subset of R2_SPI_* values.
  39. */
  40. /* single block write multiblock read */
  41. #define SPI_TOKEN_SINGLE 0xfe
  42. /* multiblock write */
  43. #define SPI_TOKEN_MULTI_WRITE 0xfc
  44. /* terminate multiblock write */
  45. #define SPI_TOKEN_STOP_TRAN 0xfd
  46. /* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
  47. #define MMC_SPI_CMD(x) (0x40 | (x))
  48. /* bus capability */
  49. #define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
  50. #define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
  51. #define MMC_SPI_MAX_CLOCK 25000000 /* SD/MMC legacy speed */
  52. /* timeout value */
  53. #define CMD_TIMEOUT 8
  54. #define READ_TIMEOUT 3000000 /* 1 sec */
  55. #define WRITE_TIMEOUT 3000000 /* 1 sec */
  56. #define R1B_TIMEOUT 3000000 /* 1 sec */
  57. struct mmc_spi_plat {
  58. struct mmc_config cfg;
  59. struct mmc mmc;
  60. };
  61. struct mmc_spi_priv {
  62. struct spi_slave *spi;
  63. };
  64. static int mmc_spi_sendcmd(struct udevice *dev,
  65. ushort cmdidx, u32 cmdarg, u32 resp_type,
  66. u8 *resp, u32 resp_size,
  67. bool resp_match, u8 resp_match_value, bool r1b)
  68. {
  69. int i, rpos = 0, ret = 0;
  70. u8 cmdo[7], r;
  71. debug("%s: cmd%d cmdarg=0x%x resp_type=0x%x "
  72. "resp_size=%d resp_match=%d resp_match_value=0x%x\n",
  73. __func__, cmdidx, cmdarg, resp_type,
  74. resp_size, resp_match, resp_match_value);
  75. cmdo[0] = 0xff;
  76. cmdo[1] = MMC_SPI_CMD(cmdidx);
  77. cmdo[2] = cmdarg >> 24;
  78. cmdo[3] = cmdarg >> 16;
  79. cmdo[4] = cmdarg >> 8;
  80. cmdo[5] = cmdarg;
  81. cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
  82. ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
  83. if (ret)
  84. return ret;
  85. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
  86. if (ret)
  87. return ret;
  88. if (!resp || !resp_size)
  89. return 0;
  90. debug("%s: cmd%d", __func__, cmdidx);
  91. if (resp_match) {
  92. r = ~resp_match_value;
  93. i = CMD_TIMEOUT;
  94. while (i) {
  95. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
  96. if (ret)
  97. return ret;
  98. debug(" resp%d=0x%x", rpos, r);
  99. rpos++;
  100. i--;
  101. if (r == resp_match_value)
  102. break;
  103. }
  104. if (!i && (r != resp_match_value))
  105. return -ETIMEDOUT;
  106. }
  107. for (i = 0; i < resp_size; i++) {
  108. if (i == 0 && resp_match) {
  109. resp[i] = resp_match_value;
  110. continue;
  111. }
  112. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
  113. if (ret)
  114. return ret;
  115. debug(" resp%d=0x%x", rpos, r);
  116. rpos++;
  117. resp[i] = r;
  118. }
  119. if (r1b == true) {
  120. i = R1B_TIMEOUT;
  121. while (i) {
  122. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
  123. if (ret)
  124. return ret;
  125. debug(" resp%d=0x%x", rpos, r);
  126. rpos++;
  127. i--;
  128. if (r)
  129. break;
  130. }
  131. if (!i)
  132. return -ETIMEDOUT;
  133. }
  134. debug("\n");
  135. return 0;
  136. }
  137. static int mmc_spi_readdata(struct udevice *dev,
  138. void *xbuf, u32 bcnt, u32 bsize)
  139. {
  140. u16 crc;
  141. u8 *buf = xbuf, r1;
  142. int i, ret = 0;
  143. while (bcnt--) {
  144. for (i = 0; i < READ_TIMEOUT; i++) {
  145. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
  146. if (ret)
  147. return ret;
  148. if (r1 == SPI_TOKEN_SINGLE)
  149. break;
  150. }
  151. debug("%s: data tok%d 0x%x\n", __func__, i, r1);
  152. if (r1 == SPI_TOKEN_SINGLE) {
  153. ret = dm_spi_xfer(dev, bsize * 8, NULL, buf, 0);
  154. if (ret)
  155. return ret;
  156. ret = dm_spi_xfer(dev, 2 * 8, NULL, &crc, 0);
  157. if (ret)
  158. return ret;
  159. #ifdef CONFIG_MMC_SPI_CRC_ON
  160. if (be16_to_cpu(crc16_ccitt(0, buf, bsize)) != crc) {
  161. debug("%s: data crc error\n", __func__);
  162. r1 = R1_SPI_COM_CRC;
  163. break;
  164. }
  165. #endif
  166. r1 = 0;
  167. } else {
  168. r1 = R1_SPI_ERROR;
  169. break;
  170. }
  171. buf += bsize;
  172. }
  173. if (r1 & R1_SPI_COM_CRC)
  174. ret = -ECOMM;
  175. else if (r1) /* other errors */
  176. ret = -ETIMEDOUT;
  177. return ret;
  178. }
  179. static int mmc_spi_writedata(struct udevice *dev, const void *xbuf,
  180. u32 bcnt, u32 bsize, int multi)
  181. {
  182. const u8 *buf = xbuf;
  183. u8 r1, tok[2];
  184. u16 crc;
  185. int i, ret = 0;
  186. tok[0] = 0xff;
  187. tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
  188. while (bcnt--) {
  189. #ifdef CONFIG_MMC_SPI_CRC_ON
  190. crc = cpu_to_be16(crc16_ccitt(0, (u8 *)buf, bsize));
  191. #endif
  192. dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
  193. dm_spi_xfer(dev, bsize * 8, buf, NULL, 0);
  194. dm_spi_xfer(dev, 2 * 8, &crc, NULL, 0);
  195. for (i = 0; i < CMD_TIMEOUT; i++) {
  196. dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
  197. if ((r1 & 0x10) == 0) /* response token */
  198. break;
  199. }
  200. debug("%s: data tok%d 0x%x\n", __func__, i, r1);
  201. if (SPI_MMC_RESPONSE_CODE(r1) == SPI_RESPONSE_ACCEPTED) {
  202. debug("%s: data accepted\n", __func__);
  203. for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
  204. dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
  205. if (i && r1 == 0xff) {
  206. r1 = 0;
  207. break;
  208. }
  209. }
  210. if (i == WRITE_TIMEOUT) {
  211. debug("%s: data write timeout 0x%x\n",
  212. __func__, r1);
  213. r1 = R1_SPI_ERROR;
  214. break;
  215. }
  216. } else {
  217. debug("%s: data error 0x%x\n", __func__, r1);
  218. r1 = R1_SPI_COM_CRC;
  219. break;
  220. }
  221. buf += bsize;
  222. }
  223. if (multi && bcnt == -1) { /* stop multi write */
  224. tok[1] = SPI_TOKEN_STOP_TRAN;
  225. dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
  226. for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
  227. dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
  228. if (i && r1 == 0xff) {
  229. r1 = 0;
  230. break;
  231. }
  232. }
  233. if (i == WRITE_TIMEOUT) {
  234. debug("%s: data write timeout 0x%x\n", __func__, r1);
  235. r1 = R1_SPI_ERROR;
  236. }
  237. }
  238. if (r1 & R1_SPI_COM_CRC)
  239. ret = -ECOMM;
  240. else if (r1) /* other errors */
  241. ret = -ETIMEDOUT;
  242. return ret;
  243. }
  244. static int dm_mmc_spi_set_ios(struct udevice *dev)
  245. {
  246. return 0;
  247. }
  248. static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
  249. struct mmc_data *data)
  250. {
  251. int i, multi, ret = 0;
  252. u8 *resp = NULL;
  253. u32 resp_size = 0;
  254. bool resp_match = false, r1b = false;
  255. u8 resp8 = 0, resp16[2] = { 0 }, resp40[5] = { 0 }, resp_match_value = 0;
  256. dm_spi_claim_bus(dev);
  257. for (i = 0; i < 4; i++)
  258. cmd->response[i] = 0;
  259. switch (cmd->cmdidx) {
  260. case SD_CMD_APP_SEND_OP_COND:
  261. case MMC_CMD_SEND_OP_COND:
  262. resp = &resp8;
  263. resp_size = sizeof(resp8);
  264. cmd->cmdarg = 0x40000000;
  265. break;
  266. case SD_CMD_SEND_IF_COND:
  267. resp = (u8 *)&resp40[0];
  268. resp_size = sizeof(resp40);
  269. resp_match = true;
  270. resp_match_value = R1_SPI_IDLE;
  271. break;
  272. case MMC_CMD_SPI_READ_OCR:
  273. resp = (u8 *)&resp40[0];
  274. resp_size = sizeof(resp40);
  275. break;
  276. case MMC_CMD_SEND_STATUS:
  277. resp = (u8 *)&resp16[0];
  278. resp_size = sizeof(resp16);
  279. break;
  280. case MMC_CMD_SET_BLOCKLEN:
  281. case MMC_CMD_SPI_CRC_ON_OFF:
  282. resp = &resp8;
  283. resp_size = sizeof(resp8);
  284. resp_match = true;
  285. resp_match_value = 0x0;
  286. break;
  287. case MMC_CMD_STOP_TRANSMISSION:
  288. case MMC_CMD_ERASE:
  289. resp = &resp8;
  290. resp_size = sizeof(resp8);
  291. r1b = true;
  292. break;
  293. case MMC_CMD_SEND_CSD:
  294. case MMC_CMD_SEND_CID:
  295. case MMC_CMD_READ_SINGLE_BLOCK:
  296. case MMC_CMD_READ_MULTIPLE_BLOCK:
  297. case MMC_CMD_WRITE_SINGLE_BLOCK:
  298. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  299. case MMC_CMD_APP_CMD:
  300. case SD_CMD_ERASE_WR_BLK_START:
  301. case SD_CMD_ERASE_WR_BLK_END:
  302. resp = &resp8;
  303. resp_size = sizeof(resp8);
  304. break;
  305. default:
  306. resp = &resp8;
  307. resp_size = sizeof(resp8);
  308. resp_match = true;
  309. resp_match_value = R1_SPI_IDLE;
  310. break;
  311. };
  312. ret = mmc_spi_sendcmd(dev, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
  313. resp, resp_size, resp_match, resp_match_value, r1b);
  314. if (ret)
  315. goto done;
  316. switch (cmd->cmdidx) {
  317. case SD_CMD_APP_SEND_OP_COND:
  318. case MMC_CMD_SEND_OP_COND:
  319. cmd->response[0] = (resp8 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
  320. break;
  321. case SD_CMD_SEND_IF_COND:
  322. case MMC_CMD_SPI_READ_OCR:
  323. cmd->response[0] = resp40[4];
  324. cmd->response[0] |= (uint)resp40[3] << 8;
  325. cmd->response[0] |= (uint)resp40[2] << 16;
  326. cmd->response[0] |= (uint)resp40[1] << 24;
  327. break;
  328. case MMC_CMD_SEND_STATUS:
  329. if (resp16[0] || resp16[1])
  330. cmd->response[0] = MMC_STATUS_ERROR;
  331. else
  332. cmd->response[0] = MMC_STATUS_RDY_FOR_DATA;
  333. break;
  334. case MMC_CMD_SEND_CID:
  335. case MMC_CMD_SEND_CSD:
  336. ret = mmc_spi_readdata(dev, cmd->response, 1, 16);
  337. if (ret)
  338. return ret;
  339. for (i = 0; i < 4; i++)
  340. cmd->response[i] =
  341. cpu_to_be32(cmd->response[i]);
  342. break;
  343. default:
  344. cmd->response[0] = resp8;
  345. break;
  346. }
  347. debug("%s: cmd%d resp0=0x%x resp1=0x%x resp2=0x%x resp3=0x%x\n",
  348. __func__, cmd->cmdidx, cmd->response[0], cmd->response[1],
  349. cmd->response[2], cmd->response[3]);
  350. if (data) {
  351. debug("%s: data flags=0x%x blocks=%d block_size=%d\n",
  352. __func__, data->flags, data->blocks, data->blocksize);
  353. multi = (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK);
  354. if (data->flags == MMC_DATA_READ)
  355. ret = mmc_spi_readdata(dev, data->dest,
  356. data->blocks, data->blocksize);
  357. else if (data->flags == MMC_DATA_WRITE)
  358. ret = mmc_spi_writedata(dev, data->src,
  359. data->blocks, data->blocksize,
  360. multi);
  361. }
  362. done:
  363. dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
  364. dm_spi_release_bus(dev);
  365. return ret;
  366. }
  367. static int mmc_spi_probe(struct udevice *dev)
  368. {
  369. struct mmc_spi_priv *priv = dev_get_priv(dev);
  370. struct mmc_spi_plat *plat = dev_get_platdata(dev);
  371. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  372. char *name;
  373. priv->spi = dev_get_parent_priv(dev);
  374. if (!priv->spi->max_hz)
  375. priv->spi->max_hz = MMC_SPI_MAX_CLOCK;
  376. priv->spi->speed = 0;
  377. priv->spi->mode = SPI_MODE_0;
  378. priv->spi->wordlen = 8;
  379. name = malloc(strlen(dev->parent->name) + strlen(dev->name) + 4);
  380. if (!name)
  381. return -ENOMEM;
  382. sprintf(name, "%s:%s", dev->parent->name, dev->name);
  383. plat->cfg.name = name;
  384. plat->cfg.host_caps = MMC_MODE_SPI;
  385. plat->cfg.voltages = MMC_SPI_VOLTAGE;
  386. plat->cfg.f_min = MMC_SPI_MIN_CLOCK;
  387. plat->cfg.f_max = priv->spi->max_hz;
  388. plat->cfg.part_type = PART_TYPE_DOS;
  389. plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  390. plat->mmc.cfg = &plat->cfg;
  391. plat->mmc.priv = priv;
  392. plat->mmc.dev = dev;
  393. upriv->mmc = &plat->mmc;
  394. return 0;
  395. }
  396. static int mmc_spi_bind(struct udevice *dev)
  397. {
  398. struct mmc_spi_plat *plat = dev_get_platdata(dev);
  399. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  400. }
  401. static const struct dm_mmc_ops mmc_spi_ops = {
  402. .send_cmd = dm_mmc_spi_request,
  403. .set_ios = dm_mmc_spi_set_ios,
  404. };
  405. static const struct udevice_id dm_mmc_spi_match[] = {
  406. { .compatible = "mmc-spi-slot" },
  407. { /* sentinel */ }
  408. };
  409. U_BOOT_DRIVER(mmc_spi) = {
  410. .name = "mmc_spi",
  411. .id = UCLASS_MMC,
  412. .of_match = dm_mmc_spi_match,
  413. .ops = &mmc_spi_ops,
  414. .probe = mmc_spi_probe,
  415. .bind = mmc_spi_bind,
  416. .platdata_auto_alloc_size = sizeof(struct mmc_spi_plat),
  417. .priv_auto_alloc_size = sizeof(struct mmc_spi_priv),
  418. };