mmc.c 69 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008, Freescale Semiconductor, Inc
  4. * Copyright 2020 NXP
  5. * Andy Fleming
  6. *
  7. * Based vaguely on the Linux code
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <blk.h>
  12. #include <command.h>
  13. #include <dm.h>
  14. #include <log.h>
  15. #include <dm/device-internal.h>
  16. #include <errno.h>
  17. #include <mmc.h>
  18. #include <part.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. #include <power/regulator.h>
  22. #include <malloc.h>
  23. #include <memalign.h>
  24. #include <linux/list.h>
  25. #include <div64.h>
  26. #include "mmc_private.h"
  27. #define DEFAULT_CMD6_TIMEOUT_MS 500
  28. static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  29. #if !CONFIG_IS_ENABLED(DM_MMC)
  30. static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
  31. {
  32. return -ENOSYS;
  33. }
  34. __weak int board_mmc_getwp(struct mmc *mmc)
  35. {
  36. return -1;
  37. }
  38. int mmc_getwp(struct mmc *mmc)
  39. {
  40. int wp;
  41. wp = board_mmc_getwp(mmc);
  42. if (wp < 0) {
  43. if (mmc->cfg->ops->getwp)
  44. wp = mmc->cfg->ops->getwp(mmc);
  45. else
  46. wp = 0;
  47. }
  48. return wp;
  49. }
  50. __weak int board_mmc_getcd(struct mmc *mmc)
  51. {
  52. return -1;
  53. }
  54. #endif
  55. #ifdef CONFIG_MMC_TRACE
  56. void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  57. {
  58. printf("CMD_SEND:%d\n", cmd->cmdidx);
  59. printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  60. }
  61. void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  62. {
  63. int i;
  64. u8 *ptr;
  65. if (ret) {
  66. printf("\t\tRET\t\t\t %d\n", ret);
  67. } else {
  68. switch (cmd->resp_type) {
  69. case MMC_RSP_NONE:
  70. printf("\t\tMMC_RSP_NONE\n");
  71. break;
  72. case MMC_RSP_R1:
  73. printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  74. cmd->response[0]);
  75. break;
  76. case MMC_RSP_R1b:
  77. printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  78. cmd->response[0]);
  79. break;
  80. case MMC_RSP_R2:
  81. printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  82. cmd->response[0]);
  83. printf("\t\t \t\t 0x%08x \n",
  84. cmd->response[1]);
  85. printf("\t\t \t\t 0x%08x \n",
  86. cmd->response[2]);
  87. printf("\t\t \t\t 0x%08x \n",
  88. cmd->response[3]);
  89. printf("\n");
  90. printf("\t\t\t\t\tDUMPING DATA\n");
  91. for (i = 0; i < 4; i++) {
  92. int j;
  93. printf("\t\t\t\t\t%03d - ", i*4);
  94. ptr = (u8 *)&cmd->response[i];
  95. ptr += 3;
  96. for (j = 0; j < 4; j++)
  97. printf("%02x ", *ptr--);
  98. printf("\n");
  99. }
  100. break;
  101. case MMC_RSP_R3:
  102. printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
  103. cmd->response[0]);
  104. break;
  105. default:
  106. printf("\t\tERROR MMC rsp not supported\n");
  107. break;
  108. }
  109. }
  110. }
  111. void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
  112. {
  113. int status;
  114. status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
  115. printf("CURR STATE:%d\n", status);
  116. }
  117. #endif
  118. #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
  119. const char *mmc_mode_name(enum bus_mode mode)
  120. {
  121. static const char *const names[] = {
  122. [MMC_LEGACY] = "MMC legacy",
  123. [MMC_HS] = "MMC High Speed (26MHz)",
  124. [SD_HS] = "SD High Speed (50MHz)",
  125. [UHS_SDR12] = "UHS SDR12 (25MHz)",
  126. [UHS_SDR25] = "UHS SDR25 (50MHz)",
  127. [UHS_SDR50] = "UHS SDR50 (100MHz)",
  128. [UHS_SDR104] = "UHS SDR104 (208MHz)",
  129. [UHS_DDR50] = "UHS DDR50 (50MHz)",
  130. [MMC_HS_52] = "MMC High Speed (52MHz)",
  131. [MMC_DDR_52] = "MMC DDR52 (52MHz)",
  132. [MMC_HS_200] = "HS200 (200MHz)",
  133. [MMC_HS_400] = "HS400 (200MHz)",
  134. [MMC_HS_400_ES] = "HS400ES (200MHz)",
  135. };
  136. if (mode >= MMC_MODES_END)
  137. return "Unknown mode";
  138. else
  139. return names[mode];
  140. }
  141. #endif
  142. static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
  143. {
  144. static const int freqs[] = {
  145. [MMC_LEGACY] = 25000000,
  146. [MMC_HS] = 26000000,
  147. [SD_HS] = 50000000,
  148. [MMC_HS_52] = 52000000,
  149. [MMC_DDR_52] = 52000000,
  150. [UHS_SDR12] = 25000000,
  151. [UHS_SDR25] = 50000000,
  152. [UHS_SDR50] = 100000000,
  153. [UHS_DDR50] = 50000000,
  154. [UHS_SDR104] = 208000000,
  155. [MMC_HS_200] = 200000000,
  156. [MMC_HS_400] = 200000000,
  157. [MMC_HS_400_ES] = 200000000,
  158. };
  159. if (mode == MMC_LEGACY)
  160. return mmc->legacy_speed;
  161. else if (mode >= MMC_MODES_END)
  162. return 0;
  163. else
  164. return freqs[mode];
  165. }
  166. static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
  167. {
  168. mmc->selected_mode = mode;
  169. mmc->tran_speed = mmc_mode2freq(mmc, mode);
  170. mmc->ddr_mode = mmc_is_mode_ddr(mode);
  171. pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
  172. mmc->tran_speed / 1000000);
  173. return 0;
  174. }
  175. #if !CONFIG_IS_ENABLED(DM_MMC)
  176. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  177. {
  178. int ret;
  179. mmmc_trace_before_send(mmc, cmd);
  180. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  181. mmmc_trace_after_send(mmc, cmd, ret);
  182. return ret;
  183. }
  184. #endif
  185. /**
  186. * mmc_send_cmd_retry() - send a command to the mmc device, retrying on error
  187. *
  188. * @dev: device to receive the command
  189. * @cmd: command to send
  190. * @data: additional data to send/receive
  191. * @retries: how many times to retry; mmc_send_cmd is always called at least
  192. * once
  193. * @return 0 if ok, -ve on error
  194. */
  195. static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd,
  196. struct mmc_data *data, uint retries)
  197. {
  198. int ret;
  199. do {
  200. ret = mmc_send_cmd(mmc, cmd, data);
  201. } while (ret && retries--);
  202. return ret;
  203. }
  204. /**
  205. * mmc_send_cmd_quirks() - send a command to the mmc device, retrying if a
  206. * specific quirk is enabled
  207. *
  208. * @dev: device to receive the command
  209. * @cmd: command to send
  210. * @data: additional data to send/receive
  211. * @quirk: retry only if this quirk is enabled
  212. * @retries: how many times to retry; mmc_send_cmd is always called at least
  213. * once
  214. * @return 0 if ok, -ve on error
  215. */
  216. static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd,
  217. struct mmc_data *data, u32 quirk, uint retries)
  218. {
  219. if (CONFIG_IS_ENABLED(MMC_QUIRKS) && mmc->quirks & quirk)
  220. return mmc_send_cmd_retry(mmc, cmd, data, retries);
  221. else
  222. return mmc_send_cmd(mmc, cmd, data);
  223. }
  224. int mmc_send_status(struct mmc *mmc, unsigned int *status)
  225. {
  226. struct mmc_cmd cmd;
  227. int ret;
  228. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  229. cmd.resp_type = MMC_RSP_R1;
  230. if (!mmc_host_is_spi(mmc))
  231. cmd.cmdarg = mmc->rca << 16;
  232. ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 4);
  233. mmc_trace_state(mmc, &cmd);
  234. if (!ret)
  235. *status = cmd.response[0];
  236. return ret;
  237. }
  238. int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
  239. {
  240. unsigned int status;
  241. int err;
  242. err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
  243. if (err != -ENOSYS)
  244. return err;
  245. while (1) {
  246. err = mmc_send_status(mmc, &status);
  247. if (err)
  248. return err;
  249. if ((status & MMC_STATUS_RDY_FOR_DATA) &&
  250. (status & MMC_STATUS_CURR_STATE) !=
  251. MMC_STATE_PRG)
  252. break;
  253. if (status & MMC_STATUS_MASK) {
  254. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  255. pr_err("Status Error: 0x%08x\n", status);
  256. #endif
  257. return -ECOMM;
  258. }
  259. if (timeout_ms-- <= 0)
  260. break;
  261. udelay(1000);
  262. }
  263. if (timeout_ms <= 0) {
  264. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  265. pr_err("Timeout waiting card ready\n");
  266. #endif
  267. return -ETIMEDOUT;
  268. }
  269. return 0;
  270. }
  271. int mmc_set_blocklen(struct mmc *mmc, int len)
  272. {
  273. struct mmc_cmd cmd;
  274. if (mmc->ddr_mode)
  275. return 0;
  276. cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
  277. cmd.resp_type = MMC_RSP_R1;
  278. cmd.cmdarg = len;
  279. return mmc_send_cmd_quirks(mmc, &cmd, NULL,
  280. MMC_QUIRK_RETRY_SET_BLOCKLEN, 4);
  281. }
  282. #ifdef MMC_SUPPORTS_TUNING
  283. static const u8 tuning_blk_pattern_4bit[] = {
  284. 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
  285. 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
  286. 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
  287. 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
  288. 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
  289. 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
  290. 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
  291. 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
  292. };
  293. static const u8 tuning_blk_pattern_8bit[] = {
  294. 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
  295. 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
  296. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  297. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  298. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  299. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  300. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  301. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  302. 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
  303. 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
  304. 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
  305. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  306. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  307. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  308. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  309. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  310. };
  311. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
  312. {
  313. struct mmc_cmd cmd;
  314. struct mmc_data data;
  315. const u8 *tuning_block_pattern;
  316. int size, err;
  317. if (mmc->bus_width == 8) {
  318. tuning_block_pattern = tuning_blk_pattern_8bit;
  319. size = sizeof(tuning_blk_pattern_8bit);
  320. } else if (mmc->bus_width == 4) {
  321. tuning_block_pattern = tuning_blk_pattern_4bit;
  322. size = sizeof(tuning_blk_pattern_4bit);
  323. } else {
  324. return -EINVAL;
  325. }
  326. ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
  327. cmd.cmdidx = opcode;
  328. cmd.cmdarg = 0;
  329. cmd.resp_type = MMC_RSP_R1;
  330. data.dest = (void *)data_buf;
  331. data.blocks = 1;
  332. data.blocksize = size;
  333. data.flags = MMC_DATA_READ;
  334. err = mmc_send_cmd(mmc, &cmd, &data);
  335. if (err)
  336. return err;
  337. if (memcmp(data_buf, tuning_block_pattern, size))
  338. return -EIO;
  339. return 0;
  340. }
  341. #endif
  342. static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
  343. lbaint_t blkcnt)
  344. {
  345. struct mmc_cmd cmd;
  346. struct mmc_data data;
  347. if (blkcnt > 1)
  348. cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
  349. else
  350. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  351. if (mmc->high_capacity)
  352. cmd.cmdarg = start;
  353. else
  354. cmd.cmdarg = start * mmc->read_bl_len;
  355. cmd.resp_type = MMC_RSP_R1;
  356. data.dest = dst;
  357. data.blocks = blkcnt;
  358. data.blocksize = mmc->read_bl_len;
  359. data.flags = MMC_DATA_READ;
  360. if (mmc_send_cmd(mmc, &cmd, &data))
  361. return 0;
  362. if (blkcnt > 1) {
  363. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  364. cmd.cmdarg = 0;
  365. cmd.resp_type = MMC_RSP_R1b;
  366. if (mmc_send_cmd(mmc, &cmd, NULL)) {
  367. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  368. pr_err("mmc fail to send stop cmd\n");
  369. #endif
  370. return 0;
  371. }
  372. }
  373. return blkcnt;
  374. }
  375. #if !CONFIG_IS_ENABLED(DM_MMC)
  376. static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
  377. {
  378. if (mmc->cfg->ops->get_b_max)
  379. return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
  380. else
  381. return mmc->cfg->b_max;
  382. }
  383. #endif
  384. #if CONFIG_IS_ENABLED(BLK)
  385. ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
  386. #else
  387. ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
  388. void *dst)
  389. #endif
  390. {
  391. #if CONFIG_IS_ENABLED(BLK)
  392. struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
  393. #endif
  394. int dev_num = block_dev->devnum;
  395. int err;
  396. lbaint_t cur, blocks_todo = blkcnt;
  397. uint b_max;
  398. if (blkcnt == 0)
  399. return 0;
  400. struct mmc *mmc = find_mmc_device(dev_num);
  401. if (!mmc)
  402. return 0;
  403. if (CONFIG_IS_ENABLED(MMC_TINY))
  404. err = mmc_switch_part(mmc, block_dev->hwpart);
  405. else
  406. err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
  407. if (err < 0)
  408. return 0;
  409. if ((start + blkcnt) > block_dev->lba) {
  410. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  411. pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
  412. start + blkcnt, block_dev->lba);
  413. #endif
  414. return 0;
  415. }
  416. if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
  417. pr_debug("%s: Failed to set blocklen\n", __func__);
  418. return 0;
  419. }
  420. b_max = mmc_get_b_max(mmc, dst, blkcnt);
  421. do {
  422. cur = (blocks_todo > b_max) ? b_max : blocks_todo;
  423. if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
  424. pr_debug("%s: Failed to read blocks\n", __func__);
  425. return 0;
  426. }
  427. blocks_todo -= cur;
  428. start += cur;
  429. dst += cur * mmc->read_bl_len;
  430. } while (blocks_todo > 0);
  431. return blkcnt;
  432. }
  433. static int mmc_go_idle(struct mmc *mmc)
  434. {
  435. struct mmc_cmd cmd;
  436. int err;
  437. udelay(1000);
  438. cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
  439. cmd.cmdarg = 0;
  440. cmd.resp_type = MMC_RSP_NONE;
  441. err = mmc_send_cmd(mmc, &cmd, NULL);
  442. if (err)
  443. return err;
  444. udelay(2000);
  445. return 0;
  446. }
  447. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  448. static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
  449. {
  450. struct mmc_cmd cmd;
  451. int err = 0;
  452. /*
  453. * Send CMD11 only if the request is to switch the card to
  454. * 1.8V signalling.
  455. */
  456. if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  457. return mmc_set_signal_voltage(mmc, signal_voltage);
  458. cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
  459. cmd.cmdarg = 0;
  460. cmd.resp_type = MMC_RSP_R1;
  461. err = mmc_send_cmd(mmc, &cmd, NULL);
  462. if (err)
  463. return err;
  464. if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
  465. return -EIO;
  466. /*
  467. * The card should drive cmd and dat[0:3] low immediately
  468. * after the response of cmd11, but wait 100 us to be sure
  469. */
  470. err = mmc_wait_dat0(mmc, 0, 100);
  471. if (err == -ENOSYS)
  472. udelay(100);
  473. else if (err)
  474. return -ETIMEDOUT;
  475. /*
  476. * During a signal voltage level switch, the clock must be gated
  477. * for 5 ms according to the SD spec
  478. */
  479. mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
  480. err = mmc_set_signal_voltage(mmc, signal_voltage);
  481. if (err)
  482. return err;
  483. /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
  484. mdelay(10);
  485. mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
  486. /*
  487. * Failure to switch is indicated by the card holding
  488. * dat[0:3] low. Wait for at least 1 ms according to spec
  489. */
  490. err = mmc_wait_dat0(mmc, 1, 1000);
  491. if (err == -ENOSYS)
  492. udelay(1000);
  493. else if (err)
  494. return -ETIMEDOUT;
  495. return 0;
  496. }
  497. #endif
  498. static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
  499. {
  500. int timeout = 1000;
  501. int err;
  502. struct mmc_cmd cmd;
  503. while (1) {
  504. cmd.cmdidx = MMC_CMD_APP_CMD;
  505. cmd.resp_type = MMC_RSP_R1;
  506. cmd.cmdarg = 0;
  507. err = mmc_send_cmd(mmc, &cmd, NULL);
  508. if (err)
  509. return err;
  510. cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
  511. cmd.resp_type = MMC_RSP_R3;
  512. /*
  513. * Most cards do not answer if some reserved bits
  514. * in the ocr are set. However, Some controller
  515. * can set bit 7 (reserved for low voltages), but
  516. * how to manage low voltages SD card is not yet
  517. * specified.
  518. */
  519. cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
  520. (mmc->cfg->voltages & 0xff8000);
  521. if (mmc->version == SD_VERSION_2)
  522. cmd.cmdarg |= OCR_HCS;
  523. if (uhs_en)
  524. cmd.cmdarg |= OCR_S18R;
  525. err = mmc_send_cmd(mmc, &cmd, NULL);
  526. if (err)
  527. return err;
  528. if (cmd.response[0] & OCR_BUSY)
  529. break;
  530. if (timeout-- <= 0)
  531. return -EOPNOTSUPP;
  532. udelay(1000);
  533. }
  534. if (mmc->version != SD_VERSION_2)
  535. mmc->version = SD_VERSION_1_0;
  536. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  537. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  538. cmd.resp_type = MMC_RSP_R3;
  539. cmd.cmdarg = 0;
  540. err = mmc_send_cmd(mmc, &cmd, NULL);
  541. if (err)
  542. return err;
  543. }
  544. mmc->ocr = cmd.response[0];
  545. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  546. if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
  547. == 0x41000000) {
  548. err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  549. if (err)
  550. return err;
  551. }
  552. #endif
  553. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  554. mmc->rca = 0;
  555. return 0;
  556. }
  557. static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
  558. {
  559. struct mmc_cmd cmd;
  560. int err;
  561. cmd.cmdidx = MMC_CMD_SEND_OP_COND;
  562. cmd.resp_type = MMC_RSP_R3;
  563. cmd.cmdarg = 0;
  564. if (use_arg && !mmc_host_is_spi(mmc))
  565. cmd.cmdarg = OCR_HCS |
  566. (mmc->cfg->voltages &
  567. (mmc->ocr & OCR_VOLTAGE_MASK)) |
  568. (mmc->ocr & OCR_ACCESS_MODE);
  569. err = mmc_send_cmd(mmc, &cmd, NULL);
  570. if (err)
  571. return err;
  572. mmc->ocr = cmd.response[0];
  573. return 0;
  574. }
  575. static int mmc_send_op_cond(struct mmc *mmc)
  576. {
  577. int err, i;
  578. int timeout = 1000;
  579. uint start;
  580. /* Some cards seem to need this */
  581. mmc_go_idle(mmc);
  582. start = get_timer(0);
  583. /* Asking to the card its capabilities */
  584. for (i = 0; ; i++) {
  585. err = mmc_send_op_cond_iter(mmc, i != 0);
  586. if (err)
  587. return err;
  588. /* exit if not busy (flag seems to be inverted) */
  589. if (mmc->ocr & OCR_BUSY)
  590. break;
  591. if (get_timer(start) > timeout)
  592. return -ETIMEDOUT;
  593. udelay(100);
  594. }
  595. mmc->op_cond_pending = 1;
  596. return 0;
  597. }
  598. static int mmc_complete_op_cond(struct mmc *mmc)
  599. {
  600. struct mmc_cmd cmd;
  601. int timeout = 1000;
  602. ulong start;
  603. int err;
  604. mmc->op_cond_pending = 0;
  605. if (!(mmc->ocr & OCR_BUSY)) {
  606. /* Some cards seem to need this */
  607. mmc_go_idle(mmc);
  608. start = get_timer(0);
  609. while (1) {
  610. err = mmc_send_op_cond_iter(mmc, 1);
  611. if (err)
  612. return err;
  613. if (mmc->ocr & OCR_BUSY)
  614. break;
  615. if (get_timer(start) > timeout)
  616. return -EOPNOTSUPP;
  617. udelay(100);
  618. }
  619. }
  620. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  621. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  622. cmd.resp_type = MMC_RSP_R3;
  623. cmd.cmdarg = 0;
  624. err = mmc_send_cmd(mmc, &cmd, NULL);
  625. if (err)
  626. return err;
  627. mmc->ocr = cmd.response[0];
  628. }
  629. mmc->version = MMC_VERSION_UNKNOWN;
  630. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  631. mmc->rca = 1;
  632. return 0;
  633. }
  634. int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
  635. {
  636. struct mmc_cmd cmd;
  637. struct mmc_data data;
  638. int err;
  639. /* Get the Card Status Register */
  640. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  641. cmd.resp_type = MMC_RSP_R1;
  642. cmd.cmdarg = 0;
  643. data.dest = (char *)ext_csd;
  644. data.blocks = 1;
  645. data.blocksize = MMC_MAX_BLOCK_LEN;
  646. data.flags = MMC_DATA_READ;
  647. err = mmc_send_cmd(mmc, &cmd, &data);
  648. return err;
  649. }
  650. static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
  651. bool send_status)
  652. {
  653. unsigned int status, start;
  654. struct mmc_cmd cmd;
  655. int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
  656. bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
  657. (index == EXT_CSD_PART_CONF);
  658. int ret;
  659. if (mmc->gen_cmd6_time)
  660. timeout_ms = mmc->gen_cmd6_time * 10;
  661. if (is_part_switch && mmc->part_switch_time)
  662. timeout_ms = mmc->part_switch_time * 10;
  663. cmd.cmdidx = MMC_CMD_SWITCH;
  664. cmd.resp_type = MMC_RSP_R1b;
  665. cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
  666. (index << 16) |
  667. (value << 8);
  668. ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 3);
  669. if (ret)
  670. return ret;
  671. start = get_timer(0);
  672. /* poll dat0 for rdy/buys status */
  673. ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
  674. if (ret && ret != -ENOSYS)
  675. return ret;
  676. /*
  677. * In cases when not allowed to poll by using CMD13 or because we aren't
  678. * capable of polling by using mmc_wait_dat0, then rely on waiting the
  679. * stated timeout to be sufficient.
  680. */
  681. if (ret == -ENOSYS && !send_status) {
  682. mdelay(timeout_ms);
  683. return 0;
  684. }
  685. /* Finally wait until the card is ready or indicates a failure
  686. * to switch. It doesn't hurt to use CMD13 here even if send_status
  687. * is false, because by now (after 'timeout_ms' ms) the bus should be
  688. * reliable.
  689. */
  690. do {
  691. ret = mmc_send_status(mmc, &status);
  692. if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
  693. pr_debug("switch failed %d/%d/0x%x !\n", set, index,
  694. value);
  695. return -EIO;
  696. }
  697. if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
  698. return 0;
  699. udelay(100);
  700. } while (get_timer(start) < timeout_ms);
  701. return -ETIMEDOUT;
  702. }
  703. int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
  704. {
  705. return __mmc_switch(mmc, set, index, value, true);
  706. }
  707. int mmc_boot_wp(struct mmc *mmc)
  708. {
  709. return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
  710. }
  711. #if !CONFIG_IS_ENABLED(MMC_TINY)
  712. static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
  713. bool hsdowngrade)
  714. {
  715. int err;
  716. int speed_bits;
  717. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  718. switch (mode) {
  719. case MMC_HS:
  720. case MMC_HS_52:
  721. case MMC_DDR_52:
  722. speed_bits = EXT_CSD_TIMING_HS;
  723. break;
  724. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  725. case MMC_HS_200:
  726. speed_bits = EXT_CSD_TIMING_HS200;
  727. break;
  728. #endif
  729. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  730. case MMC_HS_400:
  731. speed_bits = EXT_CSD_TIMING_HS400;
  732. break;
  733. #endif
  734. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  735. case MMC_HS_400_ES:
  736. speed_bits = EXT_CSD_TIMING_HS400;
  737. break;
  738. #endif
  739. case MMC_LEGACY:
  740. speed_bits = EXT_CSD_TIMING_LEGACY;
  741. break;
  742. default:
  743. return -EINVAL;
  744. }
  745. err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
  746. speed_bits, !hsdowngrade);
  747. if (err)
  748. return err;
  749. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  750. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  751. /*
  752. * In case the eMMC is in HS200/HS400 mode and we are downgrading
  753. * to HS mode, the card clock are still running much faster than
  754. * the supported HS mode clock, so we can not reliably read out
  755. * Extended CSD. Reconfigure the controller to run at HS mode.
  756. */
  757. if (hsdowngrade) {
  758. mmc_select_mode(mmc, MMC_HS);
  759. mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
  760. }
  761. #endif
  762. if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
  763. /* Now check to see that it worked */
  764. err = mmc_send_ext_csd(mmc, test_csd);
  765. if (err)
  766. return err;
  767. /* No high-speed support */
  768. if (!test_csd[EXT_CSD_HS_TIMING])
  769. return -ENOTSUPP;
  770. }
  771. return 0;
  772. }
  773. static int mmc_get_capabilities(struct mmc *mmc)
  774. {
  775. u8 *ext_csd = mmc->ext_csd;
  776. char cardtype;
  777. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
  778. if (mmc_host_is_spi(mmc))
  779. return 0;
  780. /* Only version 4 supports high-speed */
  781. if (mmc->version < MMC_VERSION_4)
  782. return 0;
  783. if (!ext_csd) {
  784. pr_err("No ext_csd found!\n"); /* this should enver happen */
  785. return -ENOTSUPP;
  786. }
  787. mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  788. cardtype = ext_csd[EXT_CSD_CARD_TYPE];
  789. mmc->cardtype = cardtype;
  790. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  791. if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
  792. EXT_CSD_CARD_TYPE_HS200_1_8V)) {
  793. mmc->card_caps |= MMC_MODE_HS200;
  794. }
  795. #endif
  796. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
  797. CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  798. if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
  799. EXT_CSD_CARD_TYPE_HS400_1_8V)) {
  800. mmc->card_caps |= MMC_MODE_HS400;
  801. }
  802. #endif
  803. if (cardtype & EXT_CSD_CARD_TYPE_52) {
  804. if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
  805. mmc->card_caps |= MMC_MODE_DDR_52MHz;
  806. mmc->card_caps |= MMC_MODE_HS_52MHz;
  807. }
  808. if (cardtype & EXT_CSD_CARD_TYPE_26)
  809. mmc->card_caps |= MMC_MODE_HS;
  810. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  811. if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
  812. (mmc->card_caps & MMC_MODE_HS400)) {
  813. mmc->card_caps |= MMC_MODE_HS400_ES;
  814. }
  815. #endif
  816. return 0;
  817. }
  818. #endif
  819. static int mmc_set_capacity(struct mmc *mmc, int part_num)
  820. {
  821. switch (part_num) {
  822. case 0:
  823. mmc->capacity = mmc->capacity_user;
  824. break;
  825. case 1:
  826. case 2:
  827. mmc->capacity = mmc->capacity_boot;
  828. break;
  829. case 3:
  830. mmc->capacity = mmc->capacity_rpmb;
  831. break;
  832. case 4:
  833. case 5:
  834. case 6:
  835. case 7:
  836. mmc->capacity = mmc->capacity_gp[part_num - 4];
  837. break;
  838. default:
  839. return -1;
  840. }
  841. mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  842. return 0;
  843. }
  844. int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
  845. {
  846. int ret;
  847. int retry = 3;
  848. do {
  849. ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  850. EXT_CSD_PART_CONF,
  851. (mmc->part_config & ~PART_ACCESS_MASK)
  852. | (part_num & PART_ACCESS_MASK));
  853. } while (ret && retry--);
  854. /*
  855. * Set the capacity if the switch succeeded or was intended
  856. * to return to representing the raw device.
  857. */
  858. if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
  859. ret = mmc_set_capacity(mmc, part_num);
  860. mmc_get_blk_desc(mmc)->hwpart = part_num;
  861. }
  862. return ret;
  863. }
  864. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  865. int mmc_hwpart_config(struct mmc *mmc,
  866. const struct mmc_hwpart_conf *conf,
  867. enum mmc_hwpart_conf_mode mode)
  868. {
  869. u8 part_attrs = 0;
  870. u32 enh_size_mult;
  871. u32 enh_start_addr;
  872. u32 gp_size_mult[4];
  873. u32 max_enh_size_mult;
  874. u32 tot_enh_size_mult = 0;
  875. u8 wr_rel_set;
  876. int i, pidx, err;
  877. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  878. if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
  879. return -EINVAL;
  880. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
  881. pr_err("eMMC >= 4.4 required for enhanced user data area\n");
  882. return -EMEDIUMTYPE;
  883. }
  884. if (!(mmc->part_support & PART_SUPPORT)) {
  885. pr_err("Card does not support partitioning\n");
  886. return -EMEDIUMTYPE;
  887. }
  888. if (!mmc->hc_wp_grp_size) {
  889. pr_err("Card does not define HC WP group size\n");
  890. return -EMEDIUMTYPE;
  891. }
  892. /* check partition alignment and total enhanced size */
  893. if (conf->user.enh_size) {
  894. if (conf->user.enh_size % mmc->hc_wp_grp_size ||
  895. conf->user.enh_start % mmc->hc_wp_grp_size) {
  896. pr_err("User data enhanced area not HC WP group "
  897. "size aligned\n");
  898. return -EINVAL;
  899. }
  900. part_attrs |= EXT_CSD_ENH_USR;
  901. enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
  902. if (mmc->high_capacity) {
  903. enh_start_addr = conf->user.enh_start;
  904. } else {
  905. enh_start_addr = (conf->user.enh_start << 9);
  906. }
  907. } else {
  908. enh_size_mult = 0;
  909. enh_start_addr = 0;
  910. }
  911. tot_enh_size_mult += enh_size_mult;
  912. for (pidx = 0; pidx < 4; pidx++) {
  913. if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
  914. pr_err("GP%i partition not HC WP group size "
  915. "aligned\n", pidx+1);
  916. return -EINVAL;
  917. }
  918. gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
  919. if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
  920. part_attrs |= EXT_CSD_ENH_GP(pidx);
  921. tot_enh_size_mult += gp_size_mult[pidx];
  922. }
  923. }
  924. if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
  925. pr_err("Card does not support enhanced attribute\n");
  926. return -EMEDIUMTYPE;
  927. }
  928. err = mmc_send_ext_csd(mmc, ext_csd);
  929. if (err)
  930. return err;
  931. max_enh_size_mult =
  932. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
  933. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
  934. ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
  935. if (tot_enh_size_mult > max_enh_size_mult) {
  936. pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
  937. tot_enh_size_mult, max_enh_size_mult);
  938. return -EMEDIUMTYPE;
  939. }
  940. /* The default value of EXT_CSD_WR_REL_SET is device
  941. * dependent, the values can only be changed if the
  942. * EXT_CSD_HS_CTRL_REL bit is set. The values can be
  943. * changed only once and before partitioning is completed. */
  944. wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  945. if (conf->user.wr_rel_change) {
  946. if (conf->user.wr_rel_set)
  947. wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
  948. else
  949. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
  950. }
  951. for (pidx = 0; pidx < 4; pidx++) {
  952. if (conf->gp_part[pidx].wr_rel_change) {
  953. if (conf->gp_part[pidx].wr_rel_set)
  954. wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
  955. else
  956. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
  957. }
  958. }
  959. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
  960. !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
  961. puts("Card does not support host controlled partition write "
  962. "reliability settings\n");
  963. return -EMEDIUMTYPE;
  964. }
  965. if (ext_csd[EXT_CSD_PARTITION_SETTING] &
  966. EXT_CSD_PARTITION_SETTING_COMPLETED) {
  967. pr_err("Card already partitioned\n");
  968. return -EPERM;
  969. }
  970. if (mode == MMC_HWPART_CONF_CHECK)
  971. return 0;
  972. /* Partitioning requires high-capacity size definitions */
  973. if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
  974. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  975. EXT_CSD_ERASE_GROUP_DEF, 1);
  976. if (err)
  977. return err;
  978. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  979. #if CONFIG_IS_ENABLED(MMC_WRITE)
  980. /* update erase group size to be high-capacity */
  981. mmc->erase_grp_size =
  982. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  983. #endif
  984. }
  985. /* all OK, write the configuration */
  986. for (i = 0; i < 4; i++) {
  987. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  988. EXT_CSD_ENH_START_ADDR+i,
  989. (enh_start_addr >> (i*8)) & 0xFF);
  990. if (err)
  991. return err;
  992. }
  993. for (i = 0; i < 3; i++) {
  994. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  995. EXT_CSD_ENH_SIZE_MULT+i,
  996. (enh_size_mult >> (i*8)) & 0xFF);
  997. if (err)
  998. return err;
  999. }
  1000. for (pidx = 0; pidx < 4; pidx++) {
  1001. for (i = 0; i < 3; i++) {
  1002. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1003. EXT_CSD_GP_SIZE_MULT+pidx*3+i,
  1004. (gp_size_mult[pidx] >> (i*8)) & 0xFF);
  1005. if (err)
  1006. return err;
  1007. }
  1008. }
  1009. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1010. EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
  1011. if (err)
  1012. return err;
  1013. if (mode == MMC_HWPART_CONF_SET)
  1014. return 0;
  1015. /* The WR_REL_SET is a write-once register but shall be
  1016. * written before setting PART_SETTING_COMPLETED. As it is
  1017. * write-once we can only write it when completing the
  1018. * partitioning. */
  1019. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
  1020. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1021. EXT_CSD_WR_REL_SET, wr_rel_set);
  1022. if (err)
  1023. return err;
  1024. }
  1025. /* Setting PART_SETTING_COMPLETED confirms the partition
  1026. * configuration but it only becomes effective after power
  1027. * cycle, so we do not adjust the partition related settings
  1028. * in the mmc struct. */
  1029. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1030. EXT_CSD_PARTITION_SETTING,
  1031. EXT_CSD_PARTITION_SETTING_COMPLETED);
  1032. if (err)
  1033. return err;
  1034. return 0;
  1035. }
  1036. #endif
  1037. #if !CONFIG_IS_ENABLED(DM_MMC)
  1038. int mmc_getcd(struct mmc *mmc)
  1039. {
  1040. int cd;
  1041. cd = board_mmc_getcd(mmc);
  1042. if (cd < 0) {
  1043. if (mmc->cfg->ops->getcd)
  1044. cd = mmc->cfg->ops->getcd(mmc);
  1045. else
  1046. cd = 1;
  1047. }
  1048. return cd;
  1049. }
  1050. #endif
  1051. #if !CONFIG_IS_ENABLED(MMC_TINY)
  1052. static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
  1053. {
  1054. struct mmc_cmd cmd;
  1055. struct mmc_data data;
  1056. /* Switch the frequency */
  1057. cmd.cmdidx = SD_CMD_SWITCH_FUNC;
  1058. cmd.resp_type = MMC_RSP_R1;
  1059. cmd.cmdarg = (mode << 31) | 0xffffff;
  1060. cmd.cmdarg &= ~(0xf << (group * 4));
  1061. cmd.cmdarg |= value << (group * 4);
  1062. data.dest = (char *)resp;
  1063. data.blocksize = 64;
  1064. data.blocks = 1;
  1065. data.flags = MMC_DATA_READ;
  1066. return mmc_send_cmd(mmc, &cmd, &data);
  1067. }
  1068. static int sd_get_capabilities(struct mmc *mmc)
  1069. {
  1070. int err;
  1071. struct mmc_cmd cmd;
  1072. ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
  1073. ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
  1074. struct mmc_data data;
  1075. int timeout;
  1076. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1077. u32 sd3_bus_mode;
  1078. #endif
  1079. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
  1080. if (mmc_host_is_spi(mmc))
  1081. return 0;
  1082. /* Read the SCR to find out if this card supports higher speeds */
  1083. cmd.cmdidx = MMC_CMD_APP_CMD;
  1084. cmd.resp_type = MMC_RSP_R1;
  1085. cmd.cmdarg = mmc->rca << 16;
  1086. err = mmc_send_cmd(mmc, &cmd, NULL);
  1087. if (err)
  1088. return err;
  1089. cmd.cmdidx = SD_CMD_APP_SEND_SCR;
  1090. cmd.resp_type = MMC_RSP_R1;
  1091. cmd.cmdarg = 0;
  1092. data.dest = (char *)scr;
  1093. data.blocksize = 8;
  1094. data.blocks = 1;
  1095. data.flags = MMC_DATA_READ;
  1096. err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
  1097. if (err)
  1098. return err;
  1099. mmc->scr[0] = __be32_to_cpu(scr[0]);
  1100. mmc->scr[1] = __be32_to_cpu(scr[1]);
  1101. switch ((mmc->scr[0] >> 24) & 0xf) {
  1102. case 0:
  1103. mmc->version = SD_VERSION_1_0;
  1104. break;
  1105. case 1:
  1106. mmc->version = SD_VERSION_1_10;
  1107. break;
  1108. case 2:
  1109. mmc->version = SD_VERSION_2;
  1110. if ((mmc->scr[0] >> 15) & 0x1)
  1111. mmc->version = SD_VERSION_3;
  1112. break;
  1113. default:
  1114. mmc->version = SD_VERSION_1_0;
  1115. break;
  1116. }
  1117. if (mmc->scr[0] & SD_DATA_4BIT)
  1118. mmc->card_caps |= MMC_MODE_4BIT;
  1119. /* Version 1.0 doesn't support switching */
  1120. if (mmc->version == SD_VERSION_1_0)
  1121. return 0;
  1122. timeout = 4;
  1123. while (timeout--) {
  1124. err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
  1125. (u8 *)switch_status);
  1126. if (err)
  1127. return err;
  1128. /* The high-speed function is busy. Try again */
  1129. if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
  1130. break;
  1131. }
  1132. /* If high-speed isn't supported, we return */
  1133. if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
  1134. mmc->card_caps |= MMC_CAP(SD_HS);
  1135. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1136. /* Version before 3.0 don't support UHS modes */
  1137. if (mmc->version < SD_VERSION_3)
  1138. return 0;
  1139. sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
  1140. if (sd3_bus_mode & SD_MODE_UHS_SDR104)
  1141. mmc->card_caps |= MMC_CAP(UHS_SDR104);
  1142. if (sd3_bus_mode & SD_MODE_UHS_SDR50)
  1143. mmc->card_caps |= MMC_CAP(UHS_SDR50);
  1144. if (sd3_bus_mode & SD_MODE_UHS_SDR25)
  1145. mmc->card_caps |= MMC_CAP(UHS_SDR25);
  1146. if (sd3_bus_mode & SD_MODE_UHS_SDR12)
  1147. mmc->card_caps |= MMC_CAP(UHS_SDR12);
  1148. if (sd3_bus_mode & SD_MODE_UHS_DDR50)
  1149. mmc->card_caps |= MMC_CAP(UHS_DDR50);
  1150. #endif
  1151. return 0;
  1152. }
  1153. static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
  1154. {
  1155. int err;
  1156. ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
  1157. int speed;
  1158. /* SD version 1.00 and 1.01 does not support CMD 6 */
  1159. if (mmc->version == SD_VERSION_1_0)
  1160. return 0;
  1161. switch (mode) {
  1162. case MMC_LEGACY:
  1163. speed = UHS_SDR12_BUS_SPEED;
  1164. break;
  1165. case SD_HS:
  1166. speed = HIGH_SPEED_BUS_SPEED;
  1167. break;
  1168. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1169. case UHS_SDR12:
  1170. speed = UHS_SDR12_BUS_SPEED;
  1171. break;
  1172. case UHS_SDR25:
  1173. speed = UHS_SDR25_BUS_SPEED;
  1174. break;
  1175. case UHS_SDR50:
  1176. speed = UHS_SDR50_BUS_SPEED;
  1177. break;
  1178. case UHS_DDR50:
  1179. speed = UHS_DDR50_BUS_SPEED;
  1180. break;
  1181. case UHS_SDR104:
  1182. speed = UHS_SDR104_BUS_SPEED;
  1183. break;
  1184. #endif
  1185. default:
  1186. return -EINVAL;
  1187. }
  1188. err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
  1189. if (err)
  1190. return err;
  1191. if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
  1192. return -ENOTSUPP;
  1193. return 0;
  1194. }
  1195. static int sd_select_bus_width(struct mmc *mmc, int w)
  1196. {
  1197. int err;
  1198. struct mmc_cmd cmd;
  1199. if ((w != 4) && (w != 1))
  1200. return -EINVAL;
  1201. cmd.cmdidx = MMC_CMD_APP_CMD;
  1202. cmd.resp_type = MMC_RSP_R1;
  1203. cmd.cmdarg = mmc->rca << 16;
  1204. err = mmc_send_cmd(mmc, &cmd, NULL);
  1205. if (err)
  1206. return err;
  1207. cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
  1208. cmd.resp_type = MMC_RSP_R1;
  1209. if (w == 4)
  1210. cmd.cmdarg = 2;
  1211. else if (w == 1)
  1212. cmd.cmdarg = 0;
  1213. err = mmc_send_cmd(mmc, &cmd, NULL);
  1214. if (err)
  1215. return err;
  1216. return 0;
  1217. }
  1218. #endif
  1219. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1220. static int sd_read_ssr(struct mmc *mmc)
  1221. {
  1222. static const unsigned int sd_au_size[] = {
  1223. 0, SZ_16K / 512, SZ_32K / 512,
  1224. SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
  1225. SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
  1226. SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
  1227. SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
  1228. SZ_64M / 512,
  1229. };
  1230. int err, i;
  1231. struct mmc_cmd cmd;
  1232. ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
  1233. struct mmc_data data;
  1234. unsigned int au, eo, et, es;
  1235. cmd.cmdidx = MMC_CMD_APP_CMD;
  1236. cmd.resp_type = MMC_RSP_R1;
  1237. cmd.cmdarg = mmc->rca << 16;
  1238. err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_APP_CMD, 4);
  1239. if (err)
  1240. return err;
  1241. cmd.cmdidx = SD_CMD_APP_SD_STATUS;
  1242. cmd.resp_type = MMC_RSP_R1;
  1243. cmd.cmdarg = 0;
  1244. data.dest = (char *)ssr;
  1245. data.blocksize = 64;
  1246. data.blocks = 1;
  1247. data.flags = MMC_DATA_READ;
  1248. err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
  1249. if (err)
  1250. return err;
  1251. for (i = 0; i < 16; i++)
  1252. ssr[i] = be32_to_cpu(ssr[i]);
  1253. au = (ssr[2] >> 12) & 0xF;
  1254. if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
  1255. mmc->ssr.au = sd_au_size[au];
  1256. es = (ssr[3] >> 24) & 0xFF;
  1257. es |= (ssr[2] & 0xFF) << 8;
  1258. et = (ssr[3] >> 18) & 0x3F;
  1259. if (es && et) {
  1260. eo = (ssr[3] >> 16) & 0x3;
  1261. mmc->ssr.erase_timeout = (et * 1000) / es;
  1262. mmc->ssr.erase_offset = eo * 1000;
  1263. }
  1264. } else {
  1265. pr_debug("Invalid Allocation Unit Size.\n");
  1266. }
  1267. return 0;
  1268. }
  1269. #endif
  1270. /* frequency bases */
  1271. /* divided by 10 to be nice to platforms without floating point */
  1272. static const int fbase[] = {
  1273. 10000,
  1274. 100000,
  1275. 1000000,
  1276. 10000000,
  1277. };
  1278. /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
  1279. * to platforms without floating point.
  1280. */
  1281. static const u8 multipliers[] = {
  1282. 0, /* reserved */
  1283. 10,
  1284. 12,
  1285. 13,
  1286. 15,
  1287. 20,
  1288. 25,
  1289. 30,
  1290. 35,
  1291. 40,
  1292. 45,
  1293. 50,
  1294. 55,
  1295. 60,
  1296. 70,
  1297. 80,
  1298. };
  1299. static inline int bus_width(uint cap)
  1300. {
  1301. if (cap == MMC_MODE_8BIT)
  1302. return 8;
  1303. if (cap == MMC_MODE_4BIT)
  1304. return 4;
  1305. if (cap == MMC_MODE_1BIT)
  1306. return 1;
  1307. pr_warn("invalid bus witdh capability 0x%x\n", cap);
  1308. return 0;
  1309. }
  1310. #if !CONFIG_IS_ENABLED(DM_MMC)
  1311. #ifdef MMC_SUPPORTS_TUNING
  1312. static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
  1313. {
  1314. return -ENOTSUPP;
  1315. }
  1316. #endif
  1317. static int mmc_set_ios(struct mmc *mmc)
  1318. {
  1319. int ret = 0;
  1320. if (mmc->cfg->ops->set_ios)
  1321. ret = mmc->cfg->ops->set_ios(mmc);
  1322. return ret;
  1323. }
  1324. static int mmc_host_power_cycle(struct mmc *mmc)
  1325. {
  1326. int ret = 0;
  1327. if (mmc->cfg->ops->host_power_cycle)
  1328. ret = mmc->cfg->ops->host_power_cycle(mmc);
  1329. return ret;
  1330. }
  1331. #endif
  1332. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
  1333. {
  1334. if (!disable) {
  1335. if (clock > mmc->cfg->f_max)
  1336. clock = mmc->cfg->f_max;
  1337. if (clock < mmc->cfg->f_min)
  1338. clock = mmc->cfg->f_min;
  1339. }
  1340. mmc->clock = clock;
  1341. mmc->clk_disable = disable;
  1342. debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
  1343. return mmc_set_ios(mmc);
  1344. }
  1345. static int mmc_set_bus_width(struct mmc *mmc, uint width)
  1346. {
  1347. mmc->bus_width = width;
  1348. return mmc_set_ios(mmc);
  1349. }
  1350. #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
  1351. /*
  1352. * helper function to display the capabilities in a human
  1353. * friendly manner. The capabilities include bus width and
  1354. * supported modes.
  1355. */
  1356. void mmc_dump_capabilities(const char *text, uint caps)
  1357. {
  1358. enum bus_mode mode;
  1359. pr_debug("%s: widths [", text);
  1360. if (caps & MMC_MODE_8BIT)
  1361. pr_debug("8, ");
  1362. if (caps & MMC_MODE_4BIT)
  1363. pr_debug("4, ");
  1364. if (caps & MMC_MODE_1BIT)
  1365. pr_debug("1, ");
  1366. pr_debug("\b\b] modes [");
  1367. for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
  1368. if (MMC_CAP(mode) & caps)
  1369. pr_debug("%s, ", mmc_mode_name(mode));
  1370. pr_debug("\b\b]\n");
  1371. }
  1372. #endif
  1373. struct mode_width_tuning {
  1374. enum bus_mode mode;
  1375. uint widths;
  1376. #ifdef MMC_SUPPORTS_TUNING
  1377. uint tuning;
  1378. #endif
  1379. };
  1380. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1381. int mmc_voltage_to_mv(enum mmc_voltage voltage)
  1382. {
  1383. switch (voltage) {
  1384. case MMC_SIGNAL_VOLTAGE_000: return 0;
  1385. case MMC_SIGNAL_VOLTAGE_330: return 3300;
  1386. case MMC_SIGNAL_VOLTAGE_180: return 1800;
  1387. case MMC_SIGNAL_VOLTAGE_120: return 1200;
  1388. }
  1389. return -EINVAL;
  1390. }
  1391. static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
  1392. {
  1393. int err;
  1394. if (mmc->signal_voltage == signal_voltage)
  1395. return 0;
  1396. mmc->signal_voltage = signal_voltage;
  1397. err = mmc_set_ios(mmc);
  1398. if (err)
  1399. pr_debug("unable to set voltage (err %d)\n", err);
  1400. return err;
  1401. }
  1402. #else
  1403. static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
  1404. {
  1405. return 0;
  1406. }
  1407. #endif
  1408. #if !CONFIG_IS_ENABLED(MMC_TINY)
  1409. static const struct mode_width_tuning sd_modes_by_pref[] = {
  1410. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1411. #ifdef MMC_SUPPORTS_TUNING
  1412. {
  1413. .mode = UHS_SDR104,
  1414. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1415. .tuning = MMC_CMD_SEND_TUNING_BLOCK
  1416. },
  1417. #endif
  1418. {
  1419. .mode = UHS_SDR50,
  1420. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1421. },
  1422. {
  1423. .mode = UHS_DDR50,
  1424. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1425. },
  1426. {
  1427. .mode = UHS_SDR25,
  1428. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1429. },
  1430. #endif
  1431. {
  1432. .mode = SD_HS,
  1433. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1434. },
  1435. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1436. {
  1437. .mode = UHS_SDR12,
  1438. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1439. },
  1440. #endif
  1441. {
  1442. .mode = MMC_LEGACY,
  1443. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1444. }
  1445. };
  1446. #define for_each_sd_mode_by_pref(caps, mwt) \
  1447. for (mwt = sd_modes_by_pref;\
  1448. mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
  1449. mwt++) \
  1450. if (caps & MMC_CAP(mwt->mode))
  1451. static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
  1452. {
  1453. int err;
  1454. uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
  1455. const struct mode_width_tuning *mwt;
  1456. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1457. bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
  1458. #else
  1459. bool uhs_en = false;
  1460. #endif
  1461. uint caps;
  1462. #ifdef DEBUG
  1463. mmc_dump_capabilities("sd card", card_caps);
  1464. mmc_dump_capabilities("host", mmc->host_caps);
  1465. #endif
  1466. if (mmc_host_is_spi(mmc)) {
  1467. mmc_set_bus_width(mmc, 1);
  1468. mmc_select_mode(mmc, MMC_LEGACY);
  1469. mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
  1470. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1471. err = sd_read_ssr(mmc);
  1472. if (err)
  1473. pr_warn("unable to read ssr\n");
  1474. #endif
  1475. return 0;
  1476. }
  1477. /* Restrict card's capabilities by what the host can do */
  1478. caps = card_caps & mmc->host_caps;
  1479. if (!uhs_en)
  1480. caps &= ~UHS_CAPS;
  1481. for_each_sd_mode_by_pref(caps, mwt) {
  1482. uint *w;
  1483. for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
  1484. if (*w & caps & mwt->widths) {
  1485. pr_debug("trying mode %s width %d (at %d MHz)\n",
  1486. mmc_mode_name(mwt->mode),
  1487. bus_width(*w),
  1488. mmc_mode2freq(mmc, mwt->mode) / 1000000);
  1489. /* configure the bus width (card + host) */
  1490. err = sd_select_bus_width(mmc, bus_width(*w));
  1491. if (err)
  1492. goto error;
  1493. mmc_set_bus_width(mmc, bus_width(*w));
  1494. /* configure the bus mode (card) */
  1495. err = sd_set_card_speed(mmc, mwt->mode);
  1496. if (err)
  1497. goto error;
  1498. /* configure the bus mode (host) */
  1499. mmc_select_mode(mmc, mwt->mode);
  1500. mmc_set_clock(mmc, mmc->tran_speed,
  1501. MMC_CLK_ENABLE);
  1502. #ifdef MMC_SUPPORTS_TUNING
  1503. /* execute tuning if needed */
  1504. if (mwt->tuning && !mmc_host_is_spi(mmc)) {
  1505. err = mmc_execute_tuning(mmc,
  1506. mwt->tuning);
  1507. if (err) {
  1508. pr_debug("tuning failed\n");
  1509. goto error;
  1510. }
  1511. }
  1512. #endif
  1513. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1514. err = sd_read_ssr(mmc);
  1515. if (err)
  1516. pr_warn("unable to read ssr\n");
  1517. #endif
  1518. if (!err)
  1519. return 0;
  1520. error:
  1521. /* revert to a safer bus speed */
  1522. mmc_select_mode(mmc, MMC_LEGACY);
  1523. mmc_set_clock(mmc, mmc->tran_speed,
  1524. MMC_CLK_ENABLE);
  1525. }
  1526. }
  1527. }
  1528. pr_err("unable to select a mode\n");
  1529. return -ENOTSUPP;
  1530. }
  1531. /*
  1532. * read the compare the part of ext csd that is constant.
  1533. * This can be used to check that the transfer is working
  1534. * as expected.
  1535. */
  1536. static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
  1537. {
  1538. int err;
  1539. const u8 *ext_csd = mmc->ext_csd;
  1540. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  1541. if (mmc->version < MMC_VERSION_4)
  1542. return 0;
  1543. err = mmc_send_ext_csd(mmc, test_csd);
  1544. if (err)
  1545. return err;
  1546. /* Only compare read only fields */
  1547. if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
  1548. == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
  1549. ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
  1550. == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
  1551. ext_csd[EXT_CSD_REV]
  1552. == test_csd[EXT_CSD_REV] &&
  1553. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1554. == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
  1555. memcmp(&ext_csd[EXT_CSD_SEC_CNT],
  1556. &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
  1557. return 0;
  1558. return -EBADMSG;
  1559. }
  1560. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1561. static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
  1562. uint32_t allowed_mask)
  1563. {
  1564. u32 card_mask = 0;
  1565. switch (mode) {
  1566. case MMC_HS_400_ES:
  1567. case MMC_HS_400:
  1568. case MMC_HS_200:
  1569. if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
  1570. EXT_CSD_CARD_TYPE_HS400_1_8V))
  1571. card_mask |= MMC_SIGNAL_VOLTAGE_180;
  1572. if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
  1573. EXT_CSD_CARD_TYPE_HS400_1_2V))
  1574. card_mask |= MMC_SIGNAL_VOLTAGE_120;
  1575. break;
  1576. case MMC_DDR_52:
  1577. if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
  1578. card_mask |= MMC_SIGNAL_VOLTAGE_330 |
  1579. MMC_SIGNAL_VOLTAGE_180;
  1580. if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
  1581. card_mask |= MMC_SIGNAL_VOLTAGE_120;
  1582. break;
  1583. default:
  1584. card_mask |= MMC_SIGNAL_VOLTAGE_330;
  1585. break;
  1586. }
  1587. while (card_mask & allowed_mask) {
  1588. enum mmc_voltage best_match;
  1589. best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
  1590. if (!mmc_set_signal_voltage(mmc, best_match))
  1591. return 0;
  1592. allowed_mask &= ~best_match;
  1593. }
  1594. return -ENOTSUPP;
  1595. }
  1596. #else
  1597. static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
  1598. uint32_t allowed_mask)
  1599. {
  1600. return 0;
  1601. }
  1602. #endif
  1603. static const struct mode_width_tuning mmc_modes_by_pref[] = {
  1604. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1605. {
  1606. .mode = MMC_HS_400_ES,
  1607. .widths = MMC_MODE_8BIT,
  1608. },
  1609. #endif
  1610. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  1611. {
  1612. .mode = MMC_HS_400,
  1613. .widths = MMC_MODE_8BIT,
  1614. .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
  1615. },
  1616. #endif
  1617. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  1618. {
  1619. .mode = MMC_HS_200,
  1620. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  1621. .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
  1622. },
  1623. #endif
  1624. {
  1625. .mode = MMC_DDR_52,
  1626. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  1627. },
  1628. {
  1629. .mode = MMC_HS_52,
  1630. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1631. },
  1632. {
  1633. .mode = MMC_HS,
  1634. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1635. },
  1636. {
  1637. .mode = MMC_LEGACY,
  1638. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1639. }
  1640. };
  1641. #define for_each_mmc_mode_by_pref(caps, mwt) \
  1642. for (mwt = mmc_modes_by_pref;\
  1643. mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
  1644. mwt++) \
  1645. if (caps & MMC_CAP(mwt->mode))
  1646. static const struct ext_csd_bus_width {
  1647. uint cap;
  1648. bool is_ddr;
  1649. uint ext_csd_bits;
  1650. } ext_csd_bus_width[] = {
  1651. {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
  1652. {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
  1653. {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
  1654. {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
  1655. {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
  1656. };
  1657. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  1658. static int mmc_select_hs400(struct mmc *mmc)
  1659. {
  1660. int err;
  1661. /* Set timing to HS200 for tuning */
  1662. err = mmc_set_card_speed(mmc, MMC_HS_200, false);
  1663. if (err)
  1664. return err;
  1665. /* configure the bus mode (host) */
  1666. mmc_select_mode(mmc, MMC_HS_200);
  1667. mmc_set_clock(mmc, mmc->tran_speed, false);
  1668. /* execute tuning if needed */
  1669. mmc->hs400_tuning = 1;
  1670. err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
  1671. mmc->hs400_tuning = 0;
  1672. if (err) {
  1673. debug("tuning failed\n");
  1674. return err;
  1675. }
  1676. /* Set back to HS */
  1677. mmc_set_card_speed(mmc, MMC_HS, true);
  1678. err = mmc_hs400_prepare_ddr(mmc);
  1679. if (err)
  1680. return err;
  1681. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
  1682. EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
  1683. if (err)
  1684. return err;
  1685. err = mmc_set_card_speed(mmc, MMC_HS_400, false);
  1686. if (err)
  1687. return err;
  1688. mmc_select_mode(mmc, MMC_HS_400);
  1689. err = mmc_set_clock(mmc, mmc->tran_speed, false);
  1690. if (err)
  1691. return err;
  1692. return 0;
  1693. }
  1694. #else
  1695. static int mmc_select_hs400(struct mmc *mmc)
  1696. {
  1697. return -ENOTSUPP;
  1698. }
  1699. #endif
  1700. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1701. #if !CONFIG_IS_ENABLED(DM_MMC)
  1702. static int mmc_set_enhanced_strobe(struct mmc *mmc)
  1703. {
  1704. return -ENOTSUPP;
  1705. }
  1706. #endif
  1707. static int mmc_select_hs400es(struct mmc *mmc)
  1708. {
  1709. int err;
  1710. err = mmc_set_card_speed(mmc, MMC_HS, true);
  1711. if (err)
  1712. return err;
  1713. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
  1714. EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
  1715. EXT_CSD_BUS_WIDTH_STROBE);
  1716. if (err) {
  1717. printf("switch to bus width for hs400 failed\n");
  1718. return err;
  1719. }
  1720. /* TODO: driver strength */
  1721. err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
  1722. if (err)
  1723. return err;
  1724. mmc_select_mode(mmc, MMC_HS_400_ES);
  1725. err = mmc_set_clock(mmc, mmc->tran_speed, false);
  1726. if (err)
  1727. return err;
  1728. return mmc_set_enhanced_strobe(mmc);
  1729. }
  1730. #else
  1731. static int mmc_select_hs400es(struct mmc *mmc)
  1732. {
  1733. return -ENOTSUPP;
  1734. }
  1735. #endif
  1736. #define for_each_supported_width(caps, ddr, ecbv) \
  1737. for (ecbv = ext_csd_bus_width;\
  1738. ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
  1739. ecbv++) \
  1740. if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
  1741. static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
  1742. {
  1743. int err;
  1744. const struct mode_width_tuning *mwt;
  1745. const struct ext_csd_bus_width *ecbw;
  1746. #ifdef DEBUG
  1747. mmc_dump_capabilities("mmc", card_caps);
  1748. mmc_dump_capabilities("host", mmc->host_caps);
  1749. #endif
  1750. if (mmc_host_is_spi(mmc)) {
  1751. mmc_set_bus_width(mmc, 1);
  1752. mmc_select_mode(mmc, MMC_LEGACY);
  1753. mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
  1754. return 0;
  1755. }
  1756. /* Restrict card's capabilities by what the host can do */
  1757. card_caps &= mmc->host_caps;
  1758. /* Only version 4 of MMC supports wider bus widths */
  1759. if (mmc->version < MMC_VERSION_4)
  1760. return 0;
  1761. if (!mmc->ext_csd) {
  1762. pr_debug("No ext_csd found!\n"); /* this should enver happen */
  1763. return -ENOTSUPP;
  1764. }
  1765. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  1766. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  1767. /*
  1768. * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
  1769. * before doing anything else, since a transition from either of
  1770. * the HS200/HS400 mode directly to legacy mode is not supported.
  1771. */
  1772. if (mmc->selected_mode == MMC_HS_200 ||
  1773. mmc->selected_mode == MMC_HS_400)
  1774. mmc_set_card_speed(mmc, MMC_HS, true);
  1775. else
  1776. #endif
  1777. mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
  1778. for_each_mmc_mode_by_pref(card_caps, mwt) {
  1779. for_each_supported_width(card_caps & mwt->widths,
  1780. mmc_is_mode_ddr(mwt->mode), ecbw) {
  1781. enum mmc_voltage old_voltage;
  1782. pr_debug("trying mode %s width %d (at %d MHz)\n",
  1783. mmc_mode_name(mwt->mode),
  1784. bus_width(ecbw->cap),
  1785. mmc_mode2freq(mmc, mwt->mode) / 1000000);
  1786. old_voltage = mmc->signal_voltage;
  1787. err = mmc_set_lowest_voltage(mmc, mwt->mode,
  1788. MMC_ALL_SIGNAL_VOLTAGE);
  1789. if (err)
  1790. continue;
  1791. /* configure the bus width (card + host) */
  1792. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1793. EXT_CSD_BUS_WIDTH,
  1794. ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
  1795. if (err)
  1796. goto error;
  1797. mmc_set_bus_width(mmc, bus_width(ecbw->cap));
  1798. if (mwt->mode == MMC_HS_400) {
  1799. err = mmc_select_hs400(mmc);
  1800. if (err) {
  1801. printf("Select HS400 failed %d\n", err);
  1802. goto error;
  1803. }
  1804. } else if (mwt->mode == MMC_HS_400_ES) {
  1805. err = mmc_select_hs400es(mmc);
  1806. if (err) {
  1807. printf("Select HS400ES failed %d\n",
  1808. err);
  1809. goto error;
  1810. }
  1811. } else {
  1812. /* configure the bus speed (card) */
  1813. err = mmc_set_card_speed(mmc, mwt->mode, false);
  1814. if (err)
  1815. goto error;
  1816. /*
  1817. * configure the bus width AND the ddr mode
  1818. * (card). The host side will be taken care
  1819. * of in the next step
  1820. */
  1821. if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
  1822. err = mmc_switch(mmc,
  1823. EXT_CSD_CMD_SET_NORMAL,
  1824. EXT_CSD_BUS_WIDTH,
  1825. ecbw->ext_csd_bits);
  1826. if (err)
  1827. goto error;
  1828. }
  1829. /* configure the bus mode (host) */
  1830. mmc_select_mode(mmc, mwt->mode);
  1831. mmc_set_clock(mmc, mmc->tran_speed,
  1832. MMC_CLK_ENABLE);
  1833. #ifdef MMC_SUPPORTS_TUNING
  1834. /* execute tuning if needed */
  1835. if (mwt->tuning) {
  1836. err = mmc_execute_tuning(mmc,
  1837. mwt->tuning);
  1838. if (err) {
  1839. pr_debug("tuning failed : %d\n", err);
  1840. goto error;
  1841. }
  1842. }
  1843. #endif
  1844. }
  1845. /* do a transfer to check the configuration */
  1846. err = mmc_read_and_compare_ext_csd(mmc);
  1847. if (!err)
  1848. return 0;
  1849. error:
  1850. mmc_set_signal_voltage(mmc, old_voltage);
  1851. /* if an error occurred, revert to a safer bus mode */
  1852. mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1853. EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
  1854. mmc_select_mode(mmc, MMC_LEGACY);
  1855. mmc_set_bus_width(mmc, 1);
  1856. }
  1857. }
  1858. pr_err("unable to select a mode : %d\n", err);
  1859. return -ENOTSUPP;
  1860. }
  1861. #endif
  1862. #if CONFIG_IS_ENABLED(MMC_TINY)
  1863. DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
  1864. #endif
  1865. static int mmc_startup_v4(struct mmc *mmc)
  1866. {
  1867. int err, i;
  1868. u64 capacity;
  1869. bool has_parts = false;
  1870. bool part_completed;
  1871. static const u32 mmc_versions[] = {
  1872. MMC_VERSION_4,
  1873. MMC_VERSION_4_1,
  1874. MMC_VERSION_4_2,
  1875. MMC_VERSION_4_3,
  1876. MMC_VERSION_4_4,
  1877. MMC_VERSION_4_41,
  1878. MMC_VERSION_4_5,
  1879. MMC_VERSION_5_0,
  1880. MMC_VERSION_5_1
  1881. };
  1882. #if CONFIG_IS_ENABLED(MMC_TINY)
  1883. u8 *ext_csd = ext_csd_bkup;
  1884. if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
  1885. return 0;
  1886. if (!mmc->ext_csd)
  1887. memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
  1888. err = mmc_send_ext_csd(mmc, ext_csd);
  1889. if (err)
  1890. goto error;
  1891. /* store the ext csd for future reference */
  1892. if (!mmc->ext_csd)
  1893. mmc->ext_csd = ext_csd;
  1894. #else
  1895. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  1896. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
  1897. return 0;
  1898. /* check ext_csd version and capacity */
  1899. err = mmc_send_ext_csd(mmc, ext_csd);
  1900. if (err)
  1901. goto error;
  1902. /* store the ext csd for future reference */
  1903. if (!mmc->ext_csd)
  1904. mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
  1905. if (!mmc->ext_csd)
  1906. return -ENOMEM;
  1907. memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
  1908. #endif
  1909. if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
  1910. return -EINVAL;
  1911. mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
  1912. if (mmc->version >= MMC_VERSION_4_2) {
  1913. /*
  1914. * According to the JEDEC Standard, the value of
  1915. * ext_csd's capacity is valid if the value is more
  1916. * than 2GB
  1917. */
  1918. capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
  1919. | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
  1920. | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
  1921. | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
  1922. capacity *= MMC_MAX_BLOCK_LEN;
  1923. if ((capacity >> 20) > 2 * 1024)
  1924. mmc->capacity_user = capacity;
  1925. }
  1926. if (mmc->version >= MMC_VERSION_4_5)
  1927. mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
  1928. /* The partition data may be non-zero but it is only
  1929. * effective if PARTITION_SETTING_COMPLETED is set in
  1930. * EXT_CSD, so ignore any data if this bit is not set,
  1931. * except for enabling the high-capacity group size
  1932. * definition (see below).
  1933. */
  1934. part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
  1935. EXT_CSD_PARTITION_SETTING_COMPLETED);
  1936. mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
  1937. /* Some eMMC set the value too low so set a minimum */
  1938. if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
  1939. mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
  1940. /* store the partition info of emmc */
  1941. mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
  1942. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
  1943. ext_csd[EXT_CSD_BOOT_MULT])
  1944. mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
  1945. if (part_completed &&
  1946. (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
  1947. mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
  1948. mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
  1949. mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
  1950. for (i = 0; i < 4; i++) {
  1951. int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
  1952. uint mult = (ext_csd[idx + 2] << 16) +
  1953. (ext_csd[idx + 1] << 8) + ext_csd[idx];
  1954. if (mult)
  1955. has_parts = true;
  1956. if (!part_completed)
  1957. continue;
  1958. mmc->capacity_gp[i] = mult;
  1959. mmc->capacity_gp[i] *=
  1960. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1961. mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1962. mmc->capacity_gp[i] <<= 19;
  1963. }
  1964. #ifndef CONFIG_SPL_BUILD
  1965. if (part_completed) {
  1966. mmc->enh_user_size =
  1967. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
  1968. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
  1969. ext_csd[EXT_CSD_ENH_SIZE_MULT];
  1970. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1971. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1972. mmc->enh_user_size <<= 19;
  1973. mmc->enh_user_start =
  1974. (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
  1975. (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
  1976. (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
  1977. ext_csd[EXT_CSD_ENH_START_ADDR];
  1978. if (mmc->high_capacity)
  1979. mmc->enh_user_start <<= 9;
  1980. }
  1981. #endif
  1982. /*
  1983. * Host needs to enable ERASE_GRP_DEF bit if device is
  1984. * partitioned. This bit will be lost every time after a reset
  1985. * or power off. This will affect erase size.
  1986. */
  1987. if (part_completed)
  1988. has_parts = true;
  1989. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
  1990. (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
  1991. has_parts = true;
  1992. if (has_parts) {
  1993. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1994. EXT_CSD_ERASE_GROUP_DEF, 1);
  1995. if (err)
  1996. goto error;
  1997. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  1998. }
  1999. if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
  2000. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2001. /* Read out group size from ext_csd */
  2002. mmc->erase_grp_size =
  2003. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  2004. #endif
  2005. /*
  2006. * if high capacity and partition setting completed
  2007. * SEC_COUNT is valid even if it is smaller than 2 GiB
  2008. * JEDEC Standard JESD84-B45, 6.2.4
  2009. */
  2010. if (mmc->high_capacity && part_completed) {
  2011. capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
  2012. (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
  2013. (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
  2014. (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
  2015. capacity *= MMC_MAX_BLOCK_LEN;
  2016. mmc->capacity_user = capacity;
  2017. }
  2018. }
  2019. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2020. else {
  2021. /* Calculate the group size from the csd value. */
  2022. int erase_gsz, erase_gmul;
  2023. erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
  2024. erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
  2025. mmc->erase_grp_size = (erase_gsz + 1)
  2026. * (erase_gmul + 1);
  2027. }
  2028. #endif
  2029. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  2030. mmc->hc_wp_grp_size = 1024
  2031. * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  2032. * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  2033. #endif
  2034. mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  2035. return 0;
  2036. error:
  2037. if (mmc->ext_csd) {
  2038. #if !CONFIG_IS_ENABLED(MMC_TINY)
  2039. free(mmc->ext_csd);
  2040. #endif
  2041. mmc->ext_csd = NULL;
  2042. }
  2043. return err;
  2044. }
  2045. static int mmc_startup(struct mmc *mmc)
  2046. {
  2047. int err, i;
  2048. uint mult, freq;
  2049. u64 cmult, csize;
  2050. struct mmc_cmd cmd;
  2051. struct blk_desc *bdesc;
  2052. #ifdef CONFIG_MMC_SPI_CRC_ON
  2053. if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
  2054. cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
  2055. cmd.resp_type = MMC_RSP_R1;
  2056. cmd.cmdarg = 1;
  2057. err = mmc_send_cmd(mmc, &cmd, NULL);
  2058. if (err)
  2059. return err;
  2060. }
  2061. #endif
  2062. /* Put the Card in Identify Mode */
  2063. cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
  2064. MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
  2065. cmd.resp_type = MMC_RSP_R2;
  2066. cmd.cmdarg = 0;
  2067. err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_SEND_CID, 4);
  2068. if (err)
  2069. return err;
  2070. memcpy(mmc->cid, cmd.response, 16);
  2071. /*
  2072. * For MMC cards, set the Relative Address.
  2073. * For SD cards, get the Relatvie Address.
  2074. * This also puts the cards into Standby State
  2075. */
  2076. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  2077. cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
  2078. cmd.cmdarg = mmc->rca << 16;
  2079. cmd.resp_type = MMC_RSP_R6;
  2080. err = mmc_send_cmd(mmc, &cmd, NULL);
  2081. if (err)
  2082. return err;
  2083. if (IS_SD(mmc))
  2084. mmc->rca = (cmd.response[0] >> 16) & 0xffff;
  2085. }
  2086. /* Get the Card-Specific Data */
  2087. cmd.cmdidx = MMC_CMD_SEND_CSD;
  2088. cmd.resp_type = MMC_RSP_R2;
  2089. cmd.cmdarg = mmc->rca << 16;
  2090. err = mmc_send_cmd(mmc, &cmd, NULL);
  2091. if (err)
  2092. return err;
  2093. mmc->csd[0] = cmd.response[0];
  2094. mmc->csd[1] = cmd.response[1];
  2095. mmc->csd[2] = cmd.response[2];
  2096. mmc->csd[3] = cmd.response[3];
  2097. if (mmc->version == MMC_VERSION_UNKNOWN) {
  2098. int version = (cmd.response[0] >> 26) & 0xf;
  2099. switch (version) {
  2100. case 0:
  2101. mmc->version = MMC_VERSION_1_2;
  2102. break;
  2103. case 1:
  2104. mmc->version = MMC_VERSION_1_4;
  2105. break;
  2106. case 2:
  2107. mmc->version = MMC_VERSION_2_2;
  2108. break;
  2109. case 3:
  2110. mmc->version = MMC_VERSION_3;
  2111. break;
  2112. case 4:
  2113. mmc->version = MMC_VERSION_4;
  2114. break;
  2115. default:
  2116. mmc->version = MMC_VERSION_1_2;
  2117. break;
  2118. }
  2119. }
  2120. /* divide frequency by 10, since the mults are 10x bigger */
  2121. freq = fbase[(cmd.response[0] & 0x7)];
  2122. mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
  2123. mmc->legacy_speed = freq * mult;
  2124. mmc_select_mode(mmc, MMC_LEGACY);
  2125. mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
  2126. mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
  2127. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2128. if (IS_SD(mmc))
  2129. mmc->write_bl_len = mmc->read_bl_len;
  2130. else
  2131. mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
  2132. #endif
  2133. if (mmc->high_capacity) {
  2134. csize = (mmc->csd[1] & 0x3f) << 16
  2135. | (mmc->csd[2] & 0xffff0000) >> 16;
  2136. cmult = 8;
  2137. } else {
  2138. csize = (mmc->csd[1] & 0x3ff) << 2
  2139. | (mmc->csd[2] & 0xc0000000) >> 30;
  2140. cmult = (mmc->csd[2] & 0x00038000) >> 15;
  2141. }
  2142. mmc->capacity_user = (csize + 1) << (cmult + 2);
  2143. mmc->capacity_user *= mmc->read_bl_len;
  2144. mmc->capacity_boot = 0;
  2145. mmc->capacity_rpmb = 0;
  2146. for (i = 0; i < 4; i++)
  2147. mmc->capacity_gp[i] = 0;
  2148. if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
  2149. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  2150. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2151. if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
  2152. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  2153. #endif
  2154. if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
  2155. cmd.cmdidx = MMC_CMD_SET_DSR;
  2156. cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
  2157. cmd.resp_type = MMC_RSP_NONE;
  2158. if (mmc_send_cmd(mmc, &cmd, NULL))
  2159. pr_warn("MMC: SET_DSR failed\n");
  2160. }
  2161. /* Select the card, and put it into Transfer Mode */
  2162. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  2163. cmd.cmdidx = MMC_CMD_SELECT_CARD;
  2164. cmd.resp_type = MMC_RSP_R1;
  2165. cmd.cmdarg = mmc->rca << 16;
  2166. err = mmc_send_cmd(mmc, &cmd, NULL);
  2167. if (err)
  2168. return err;
  2169. }
  2170. /*
  2171. * For SD, its erase group is always one sector
  2172. */
  2173. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2174. mmc->erase_grp_size = 1;
  2175. #endif
  2176. mmc->part_config = MMCPART_NOAVAILABLE;
  2177. err = mmc_startup_v4(mmc);
  2178. if (err)
  2179. return err;
  2180. err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
  2181. if (err)
  2182. return err;
  2183. #if CONFIG_IS_ENABLED(MMC_TINY)
  2184. mmc_set_clock(mmc, mmc->legacy_speed, false);
  2185. mmc_select_mode(mmc, MMC_LEGACY);
  2186. mmc_set_bus_width(mmc, 1);
  2187. #else
  2188. if (IS_SD(mmc)) {
  2189. err = sd_get_capabilities(mmc);
  2190. if (err)
  2191. return err;
  2192. err = sd_select_mode_and_width(mmc, mmc->card_caps);
  2193. } else {
  2194. err = mmc_get_capabilities(mmc);
  2195. if (err)
  2196. return err;
  2197. err = mmc_select_mode_and_width(mmc, mmc->card_caps);
  2198. }
  2199. #endif
  2200. if (err)
  2201. return err;
  2202. mmc->best_mode = mmc->selected_mode;
  2203. /* Fix the block length for DDR mode */
  2204. if (mmc->ddr_mode) {
  2205. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  2206. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2207. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  2208. #endif
  2209. }
  2210. /* fill in device description */
  2211. bdesc = mmc_get_blk_desc(mmc);
  2212. bdesc->lun = 0;
  2213. bdesc->hwpart = 0;
  2214. bdesc->type = 0;
  2215. bdesc->blksz = mmc->read_bl_len;
  2216. bdesc->log2blksz = LOG2(bdesc->blksz);
  2217. bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  2218. #if !defined(CONFIG_SPL_BUILD) || \
  2219. (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
  2220. !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
  2221. sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
  2222. mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
  2223. (mmc->cid[3] >> 16) & 0xffff);
  2224. sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
  2225. (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
  2226. (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
  2227. (mmc->cid[2] >> 24) & 0xff);
  2228. sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
  2229. (mmc->cid[2] >> 16) & 0xf);
  2230. #else
  2231. bdesc->vendor[0] = 0;
  2232. bdesc->product[0] = 0;
  2233. bdesc->revision[0] = 0;
  2234. #endif
  2235. #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
  2236. part_init(bdesc);
  2237. #endif
  2238. return 0;
  2239. }
  2240. static int mmc_send_if_cond(struct mmc *mmc)
  2241. {
  2242. struct mmc_cmd cmd;
  2243. int err;
  2244. cmd.cmdidx = SD_CMD_SEND_IF_COND;
  2245. /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
  2246. cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
  2247. cmd.resp_type = MMC_RSP_R7;
  2248. err = mmc_send_cmd(mmc, &cmd, NULL);
  2249. if (err)
  2250. return err;
  2251. if ((cmd.response[0] & 0xff) != 0xaa)
  2252. return -EOPNOTSUPP;
  2253. else
  2254. mmc->version = SD_VERSION_2;
  2255. return 0;
  2256. }
  2257. #if !CONFIG_IS_ENABLED(DM_MMC)
  2258. /* board-specific MMC power initializations. */
  2259. __weak void board_mmc_power_init(void)
  2260. {
  2261. }
  2262. #endif
  2263. static int mmc_power_init(struct mmc *mmc)
  2264. {
  2265. #if CONFIG_IS_ENABLED(DM_MMC)
  2266. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  2267. int ret;
  2268. ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
  2269. &mmc->vmmc_supply);
  2270. if (ret)
  2271. pr_debug("%s: No vmmc supply\n", mmc->dev->name);
  2272. ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
  2273. &mmc->vqmmc_supply);
  2274. if (ret)
  2275. pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
  2276. #endif
  2277. #else /* !CONFIG_DM_MMC */
  2278. /*
  2279. * Driver model should use a regulator, as above, rather than calling
  2280. * out to board code.
  2281. */
  2282. board_mmc_power_init();
  2283. #endif
  2284. return 0;
  2285. }
  2286. /*
  2287. * put the host in the initial state:
  2288. * - turn on Vdd (card power supply)
  2289. * - configure the bus width and clock to minimal values
  2290. */
  2291. static void mmc_set_initial_state(struct mmc *mmc)
  2292. {
  2293. int err;
  2294. /* First try to set 3.3V. If it fails set to 1.8V */
  2295. err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
  2296. if (err != 0)
  2297. err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  2298. if (err != 0)
  2299. pr_warn("mmc: failed to set signal voltage\n");
  2300. mmc_select_mode(mmc, MMC_LEGACY);
  2301. mmc_set_bus_width(mmc, 1);
  2302. mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
  2303. }
  2304. static int mmc_power_on(struct mmc *mmc)
  2305. {
  2306. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
  2307. if (mmc->vmmc_supply) {
  2308. int ret = regulator_set_enable(mmc->vmmc_supply, true);
  2309. if (ret && ret != -EACCES) {
  2310. printf("Error enabling VMMC supply : %d\n", ret);
  2311. return ret;
  2312. }
  2313. }
  2314. #endif
  2315. return 0;
  2316. }
  2317. static int mmc_power_off(struct mmc *mmc)
  2318. {
  2319. mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
  2320. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
  2321. if (mmc->vmmc_supply) {
  2322. int ret = regulator_set_enable(mmc->vmmc_supply, false);
  2323. if (ret && ret != -EACCES) {
  2324. pr_debug("Error disabling VMMC supply : %d\n", ret);
  2325. return ret;
  2326. }
  2327. }
  2328. #endif
  2329. return 0;
  2330. }
  2331. static int mmc_power_cycle(struct mmc *mmc)
  2332. {
  2333. int ret;
  2334. ret = mmc_power_off(mmc);
  2335. if (ret)
  2336. return ret;
  2337. ret = mmc_host_power_cycle(mmc);
  2338. if (ret)
  2339. return ret;
  2340. /*
  2341. * SD spec recommends at least 1ms of delay. Let's wait for 2ms
  2342. * to be on the safer side.
  2343. */
  2344. udelay(2000);
  2345. return mmc_power_on(mmc);
  2346. }
  2347. int mmc_get_op_cond(struct mmc *mmc)
  2348. {
  2349. bool uhs_en = supports_uhs(mmc->cfg->host_caps);
  2350. int err;
  2351. if (mmc->has_init)
  2352. return 0;
  2353. err = mmc_power_init(mmc);
  2354. if (err)
  2355. return err;
  2356. #ifdef CONFIG_MMC_QUIRKS
  2357. mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
  2358. MMC_QUIRK_RETRY_SEND_CID |
  2359. MMC_QUIRK_RETRY_APP_CMD;
  2360. #endif
  2361. err = mmc_power_cycle(mmc);
  2362. if (err) {
  2363. /*
  2364. * if power cycling is not supported, we should not try
  2365. * to use the UHS modes, because we wouldn't be able to
  2366. * recover from an error during the UHS initialization.
  2367. */
  2368. pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
  2369. uhs_en = false;
  2370. mmc->host_caps &= ~UHS_CAPS;
  2371. err = mmc_power_on(mmc);
  2372. }
  2373. if (err)
  2374. return err;
  2375. #if CONFIG_IS_ENABLED(DM_MMC)
  2376. /*
  2377. * Re-initialization is needed to clear old configuration for
  2378. * mmc rescan.
  2379. */
  2380. err = mmc_reinit(mmc);
  2381. #else
  2382. /* made sure it's not NULL earlier */
  2383. err = mmc->cfg->ops->init(mmc);
  2384. #endif
  2385. if (err)
  2386. return err;
  2387. mmc->ddr_mode = 0;
  2388. retry:
  2389. mmc_set_initial_state(mmc);
  2390. /* Reset the Card */
  2391. err = mmc_go_idle(mmc);
  2392. if (err)
  2393. return err;
  2394. /* The internal partition reset to user partition(0) at every CMD0 */
  2395. mmc_get_blk_desc(mmc)->hwpart = 0;
  2396. /* Test for SD version 2 */
  2397. err = mmc_send_if_cond(mmc);
  2398. /* Now try to get the SD card's operating condition */
  2399. err = sd_send_op_cond(mmc, uhs_en);
  2400. if (err && uhs_en) {
  2401. uhs_en = false;
  2402. mmc_power_cycle(mmc);
  2403. goto retry;
  2404. }
  2405. /* If the command timed out, we check for an MMC card */
  2406. if (err == -ETIMEDOUT) {
  2407. err = mmc_send_op_cond(mmc);
  2408. if (err) {
  2409. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  2410. pr_err("Card did not respond to voltage select! : %d\n", err);
  2411. #endif
  2412. return -EOPNOTSUPP;
  2413. }
  2414. }
  2415. return err;
  2416. }
  2417. int mmc_start_init(struct mmc *mmc)
  2418. {
  2419. bool no_card;
  2420. int err = 0;
  2421. /*
  2422. * all hosts are capable of 1 bit bus-width and able to use the legacy
  2423. * timings.
  2424. */
  2425. mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
  2426. MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
  2427. #if CONFIG_IS_ENABLED(DM_MMC)
  2428. mmc_deferred_probe(mmc);
  2429. #endif
  2430. #if !defined(CONFIG_MMC_BROKEN_CD)
  2431. no_card = mmc_getcd(mmc) == 0;
  2432. #else
  2433. no_card = 0;
  2434. #endif
  2435. #if !CONFIG_IS_ENABLED(DM_MMC)
  2436. /* we pretend there's no card when init is NULL */
  2437. no_card = no_card || (mmc->cfg->ops->init == NULL);
  2438. #endif
  2439. if (no_card) {
  2440. mmc->has_init = 0;
  2441. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  2442. pr_err("MMC: no card present\n");
  2443. #endif
  2444. return -ENOMEDIUM;
  2445. }
  2446. err = mmc_get_op_cond(mmc);
  2447. if (!err)
  2448. mmc->init_in_progress = 1;
  2449. return err;
  2450. }
  2451. static int mmc_complete_init(struct mmc *mmc)
  2452. {
  2453. int err = 0;
  2454. mmc->init_in_progress = 0;
  2455. if (mmc->op_cond_pending)
  2456. err = mmc_complete_op_cond(mmc);
  2457. if (!err)
  2458. err = mmc_startup(mmc);
  2459. if (err)
  2460. mmc->has_init = 0;
  2461. else
  2462. mmc->has_init = 1;
  2463. return err;
  2464. }
  2465. int mmc_init(struct mmc *mmc)
  2466. {
  2467. int err = 0;
  2468. __maybe_unused ulong start;
  2469. #if CONFIG_IS_ENABLED(DM_MMC)
  2470. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
  2471. upriv->mmc = mmc;
  2472. #endif
  2473. if (mmc->has_init)
  2474. return 0;
  2475. start = get_timer(0);
  2476. if (!mmc->init_in_progress)
  2477. err = mmc_start_init(mmc);
  2478. if (!err)
  2479. err = mmc_complete_init(mmc);
  2480. if (err)
  2481. pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
  2482. return err;
  2483. }
  2484. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  2485. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  2486. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  2487. int mmc_deinit(struct mmc *mmc)
  2488. {
  2489. u32 caps_filtered;
  2490. if (!mmc->has_init)
  2491. return 0;
  2492. if (IS_SD(mmc)) {
  2493. caps_filtered = mmc->card_caps &
  2494. ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
  2495. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
  2496. MMC_CAP(UHS_SDR104));
  2497. return sd_select_mode_and_width(mmc, caps_filtered);
  2498. } else {
  2499. caps_filtered = mmc->card_caps &
  2500. ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
  2501. return mmc_select_mode_and_width(mmc, caps_filtered);
  2502. }
  2503. }
  2504. #endif
  2505. int mmc_set_dsr(struct mmc *mmc, u16 val)
  2506. {
  2507. mmc->dsr = val;
  2508. return 0;
  2509. }
  2510. /* CPU-specific MMC initializations */
  2511. __weak int cpu_mmc_init(struct bd_info *bis)
  2512. {
  2513. return -1;
  2514. }
  2515. /* board-specific MMC initializations. */
  2516. __weak int board_mmc_init(struct bd_info *bis)
  2517. {
  2518. return -1;
  2519. }
  2520. void mmc_set_preinit(struct mmc *mmc, int preinit)
  2521. {
  2522. mmc->preinit = preinit;
  2523. }
  2524. #if CONFIG_IS_ENABLED(DM_MMC)
  2525. static int mmc_probe(struct bd_info *bis)
  2526. {
  2527. int ret, i;
  2528. struct uclass *uc;
  2529. struct udevice *dev;
  2530. ret = uclass_get(UCLASS_MMC, &uc);
  2531. if (ret)
  2532. return ret;
  2533. /*
  2534. * Try to add them in sequence order. Really with driver model we
  2535. * should allow holes, but the current MMC list does not allow that.
  2536. * So if we request 0, 1, 3 we will get 0, 1, 2.
  2537. */
  2538. for (i = 0; ; i++) {
  2539. ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
  2540. if (ret == -ENODEV)
  2541. break;
  2542. }
  2543. uclass_foreach_dev(dev, uc) {
  2544. ret = device_probe(dev);
  2545. if (ret)
  2546. pr_err("%s - probe failed: %d\n", dev->name, ret);
  2547. }
  2548. return 0;
  2549. }
  2550. #else
  2551. static int mmc_probe(struct bd_info *bis)
  2552. {
  2553. if (board_mmc_init(bis) < 0)
  2554. cpu_mmc_init(bis);
  2555. return 0;
  2556. }
  2557. #endif
  2558. int mmc_initialize(struct bd_info *bis)
  2559. {
  2560. static int initialized = 0;
  2561. int ret;
  2562. if (initialized) /* Avoid initializing mmc multiple times */
  2563. return 0;
  2564. initialized = 1;
  2565. #if !CONFIG_IS_ENABLED(BLK)
  2566. #if !CONFIG_IS_ENABLED(MMC_TINY)
  2567. mmc_list_init();
  2568. #endif
  2569. #endif
  2570. ret = mmc_probe(bis);
  2571. if (ret)
  2572. return ret;
  2573. #ifndef CONFIG_SPL_BUILD
  2574. print_mmc_devices(',');
  2575. #endif
  2576. mmc_do_preinit();
  2577. return 0;
  2578. }
  2579. #if CONFIG_IS_ENABLED(DM_MMC)
  2580. int mmc_init_device(int num)
  2581. {
  2582. struct udevice *dev;
  2583. struct mmc *m;
  2584. int ret;
  2585. ret = uclass_get_device(UCLASS_MMC, num, &dev);
  2586. if (ret)
  2587. return ret;
  2588. m = mmc_get_mmc_dev(dev);
  2589. if (!m)
  2590. return 0;
  2591. if (m->preinit)
  2592. mmc_start_init(m);
  2593. return 0;
  2594. }
  2595. #endif
  2596. #ifdef CONFIG_CMD_BKOPS_ENABLE
  2597. int mmc_set_bkops_enable(struct mmc *mmc)
  2598. {
  2599. int err;
  2600. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  2601. err = mmc_send_ext_csd(mmc, ext_csd);
  2602. if (err) {
  2603. puts("Could not get ext_csd register values\n");
  2604. return err;
  2605. }
  2606. if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
  2607. puts("Background operations not supported on device\n");
  2608. return -EMEDIUMTYPE;
  2609. }
  2610. if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
  2611. puts("Background operations already enabled\n");
  2612. return 0;
  2613. }
  2614. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
  2615. if (err) {
  2616. puts("Failed to enable manual background operations\n");
  2617. return err;
  2618. }
  2619. puts("Enabled manual background operations\n");
  2620. return 0;
  2621. }
  2622. #endif
  2623. __weak int mmc_get_env_dev(void)
  2624. {
  2625. #ifdef CONFIG_SYS_MMC_ENV_DEV
  2626. return CONFIG_SYS_MMC_ENV_DEV;
  2627. #else
  2628. return 0;
  2629. #endif
  2630. }