fsl_esdhc_imx.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019 NXP Semiconductors
  5. * Andy Fleming
  6. * Yangbo Lu <yangbo.lu@nxp.com>
  7. *
  8. * Based vaguely on the pxa mmc code:
  9. * (C) Copyright 2003
  10. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  11. */
  12. #include <config.h>
  13. #include <common.h>
  14. #include <command.h>
  15. #include <clk.h>
  16. #include <cpu_func.h>
  17. #include <errno.h>
  18. #include <hwconfig.h>
  19. #include <log.h>
  20. #include <mmc.h>
  21. #include <part.h>
  22. #include <asm/cache.h>
  23. #include <dm/device_compat.h>
  24. #include <linux/bitops.h>
  25. #include <linux/delay.h>
  26. #include <linux/err.h>
  27. #include <power/regulator.h>
  28. #include <malloc.h>
  29. #include <fsl_esdhc_imx.h>
  30. #include <fdt_support.h>
  31. #include <asm/io.h>
  32. #include <dm.h>
  33. #include <asm-generic/gpio.h>
  34. #include <dm/pinctrl.h>
  35. #include <dt-structs.h>
  36. #include <mapmem.h>
  37. #include <dm/ofnode.h>
  38. #include <linux/iopoll.h>
  39. #if !CONFIG_IS_ENABLED(BLK)
  40. #include "mmc_private.h"
  41. #endif
  42. DECLARE_GLOBAL_DATA_PTR;
  43. #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
  44. IRQSTATEN_CINT | \
  45. IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  46. IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  47. IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  48. IRQSTATEN_DINT)
  49. #define MAX_TUNING_LOOP 40
  50. #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
  51. struct fsl_esdhc {
  52. uint dsaddr; /* SDMA system address register */
  53. uint blkattr; /* Block attributes register */
  54. uint cmdarg; /* Command argument register */
  55. uint xfertyp; /* Transfer type register */
  56. uint cmdrsp0; /* Command response 0 register */
  57. uint cmdrsp1; /* Command response 1 register */
  58. uint cmdrsp2; /* Command response 2 register */
  59. uint cmdrsp3; /* Command response 3 register */
  60. uint datport; /* Buffer data port register */
  61. uint prsstat; /* Present state register */
  62. uint proctl; /* Protocol control register */
  63. uint sysctl; /* System Control Register */
  64. uint irqstat; /* Interrupt status register */
  65. uint irqstaten; /* Interrupt status enable register */
  66. uint irqsigen; /* Interrupt signal enable register */
  67. uint autoc12err; /* Auto CMD error status register */
  68. uint hostcapblt; /* Host controller capabilities register */
  69. uint wml; /* Watermark level register */
  70. uint mixctrl; /* For USDHC */
  71. char reserved1[4]; /* reserved */
  72. uint fevt; /* Force event register */
  73. uint admaes; /* ADMA error status register */
  74. uint adsaddr; /* ADMA system address register */
  75. char reserved2[4];
  76. uint dllctrl;
  77. uint dllstat;
  78. uint clktunectrlstatus;
  79. char reserved3[4];
  80. uint strobe_dllctrl;
  81. uint strobe_dllstat;
  82. char reserved4[72];
  83. uint vendorspec;
  84. uint mmcboot;
  85. uint vendorspec2;
  86. uint tuning_ctrl; /* on i.MX6/7/8/RT */
  87. char reserved5[44];
  88. uint hostver; /* Host controller version register */
  89. char reserved6[4]; /* reserved */
  90. uint dmaerraddr; /* DMA error address register */
  91. char reserved7[4]; /* reserved */
  92. uint dmaerrattr; /* DMA error attribute register */
  93. char reserved8[4]; /* reserved */
  94. uint hostcapblt2; /* Host controller capabilities register 2 */
  95. char reserved9[8]; /* reserved */
  96. uint tcr; /* Tuning control register */
  97. char reserved10[28]; /* reserved */
  98. uint sddirctl; /* SD direction control register */
  99. char reserved11[712];/* reserved */
  100. uint scr; /* eSDHC control register */
  101. };
  102. struct fsl_esdhc_plat {
  103. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  104. /* Put this first since driver model will copy the data here */
  105. struct dtd_fsl_esdhc dtplat;
  106. #endif
  107. struct mmc_config cfg;
  108. struct mmc mmc;
  109. };
  110. struct esdhc_soc_data {
  111. u32 flags;
  112. };
  113. /**
  114. * struct fsl_esdhc_priv
  115. *
  116. * @esdhc_regs: registers of the sdhc controller
  117. * @sdhc_clk: Current clk of the sdhc controller
  118. * @bus_width: bus width, 1bit, 4bit or 8bit
  119. * @cfg: mmc config
  120. * @mmc: mmc
  121. * Following is used when Driver Model is enabled for MMC
  122. * @dev: pointer for the device
  123. * @non_removable: 0: removable; 1: non-removable
  124. * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
  125. * @wp_enable: 1: enable checking wp; 0: no check
  126. * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
  127. * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
  128. * @caps: controller capabilities
  129. * @tuning_step: tuning step setting in tuning_ctrl register
  130. * @start_tuning_tap: the start point for tuning in tuning_ctrl register
  131. * @strobe_dll_delay_target: settings in strobe_dllctrl
  132. * @signal_voltage: indicating the current voltage
  133. * @cd_gpio: gpio for card detection
  134. * @wp_gpio: gpio for write protection
  135. */
  136. struct fsl_esdhc_priv {
  137. struct fsl_esdhc *esdhc_regs;
  138. unsigned int sdhc_clk;
  139. struct clk per_clk;
  140. unsigned int clock;
  141. unsigned int mode;
  142. unsigned int bus_width;
  143. #if !CONFIG_IS_ENABLED(BLK)
  144. struct mmc *mmc;
  145. #endif
  146. struct udevice *dev;
  147. int non_removable;
  148. int broken_cd;
  149. int wp_enable;
  150. int vs18_enable;
  151. u32 flags;
  152. u32 caps;
  153. u32 tuning_step;
  154. u32 tuning_start_tap;
  155. u32 strobe_dll_delay_target;
  156. u32 signal_voltage;
  157. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  158. struct udevice *vqmmc_dev;
  159. struct udevice *vmmc_dev;
  160. #endif
  161. #if CONFIG_IS_ENABLED(DM_GPIO)
  162. struct gpio_desc cd_gpio;
  163. struct gpio_desc wp_gpio;
  164. #endif
  165. };
  166. /* Return the XFERTYP flags for a given command and data packet */
  167. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  168. {
  169. uint xfertyp = 0;
  170. if (data) {
  171. xfertyp |= XFERTYP_DPSEL;
  172. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  173. xfertyp |= XFERTYP_DMAEN;
  174. #endif
  175. if (data->blocks > 1) {
  176. xfertyp |= XFERTYP_MSBSEL;
  177. xfertyp |= XFERTYP_BCEN;
  178. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  179. xfertyp |= XFERTYP_AC12EN;
  180. #endif
  181. }
  182. if (data->flags & MMC_DATA_READ)
  183. xfertyp |= XFERTYP_DTDSEL;
  184. }
  185. if (cmd->resp_type & MMC_RSP_CRC)
  186. xfertyp |= XFERTYP_CCCEN;
  187. if (cmd->resp_type & MMC_RSP_OPCODE)
  188. xfertyp |= XFERTYP_CICEN;
  189. if (cmd->resp_type & MMC_RSP_136)
  190. xfertyp |= XFERTYP_RSPTYP_136;
  191. else if (cmd->resp_type & MMC_RSP_BUSY)
  192. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  193. else if (cmd->resp_type & MMC_RSP_PRESENT)
  194. xfertyp |= XFERTYP_RSPTYP_48;
  195. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  196. xfertyp |= XFERTYP_CMDTYP_ABORT;
  197. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  198. }
  199. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  200. /*
  201. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  202. */
  203. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  204. struct mmc_data *data)
  205. {
  206. struct fsl_esdhc *regs = priv->esdhc_regs;
  207. uint blocks;
  208. char *buffer;
  209. uint databuf;
  210. uint size;
  211. uint irqstat;
  212. ulong start;
  213. if (data->flags & MMC_DATA_READ) {
  214. blocks = data->blocks;
  215. buffer = data->dest;
  216. while (blocks) {
  217. start = get_timer(0);
  218. size = data->blocksize;
  219. irqstat = esdhc_read32(&regs->irqstat);
  220. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  221. if (get_timer(start) > PIO_TIMEOUT) {
  222. printf("\nData Read Failed in PIO Mode.");
  223. return;
  224. }
  225. }
  226. while (size && (!(irqstat & IRQSTAT_TC))) {
  227. udelay(100); /* Wait before last byte transfer complete */
  228. irqstat = esdhc_read32(&regs->irqstat);
  229. databuf = in_le32(&regs->datport);
  230. *((uint *)buffer) = databuf;
  231. buffer += 4;
  232. size -= 4;
  233. }
  234. blocks--;
  235. }
  236. } else {
  237. blocks = data->blocks;
  238. buffer = (char *)data->src;
  239. while (blocks) {
  240. start = get_timer(0);
  241. size = data->blocksize;
  242. irqstat = esdhc_read32(&regs->irqstat);
  243. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  244. if (get_timer(start) > PIO_TIMEOUT) {
  245. printf("\nData Write Failed in PIO Mode.");
  246. return;
  247. }
  248. }
  249. while (size && (!(irqstat & IRQSTAT_TC))) {
  250. udelay(100); /* Wait before last byte transfer complete */
  251. databuf = *((uint *)buffer);
  252. buffer += 4;
  253. size -= 4;
  254. irqstat = esdhc_read32(&regs->irqstat);
  255. out_le32(&regs->datport, databuf);
  256. }
  257. blocks--;
  258. }
  259. }
  260. }
  261. #endif
  262. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  263. struct mmc_data *data)
  264. {
  265. int timeout;
  266. struct fsl_esdhc *regs = priv->esdhc_regs;
  267. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  268. dma_addr_t addr;
  269. #endif
  270. uint wml_value;
  271. wml_value = data->blocksize/4;
  272. if (data->flags & MMC_DATA_READ) {
  273. if (wml_value > WML_RD_WML_MAX)
  274. wml_value = WML_RD_WML_MAX_VAL;
  275. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  276. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  277. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  278. addr = virt_to_phys((void *)(data->dest));
  279. if (upper_32_bits(addr))
  280. printf("Error found for upper 32 bits\n");
  281. else
  282. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  283. #else
  284. esdhc_write32(&regs->dsaddr, (u32)data->dest);
  285. #endif
  286. #endif
  287. } else {
  288. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  289. flush_dcache_range((ulong)data->src,
  290. (ulong)data->src+data->blocks
  291. *data->blocksize);
  292. #endif
  293. if (wml_value > WML_WR_WML_MAX)
  294. wml_value = WML_WR_WML_MAX_VAL;
  295. if (priv->wp_enable) {
  296. if ((esdhc_read32(&regs->prsstat) &
  297. PRSSTAT_WPSPL) == 0) {
  298. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  299. return -ETIMEDOUT;
  300. }
  301. } else {
  302. #if CONFIG_IS_ENABLED(DM_GPIO)
  303. if (dm_gpio_is_valid(&priv->wp_gpio) &&
  304. dm_gpio_get_value(&priv->wp_gpio)) {
  305. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  306. return -ETIMEDOUT;
  307. }
  308. #endif
  309. }
  310. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  311. wml_value << 16);
  312. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  313. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  314. addr = virt_to_phys((void *)(data->src));
  315. if (upper_32_bits(addr))
  316. printf("Error found for upper 32 bits\n");
  317. else
  318. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  319. #else
  320. esdhc_write32(&regs->dsaddr, (u32)data->src);
  321. #endif
  322. #endif
  323. }
  324. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  325. /* Calculate the timeout period for data transactions */
  326. /*
  327. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  328. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  329. * So, Number of SD Clock cycles for 0.25sec should be minimum
  330. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  331. * = (mmc->clock * 1/4) SD Clock cycles
  332. * As 1) >= 2)
  333. * => (2^(timeout+13)) >= mmc->clock * 1/4
  334. * Taking log2 both the sides
  335. * => timeout + 13 >= log2(mmc->clock/4)
  336. * Rounding up to next power of 2
  337. * => timeout + 13 = log2(mmc->clock/4) + 1
  338. * => timeout + 13 = fls(mmc->clock/4)
  339. *
  340. * However, the MMC spec "It is strongly recommended for hosts to
  341. * implement more than 500ms timeout value even if the card
  342. * indicates the 250ms maximum busy length." Even the previous
  343. * value of 300ms is known to be insufficient for some cards.
  344. * So, we use
  345. * => timeout + 13 = fls(mmc->clock/2)
  346. */
  347. timeout = fls(mmc->clock/2);
  348. timeout -= 13;
  349. if (timeout > 14)
  350. timeout = 14;
  351. if (timeout < 0)
  352. timeout = 0;
  353. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  354. if ((timeout == 4) || (timeout == 8) || (timeout == 12))
  355. timeout++;
  356. #endif
  357. #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  358. timeout = 0xE;
  359. #endif
  360. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  361. return 0;
  362. }
  363. static void check_and_invalidate_dcache_range
  364. (struct mmc_cmd *cmd,
  365. struct mmc_data *data) {
  366. unsigned start = 0;
  367. unsigned end = 0;
  368. unsigned size = roundup(ARCH_DMA_MINALIGN,
  369. data->blocks*data->blocksize);
  370. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  371. dma_addr_t addr;
  372. addr = virt_to_phys((void *)(data->dest));
  373. if (upper_32_bits(addr))
  374. printf("Error found for upper 32 bits\n");
  375. else
  376. start = lower_32_bits(addr);
  377. #else
  378. start = (unsigned)data->dest;
  379. #endif
  380. end = start + size;
  381. invalidate_dcache_range(start, end);
  382. }
  383. #ifdef CONFIG_MCF5441x
  384. /*
  385. * Swaps 32-bit words to little-endian byte order.
  386. */
  387. static inline void sd_swap_dma_buff(struct mmc_data *data)
  388. {
  389. int i, size = data->blocksize >> 2;
  390. u32 *buffer = (u32 *)data->dest;
  391. u32 sw;
  392. while (data->blocks--) {
  393. for (i = 0; i < size; i++) {
  394. sw = __sw32(*buffer);
  395. *buffer++ = sw;
  396. }
  397. }
  398. }
  399. #endif
  400. /*
  401. * Sends a command out on the bus. Takes the mmc pointer,
  402. * a command pointer, and an optional data pointer.
  403. */
  404. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  405. struct mmc_cmd *cmd, struct mmc_data *data)
  406. {
  407. int err = 0;
  408. uint xfertyp;
  409. uint irqstat;
  410. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  411. struct fsl_esdhc *regs = priv->esdhc_regs;
  412. unsigned long start;
  413. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  414. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  415. return 0;
  416. #endif
  417. esdhc_write32(&regs->irqstat, -1);
  418. sync();
  419. /* Wait for the bus to be idle */
  420. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  421. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  422. ;
  423. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  424. ;
  425. /* Set up for a data transfer if we have one */
  426. if (data) {
  427. err = esdhc_setup_data(priv, mmc, data);
  428. if(err)
  429. return err;
  430. if (data->flags & MMC_DATA_READ)
  431. check_and_invalidate_dcache_range(cmd, data);
  432. }
  433. /* Figure out the transfer arguments */
  434. xfertyp = esdhc_xfertyp(cmd, data);
  435. /* Mask all irqs */
  436. esdhc_write32(&regs->irqsigen, 0);
  437. /* Send the command */
  438. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  439. #if defined(CONFIG_FSL_USDHC)
  440. esdhc_write32(&regs->mixctrl,
  441. (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
  442. | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
  443. esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
  444. #else
  445. esdhc_write32(&regs->xfertyp, xfertyp);
  446. #endif
  447. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  448. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
  449. flags = IRQSTAT_BRR;
  450. /* Wait for the command to complete */
  451. start = get_timer(0);
  452. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  453. if (get_timer(start) > 1000) {
  454. err = -ETIMEDOUT;
  455. goto out;
  456. }
  457. }
  458. irqstat = esdhc_read32(&regs->irqstat);
  459. if (irqstat & CMD_ERR) {
  460. err = -ECOMM;
  461. goto out;
  462. }
  463. if (irqstat & IRQSTAT_CTOE) {
  464. err = -ETIMEDOUT;
  465. goto out;
  466. }
  467. /* Switch voltage to 1.8V if CMD11 succeeded */
  468. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
  469. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  470. printf("Run CMD11 1.8V switch\n");
  471. /* Sleep for 5 ms - max time for card to switch to 1.8V */
  472. udelay(5000);
  473. }
  474. /* Workaround for ESDHC errata ENGcm03648 */
  475. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  476. int timeout = 50000;
  477. /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
  478. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  479. PRSSTAT_DAT0)) {
  480. udelay(100);
  481. timeout--;
  482. }
  483. if (timeout <= 0) {
  484. printf("Timeout waiting for DAT0 to go high!\n");
  485. err = -ETIMEDOUT;
  486. goto out;
  487. }
  488. }
  489. /* Copy the response to the response buffer */
  490. if (cmd->resp_type & MMC_RSP_136) {
  491. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  492. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  493. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  494. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  495. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  496. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  497. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  498. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  499. cmd->response[3] = (cmdrsp0 << 8);
  500. } else
  501. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  502. /* Wait until all of the blocks are transferred */
  503. if (data) {
  504. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  505. esdhc_pio_read_write(priv, data);
  506. #else
  507. flags = DATA_COMPLETE;
  508. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  509. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
  510. flags = IRQSTAT_BRR;
  511. }
  512. do {
  513. irqstat = esdhc_read32(&regs->irqstat);
  514. if (irqstat & IRQSTAT_DTOE) {
  515. err = -ETIMEDOUT;
  516. goto out;
  517. }
  518. if (irqstat & DATA_ERR) {
  519. err = -ECOMM;
  520. goto out;
  521. }
  522. } while ((irqstat & flags) != flags);
  523. /*
  524. * Need invalidate the dcache here again to avoid any
  525. * cache-fill during the DMA operations such as the
  526. * speculative pre-fetching etc.
  527. */
  528. if (data->flags & MMC_DATA_READ) {
  529. check_and_invalidate_dcache_range(cmd, data);
  530. #ifdef CONFIG_MCF5441x
  531. sd_swap_dma_buff(data);
  532. #endif
  533. }
  534. #endif
  535. }
  536. out:
  537. /* Reset CMD and DATA portions on error */
  538. if (err) {
  539. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  540. SYSCTL_RSTC);
  541. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  542. ;
  543. if (data) {
  544. esdhc_write32(&regs->sysctl,
  545. esdhc_read32(&regs->sysctl) |
  546. SYSCTL_RSTD);
  547. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  548. ;
  549. }
  550. /* If this was CMD11, then notify that power cycle is needed */
  551. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
  552. printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
  553. }
  554. esdhc_write32(&regs->irqstat, -1);
  555. return err;
  556. }
  557. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  558. {
  559. struct fsl_esdhc *regs = priv->esdhc_regs;
  560. int div = 1;
  561. u32 tmp;
  562. int ret;
  563. #ifdef ARCH_MXC
  564. #ifdef CONFIG_MX53
  565. /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
  566. int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
  567. #else
  568. int pre_div = 1;
  569. #endif
  570. #else
  571. int pre_div = 2;
  572. #endif
  573. int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
  574. int sdhc_clk = priv->sdhc_clk;
  575. uint clk;
  576. while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
  577. pre_div *= 2;
  578. while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
  579. div++;
  580. pre_div >>= 1;
  581. div -= 1;
  582. clk = (pre_div << 8) | (div << 4);
  583. #ifdef CONFIG_FSL_USDHC
  584. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  585. #else
  586. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  587. #endif
  588. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  589. ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
  590. if (ret)
  591. pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
  592. #ifdef CONFIG_FSL_USDHC
  593. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
  594. #else
  595. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  596. #endif
  597. priv->clock = clock;
  598. }
  599. #ifdef MMC_SUPPORTS_TUNING
  600. static int esdhc_change_pinstate(struct udevice *dev)
  601. {
  602. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  603. int ret;
  604. switch (priv->mode) {
  605. case UHS_SDR50:
  606. case UHS_DDR50:
  607. ret = pinctrl_select_state(dev, "state_100mhz");
  608. break;
  609. case UHS_SDR104:
  610. case MMC_HS_200:
  611. case MMC_HS_400:
  612. case MMC_HS_400_ES:
  613. ret = pinctrl_select_state(dev, "state_200mhz");
  614. break;
  615. default:
  616. ret = pinctrl_select_state(dev, "default");
  617. break;
  618. }
  619. if (ret)
  620. printf("%s %d error\n", __func__, priv->mode);
  621. return ret;
  622. }
  623. static void esdhc_reset_tuning(struct mmc *mmc)
  624. {
  625. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  626. struct fsl_esdhc *regs = priv->esdhc_regs;
  627. if (priv->flags & ESDHC_FLAG_USDHC) {
  628. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  629. esdhc_clrbits32(&regs->autoc12err,
  630. MIX_CTRL_SMPCLK_SEL |
  631. MIX_CTRL_EXE_TUNE);
  632. }
  633. }
  634. }
  635. static void esdhc_set_strobe_dll(struct mmc *mmc)
  636. {
  637. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  638. struct fsl_esdhc *regs = priv->esdhc_regs;
  639. u32 val;
  640. if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
  641. esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
  642. /*
  643. * enable strobe dll ctrl and adjust the delay target
  644. * for the uSDHC loopback read clock
  645. */
  646. val = ESDHC_STROBE_DLL_CTRL_ENABLE |
  647. (priv->strobe_dll_delay_target <<
  648. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
  649. esdhc_write32(&regs->strobe_dllctrl, val);
  650. /* wait 1us to make sure strobe dll status register stable */
  651. mdelay(1);
  652. val = esdhc_read32(&regs->strobe_dllstat);
  653. if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
  654. pr_warn("HS400 strobe DLL status REF not lock!\n");
  655. if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
  656. pr_warn("HS400 strobe DLL status SLV not lock!\n");
  657. }
  658. }
  659. static int esdhc_set_timing(struct mmc *mmc)
  660. {
  661. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  662. struct fsl_esdhc *regs = priv->esdhc_regs;
  663. u32 mixctrl;
  664. mixctrl = esdhc_read32(&regs->mixctrl);
  665. mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
  666. switch (mmc->selected_mode) {
  667. case MMC_LEGACY:
  668. esdhc_reset_tuning(mmc);
  669. esdhc_write32(&regs->mixctrl, mixctrl);
  670. break;
  671. case MMC_HS_400:
  672. case MMC_HS_400_ES:
  673. mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
  674. esdhc_write32(&regs->mixctrl, mixctrl);
  675. break;
  676. case MMC_HS:
  677. case MMC_HS_52:
  678. case MMC_HS_200:
  679. case SD_HS:
  680. case UHS_SDR12:
  681. case UHS_SDR25:
  682. case UHS_SDR50:
  683. case UHS_SDR104:
  684. esdhc_write32(&regs->mixctrl, mixctrl);
  685. break;
  686. case UHS_DDR50:
  687. case MMC_DDR_52:
  688. mixctrl |= MIX_CTRL_DDREN;
  689. esdhc_write32(&regs->mixctrl, mixctrl);
  690. break;
  691. default:
  692. printf("Not supported %d\n", mmc->selected_mode);
  693. return -EINVAL;
  694. }
  695. priv->mode = mmc->selected_mode;
  696. return esdhc_change_pinstate(mmc->dev);
  697. }
  698. static int esdhc_set_voltage(struct mmc *mmc)
  699. {
  700. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  701. struct fsl_esdhc *regs = priv->esdhc_regs;
  702. int ret;
  703. priv->signal_voltage = mmc->signal_voltage;
  704. switch (mmc->signal_voltage) {
  705. case MMC_SIGNAL_VOLTAGE_330:
  706. if (priv->vs18_enable)
  707. return -ENOTSUPP;
  708. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  709. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  710. ret = regulator_set_value(priv->vqmmc_dev, 3300000);
  711. if (ret) {
  712. printf("Setting to 3.3V error");
  713. return -EIO;
  714. }
  715. /* Wait for 5ms */
  716. mdelay(5);
  717. }
  718. #endif
  719. esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  720. if (!(esdhc_read32(&regs->vendorspec) &
  721. ESDHC_VENDORSPEC_VSELECT))
  722. return 0;
  723. return -EAGAIN;
  724. case MMC_SIGNAL_VOLTAGE_180:
  725. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  726. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  727. ret = regulator_set_value(priv->vqmmc_dev, 1800000);
  728. if (ret) {
  729. printf("Setting to 1.8V error");
  730. return -EIO;
  731. }
  732. }
  733. #endif
  734. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  735. if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
  736. return 0;
  737. return -EAGAIN;
  738. case MMC_SIGNAL_VOLTAGE_120:
  739. return -ENOTSUPP;
  740. default:
  741. return 0;
  742. }
  743. }
  744. static void esdhc_stop_tuning(struct mmc *mmc)
  745. {
  746. struct mmc_cmd cmd;
  747. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  748. cmd.cmdarg = 0;
  749. cmd.resp_type = MMC_RSP_R1b;
  750. dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
  751. }
  752. static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
  753. {
  754. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  755. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  756. struct fsl_esdhc *regs = priv->esdhc_regs;
  757. struct mmc *mmc = &plat->mmc;
  758. u32 irqstaten = esdhc_read32(&regs->irqstaten);
  759. u32 irqsigen = esdhc_read32(&regs->irqsigen);
  760. int i, ret = -ETIMEDOUT;
  761. u32 val, mixctrl;
  762. /* clock tuning is not needed for upto 52MHz */
  763. if (mmc->clock <= 52000000)
  764. return 0;
  765. /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
  766. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  767. val = esdhc_read32(&regs->autoc12err);
  768. mixctrl = esdhc_read32(&regs->mixctrl);
  769. val &= ~MIX_CTRL_SMPCLK_SEL;
  770. mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
  771. val |= MIX_CTRL_EXE_TUNE;
  772. mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
  773. esdhc_write32(&regs->autoc12err, val);
  774. esdhc_write32(&regs->mixctrl, mixctrl);
  775. }
  776. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
  777. mixctrl = esdhc_read32(&regs->mixctrl);
  778. mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
  779. esdhc_write32(&regs->mixctrl, mixctrl);
  780. esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
  781. esdhc_write32(&regs->irqsigen, IRQSTATEN_BRR);
  782. /*
  783. * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
  784. * of loops reaches 40 times.
  785. */
  786. for (i = 0; i < MAX_TUNING_LOOP; i++) {
  787. u32 ctrl;
  788. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  789. if (mmc->bus_width == 8)
  790. esdhc_write32(&regs->blkattr, 0x7080);
  791. else if (mmc->bus_width == 4)
  792. esdhc_write32(&regs->blkattr, 0x7040);
  793. } else {
  794. esdhc_write32(&regs->blkattr, 0x7040);
  795. }
  796. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
  797. val = esdhc_read32(&regs->mixctrl);
  798. val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
  799. esdhc_write32(&regs->mixctrl, val);
  800. /* We are using STD tuning, no need to check return value */
  801. mmc_send_tuning(mmc, opcode, NULL);
  802. ctrl = esdhc_read32(&regs->autoc12err);
  803. if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
  804. (ctrl & MIX_CTRL_SMPCLK_SEL)) {
  805. ret = 0;
  806. break;
  807. }
  808. }
  809. esdhc_write32(&regs->irqstaten, irqstaten);
  810. esdhc_write32(&regs->irqsigen, irqsigen);
  811. esdhc_stop_tuning(mmc);
  812. return ret;
  813. }
  814. #endif
  815. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  816. {
  817. struct fsl_esdhc *regs = priv->esdhc_regs;
  818. int ret __maybe_unused;
  819. u32 clock;
  820. #ifdef MMC_SUPPORTS_TUNING
  821. /*
  822. * call esdhc_set_timing() before update the clock rate,
  823. * This is because current we support DDR and SDR mode,
  824. * Once the DDR_EN bit is set, the card clock will be
  825. * divide by 2 automatically. So need to do this before
  826. * setting clock rate.
  827. */
  828. if (priv->mode != mmc->selected_mode) {
  829. ret = esdhc_set_timing(mmc);
  830. if (ret) {
  831. printf("esdhc_set_timing error %d\n", ret);
  832. return ret;
  833. }
  834. }
  835. #endif
  836. /* Set the clock speed */
  837. clock = mmc->clock;
  838. if (clock < mmc->cfg->f_min)
  839. clock = mmc->cfg->f_min;
  840. if (priv->clock != clock)
  841. set_sysctl(priv, mmc, clock);
  842. #ifdef MMC_SUPPORTS_TUNING
  843. if (mmc->clk_disable) {
  844. #ifdef CONFIG_FSL_USDHC
  845. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  846. #else
  847. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  848. #endif
  849. } else {
  850. #ifdef CONFIG_FSL_USDHC
  851. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  852. VENDORSPEC_CKEN);
  853. #else
  854. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  855. #endif
  856. }
  857. /*
  858. * For HS400/HS400ES mode, make sure set the strobe dll in the
  859. * target clock rate. So call esdhc_set_strobe_dll() after the
  860. * clock updated.
  861. */
  862. if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
  863. esdhc_set_strobe_dll(mmc);
  864. if (priv->signal_voltage != mmc->signal_voltage) {
  865. ret = esdhc_set_voltage(mmc);
  866. if (ret) {
  867. if (ret != -ENOTSUPP)
  868. printf("esdhc_set_voltage error %d\n", ret);
  869. return ret;
  870. }
  871. }
  872. #endif
  873. /* Set the bus width */
  874. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  875. if (mmc->bus_width == 4)
  876. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  877. else if (mmc->bus_width == 8)
  878. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  879. return 0;
  880. }
  881. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  882. {
  883. struct fsl_esdhc *regs = priv->esdhc_regs;
  884. ulong start;
  885. /* Reset the entire host controller */
  886. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  887. /* Wait until the controller is available */
  888. start = get_timer(0);
  889. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  890. if (get_timer(start) > 1000)
  891. return -ETIMEDOUT;
  892. }
  893. #if defined(CONFIG_FSL_USDHC)
  894. /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
  895. esdhc_write32(&regs->mmcboot, 0x0);
  896. /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
  897. esdhc_write32(&regs->mixctrl, 0x0);
  898. esdhc_write32(&regs->clktunectrlstatus, 0x0);
  899. /* Put VEND_SPEC to default value */
  900. if (priv->vs18_enable)
  901. esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
  902. ESDHC_VENDORSPEC_VSELECT));
  903. else
  904. esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
  905. /* Disable DLL_CTRL delay line */
  906. esdhc_write32(&regs->dllctrl, 0x0);
  907. #endif
  908. #ifndef ARCH_MXC
  909. /* Enable cache snooping */
  910. esdhc_write32(&regs->scr, 0x00000040);
  911. #endif
  912. #ifndef CONFIG_FSL_USDHC
  913. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  914. #else
  915. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
  916. #endif
  917. /* Set the initial clock speed */
  918. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  919. /* Disable the BRR and BWR bits in IRQSTAT */
  920. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  921. #ifdef CONFIG_MCF5441x
  922. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  923. #else
  924. /* Put the PROCTL reg back to the default */
  925. esdhc_write32(&regs->proctl, PROCTL_INIT);
  926. #endif
  927. /* Set timout to the maximum value */
  928. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  929. return 0;
  930. }
  931. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  932. {
  933. struct fsl_esdhc *regs = priv->esdhc_regs;
  934. int timeout = 1000;
  935. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  936. if (CONFIG_ESDHC_DETECT_QUIRK)
  937. return 1;
  938. #endif
  939. #if CONFIG_IS_ENABLED(DM_MMC)
  940. if (priv->non_removable)
  941. return 1;
  942. if (priv->broken_cd)
  943. return 1;
  944. #if CONFIG_IS_ENABLED(DM_GPIO)
  945. if (dm_gpio_is_valid(&priv->cd_gpio))
  946. return dm_gpio_get_value(&priv->cd_gpio);
  947. #endif
  948. #endif
  949. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
  950. udelay(1000);
  951. return timeout > 0;
  952. }
  953. static int esdhc_reset(struct fsl_esdhc *regs)
  954. {
  955. ulong start;
  956. /* reset the controller */
  957. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  958. /* hardware clears the bit when it is done */
  959. start = get_timer(0);
  960. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  961. if (get_timer(start) > 100) {
  962. printf("MMC/SD: Reset never completed.\n");
  963. return -ETIMEDOUT;
  964. }
  965. }
  966. return 0;
  967. }
  968. #if !CONFIG_IS_ENABLED(DM_MMC)
  969. static int esdhc_getcd(struct mmc *mmc)
  970. {
  971. struct fsl_esdhc_priv *priv = mmc->priv;
  972. return esdhc_getcd_common(priv);
  973. }
  974. static int esdhc_init(struct mmc *mmc)
  975. {
  976. struct fsl_esdhc_priv *priv = mmc->priv;
  977. return esdhc_init_common(priv, mmc);
  978. }
  979. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  980. struct mmc_data *data)
  981. {
  982. struct fsl_esdhc_priv *priv = mmc->priv;
  983. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  984. }
  985. static int esdhc_set_ios(struct mmc *mmc)
  986. {
  987. struct fsl_esdhc_priv *priv = mmc->priv;
  988. return esdhc_set_ios_common(priv, mmc);
  989. }
  990. static const struct mmc_ops esdhc_ops = {
  991. .getcd = esdhc_getcd,
  992. .init = esdhc_init,
  993. .send_cmd = esdhc_send_cmd,
  994. .set_ios = esdhc_set_ios,
  995. };
  996. #endif
  997. static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
  998. struct fsl_esdhc_plat *plat)
  999. {
  1000. struct mmc_config *cfg;
  1001. struct fsl_esdhc *regs;
  1002. u32 caps, voltage_caps;
  1003. int ret;
  1004. if (!priv)
  1005. return -EINVAL;
  1006. regs = priv->esdhc_regs;
  1007. /* First reset the eSDHC controller */
  1008. ret = esdhc_reset(regs);
  1009. if (ret)
  1010. return ret;
  1011. #ifdef CONFIG_MCF5441x
  1012. /* ColdFire, using SDHC_DATA[3] for card detection */
  1013. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  1014. #endif
  1015. #ifndef CONFIG_FSL_USDHC
  1016. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
  1017. | SYSCTL_IPGEN | SYSCTL_CKEN);
  1018. /* Clearing tuning bits in case ROM has set it already */
  1019. esdhc_write32(&regs->mixctrl, 0);
  1020. esdhc_write32(&regs->autoc12err, 0);
  1021. esdhc_write32(&regs->clktunectrlstatus, 0);
  1022. #else
  1023. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  1024. VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
  1025. #endif
  1026. if (priv->vs18_enable)
  1027. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  1028. esdhc_write32(&regs->irqstaten, SDHCI_IRQ_EN_BITS);
  1029. cfg = &plat->cfg;
  1030. #ifndef CONFIG_DM_MMC
  1031. memset(cfg, '\0', sizeof(*cfg));
  1032. #endif
  1033. voltage_caps = 0;
  1034. caps = esdhc_read32(&regs->hostcapblt);
  1035. #ifdef CONFIG_MCF5441x
  1036. /*
  1037. * MCF5441x RM declares in more points that sdhc clock speed must
  1038. * never exceed 25 Mhz. From this, the HS bit needs to be disabled
  1039. * from host capabilities.
  1040. */
  1041. caps &= ~ESDHC_HOSTCAPBLT_HSS;
  1042. #endif
  1043. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
  1044. caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
  1045. ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
  1046. #endif
  1047. /* T4240 host controller capabilities register should have VS33 bit */
  1048. #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  1049. caps = caps | ESDHC_HOSTCAPBLT_VS33;
  1050. #endif
  1051. if (caps & ESDHC_HOSTCAPBLT_VS18)
  1052. voltage_caps |= MMC_VDD_165_195;
  1053. if (caps & ESDHC_HOSTCAPBLT_VS30)
  1054. voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
  1055. if (caps & ESDHC_HOSTCAPBLT_VS33)
  1056. voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
  1057. cfg->name = "FSL_SDHC";
  1058. #if !CONFIG_IS_ENABLED(DM_MMC)
  1059. cfg->ops = &esdhc_ops;
  1060. #endif
  1061. #ifdef CONFIG_SYS_SD_VOLTAGE
  1062. cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
  1063. #else
  1064. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  1065. #endif
  1066. if ((cfg->voltages & voltage_caps) == 0) {
  1067. printf("voltage not supported by controller\n");
  1068. return -1;
  1069. }
  1070. if (priv->bus_width == 8)
  1071. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1072. else if (priv->bus_width == 4)
  1073. cfg->host_caps = MMC_MODE_4BIT;
  1074. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1075. #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
  1076. cfg->host_caps |= MMC_MODE_DDR_52MHz;
  1077. #endif
  1078. if (priv->bus_width > 0) {
  1079. if (priv->bus_width < 8)
  1080. cfg->host_caps &= ~MMC_MODE_8BIT;
  1081. if (priv->bus_width < 4)
  1082. cfg->host_caps &= ~MMC_MODE_4BIT;
  1083. }
  1084. if (caps & ESDHC_HOSTCAPBLT_HSS)
  1085. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1086. #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
  1087. if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
  1088. cfg->host_caps &= ~MMC_MODE_8BIT;
  1089. #endif
  1090. cfg->host_caps |= priv->caps;
  1091. cfg->f_min = 400000;
  1092. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  1093. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1094. esdhc_write32(&regs->dllctrl, 0);
  1095. if (priv->flags & ESDHC_FLAG_USDHC) {
  1096. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  1097. u32 val = esdhc_read32(&regs->tuning_ctrl);
  1098. val |= ESDHC_STD_TUNING_EN;
  1099. val &= ~ESDHC_TUNING_START_TAP_MASK;
  1100. val |= priv->tuning_start_tap;
  1101. val &= ~ESDHC_TUNING_STEP_MASK;
  1102. val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
  1103. /* Disable the CMD CRC check for tuning, if not, need to
  1104. * add some delay after every tuning command, because
  1105. * hardware standard tuning logic will directly go to next
  1106. * step once it detect the CMD CRC error, will not wait for
  1107. * the card side to finally send out the tuning data, trigger
  1108. * the buffer read ready interrupt immediately. If usdhc send
  1109. * the next tuning command some eMMC card will stuck, can't
  1110. * response, block the tuning procedure or the first command
  1111. * after the whole tuning procedure always can't get any response.
  1112. */
  1113. val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
  1114. esdhc_write32(&regs->tuning_ctrl, val);
  1115. }
  1116. }
  1117. return 0;
  1118. }
  1119. #if !CONFIG_IS_ENABLED(DM_MMC)
  1120. static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
  1121. struct fsl_esdhc_priv *priv)
  1122. {
  1123. if (!cfg || !priv)
  1124. return -EINVAL;
  1125. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  1126. priv->bus_width = cfg->max_bus_width;
  1127. priv->sdhc_clk = cfg->sdhc_clk;
  1128. priv->wp_enable = cfg->wp_enable;
  1129. priv->vs18_enable = cfg->vs18_enable;
  1130. return 0;
  1131. };
  1132. int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
  1133. {
  1134. struct fsl_esdhc_plat *plat;
  1135. struct fsl_esdhc_priv *priv;
  1136. struct mmc *mmc;
  1137. int ret;
  1138. if (!cfg)
  1139. return -EINVAL;
  1140. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  1141. if (!priv)
  1142. return -ENOMEM;
  1143. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  1144. if (!plat) {
  1145. free(priv);
  1146. return -ENOMEM;
  1147. }
  1148. ret = fsl_esdhc_cfg_to_priv(cfg, priv);
  1149. if (ret) {
  1150. debug("%s xlate failure\n", __func__);
  1151. free(plat);
  1152. free(priv);
  1153. return ret;
  1154. }
  1155. ret = fsl_esdhc_init(priv, plat);
  1156. if (ret) {
  1157. debug("%s init failure\n", __func__);
  1158. free(plat);
  1159. free(priv);
  1160. return ret;
  1161. }
  1162. mmc = mmc_create(&plat->cfg, priv);
  1163. if (!mmc)
  1164. return -EIO;
  1165. priv->mmc = mmc;
  1166. return 0;
  1167. }
  1168. int fsl_esdhc_mmc_init(struct bd_info *bis)
  1169. {
  1170. struct fsl_esdhc_cfg *cfg;
  1171. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  1172. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  1173. cfg->sdhc_clk = gd->arch.sdhc_clk;
  1174. return fsl_esdhc_initialize(bis, cfg);
  1175. }
  1176. #endif
  1177. #ifdef CONFIG_OF_LIBFDT
  1178. __weak int esdhc_status_fixup(void *blob, const char *compat)
  1179. {
  1180. #ifdef CONFIG_FSL_ESDHC_PIN_MUX
  1181. if (!hwconfig("esdhc")) {
  1182. do_fixup_by_compat(blob, compat, "status", "disabled",
  1183. sizeof("disabled"), 1);
  1184. return 1;
  1185. }
  1186. #endif
  1187. return 0;
  1188. }
  1189. void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
  1190. {
  1191. const char *compat = "fsl,esdhc";
  1192. if (esdhc_status_fixup(blob, compat))
  1193. return;
  1194. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  1195. gd->arch.sdhc_clk, 1);
  1196. }
  1197. #endif
  1198. #if CONFIG_IS_ENABLED(DM_MMC)
  1199. #include <asm/arch/clock.h>
  1200. __weak void init_clk_usdhc(u32 index)
  1201. {
  1202. }
  1203. static int fsl_esdhc_ofdata_to_platdata(struct udevice *dev)
  1204. {
  1205. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  1206. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1207. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1208. struct udevice *vqmmc_dev;
  1209. int ret;
  1210. #endif
  1211. const void *fdt = gd->fdt_blob;
  1212. int node = dev_of_offset(dev);
  1213. fdt_addr_t addr;
  1214. unsigned int val;
  1215. addr = dev_read_addr(dev);
  1216. if (addr == FDT_ADDR_T_NONE)
  1217. return -EINVAL;
  1218. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  1219. priv->dev = dev;
  1220. priv->mode = -1;
  1221. val = dev_read_u32_default(dev, "bus-width", -1);
  1222. if (val == 8)
  1223. priv->bus_width = 8;
  1224. else if (val == 4)
  1225. priv->bus_width = 4;
  1226. else
  1227. priv->bus_width = 1;
  1228. val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
  1229. priv->tuning_step = val;
  1230. val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
  1231. ESDHC_TUNING_START_TAP_DEFAULT);
  1232. priv->tuning_start_tap = val;
  1233. val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
  1234. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
  1235. priv->strobe_dll_delay_target = val;
  1236. if (dev_read_bool(dev, "broken-cd"))
  1237. priv->broken_cd = 1;
  1238. if (dev_read_bool(dev, "non-removable")) {
  1239. priv->non_removable = 1;
  1240. } else {
  1241. priv->non_removable = 0;
  1242. #if CONFIG_IS_ENABLED(DM_GPIO)
  1243. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  1244. GPIOD_IS_IN);
  1245. #endif
  1246. }
  1247. if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
  1248. priv->wp_enable = 1;
  1249. } else {
  1250. priv->wp_enable = 0;
  1251. #if CONFIG_IS_ENABLED(DM_GPIO)
  1252. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
  1253. GPIOD_IS_IN);
  1254. #endif
  1255. }
  1256. priv->vs18_enable = 0;
  1257. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1258. /*
  1259. * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
  1260. * otherwise, emmc will work abnormally.
  1261. */
  1262. ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
  1263. if (ret) {
  1264. dev_dbg(dev, "no vqmmc-supply\n");
  1265. } else {
  1266. priv->vqmmc_dev = vqmmc_dev;
  1267. ret = regulator_set_enable(vqmmc_dev, true);
  1268. if (ret) {
  1269. dev_err(dev, "fail to enable vqmmc-supply\n");
  1270. return ret;
  1271. }
  1272. if (regulator_get_value(vqmmc_dev) == 1800000)
  1273. priv->vs18_enable = 1;
  1274. }
  1275. #endif
  1276. #endif
  1277. return 0;
  1278. }
  1279. static int fsl_esdhc_probe(struct udevice *dev)
  1280. {
  1281. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1282. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1283. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1284. struct esdhc_soc_data *data =
  1285. (struct esdhc_soc_data *)dev_get_driver_data(dev);
  1286. struct mmc *mmc;
  1287. #if !CONFIG_IS_ENABLED(BLK)
  1288. struct blk_desc *bdesc;
  1289. #endif
  1290. int ret;
  1291. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  1292. struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
  1293. unsigned int val;
  1294. priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  1295. val = plat->dtplat.bus_width;
  1296. if (val == 8)
  1297. priv->bus_width = 8;
  1298. else if (val == 4)
  1299. priv->bus_width = 4;
  1300. else
  1301. priv->bus_width = 1;
  1302. if (dtplat->non_removable)
  1303. priv->non_removable = 1;
  1304. else
  1305. priv->non_removable = 0;
  1306. if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
  1307. struct udevice *gpiodev;
  1308. ret = device_get_by_driver_info_idx(dtplat->cd_gpios->idx,
  1309. &gpiodev);
  1310. if (ret)
  1311. return ret;
  1312. ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
  1313. dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
  1314. dtplat->cd_gpios->arg[1], &priv->cd_gpio);
  1315. if (ret)
  1316. return ret;
  1317. }
  1318. #endif
  1319. if (data)
  1320. priv->flags = data->flags;
  1321. /*
  1322. * TODO:
  1323. * Because lack of clk driver, if SDHC clk is not enabled,
  1324. * need to enable it first before this driver is invoked.
  1325. *
  1326. * we use MXC_ESDHC_CLK to get clk freq.
  1327. * If one would like to make this function work,
  1328. * the aliases should be provided in dts as this:
  1329. *
  1330. * aliases {
  1331. * mmc0 = &usdhc1;
  1332. * mmc1 = &usdhc2;
  1333. * mmc2 = &usdhc3;
  1334. * mmc3 = &usdhc4;
  1335. * };
  1336. * Then if your board only supports mmc2 and mmc3, but we can
  1337. * correctly get the seq as 2 and 3, then let mxc_get_clock
  1338. * work as expected.
  1339. */
  1340. init_clk_usdhc(dev->seq);
  1341. #if CONFIG_IS_ENABLED(CLK)
  1342. /* Assigned clock already set clock */
  1343. ret = clk_get_by_name(dev, "per", &priv->per_clk);
  1344. if (ret) {
  1345. printf("Failed to get per_clk\n");
  1346. return ret;
  1347. }
  1348. ret = clk_enable(&priv->per_clk);
  1349. if (ret) {
  1350. printf("Failed to enable per_clk\n");
  1351. return ret;
  1352. }
  1353. priv->sdhc_clk = clk_get_rate(&priv->per_clk);
  1354. #else
  1355. priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
  1356. if (priv->sdhc_clk <= 0) {
  1357. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  1358. return -EINVAL;
  1359. }
  1360. #endif
  1361. ret = fsl_esdhc_init(priv, plat);
  1362. if (ret) {
  1363. dev_err(dev, "fsl_esdhc_init failure\n");
  1364. return ret;
  1365. }
  1366. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  1367. ret = mmc_of_parse(dev, &plat->cfg);
  1368. if (ret)
  1369. return ret;
  1370. #endif
  1371. mmc = &plat->mmc;
  1372. mmc->cfg = &plat->cfg;
  1373. mmc->dev = dev;
  1374. #if !CONFIG_IS_ENABLED(BLK)
  1375. mmc->priv = priv;
  1376. /* Setup dsr related values */
  1377. mmc->dsr_imp = 0;
  1378. mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
  1379. /* Setup the universal parts of the block interface just once */
  1380. bdesc = mmc_get_blk_desc(mmc);
  1381. bdesc->if_type = IF_TYPE_MMC;
  1382. bdesc->removable = 1;
  1383. bdesc->devnum = mmc_get_next_devnum();
  1384. bdesc->block_read = mmc_bread;
  1385. bdesc->block_write = mmc_bwrite;
  1386. bdesc->block_erase = mmc_berase;
  1387. /* setup initial part type */
  1388. bdesc->part_type = mmc->cfg->part_type;
  1389. mmc_list_add(mmc);
  1390. #endif
  1391. upriv->mmc = mmc;
  1392. return esdhc_init_common(priv, mmc);
  1393. }
  1394. #if CONFIG_IS_ENABLED(DM_MMC)
  1395. static int fsl_esdhc_get_cd(struct udevice *dev)
  1396. {
  1397. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1398. return esdhc_getcd_common(priv);
  1399. }
  1400. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  1401. struct mmc_data *data)
  1402. {
  1403. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1404. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1405. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  1406. }
  1407. static int fsl_esdhc_set_ios(struct udevice *dev)
  1408. {
  1409. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1410. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1411. return esdhc_set_ios_common(priv, &plat->mmc);
  1412. }
  1413. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1414. static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
  1415. {
  1416. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1417. struct fsl_esdhc *regs = priv->esdhc_regs;
  1418. u32 m;
  1419. m = esdhc_read32(&regs->mixctrl);
  1420. m |= MIX_CTRL_HS400_ES;
  1421. esdhc_write32(&regs->mixctrl, m);
  1422. return 0;
  1423. }
  1424. #endif
  1425. static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
  1426. int timeout_us)
  1427. {
  1428. int ret;
  1429. u32 tmp;
  1430. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1431. struct fsl_esdhc *regs = priv->esdhc_regs;
  1432. ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp,
  1433. !!(tmp & PRSSTAT_DAT0) == !!state,
  1434. timeout_us);
  1435. return ret;
  1436. }
  1437. static const struct dm_mmc_ops fsl_esdhc_ops = {
  1438. .get_cd = fsl_esdhc_get_cd,
  1439. .send_cmd = fsl_esdhc_send_cmd,
  1440. .set_ios = fsl_esdhc_set_ios,
  1441. #ifdef MMC_SUPPORTS_TUNING
  1442. .execute_tuning = fsl_esdhc_execute_tuning,
  1443. #endif
  1444. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1445. .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
  1446. #endif
  1447. .wait_dat0 = fsl_esdhc_wait_dat0,
  1448. };
  1449. #endif
  1450. static struct esdhc_soc_data usdhc_imx7d_data = {
  1451. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  1452. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  1453. | ESDHC_FLAG_HS400,
  1454. };
  1455. static struct esdhc_soc_data usdhc_imx8qm_data = {
  1456. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
  1457. ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
  1458. ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
  1459. };
  1460. static const struct udevice_id fsl_esdhc_ids[] = {
  1461. { .compatible = "fsl,imx53-esdhc", },
  1462. { .compatible = "fsl,imx6ul-usdhc", },
  1463. { .compatible = "fsl,imx6sx-usdhc", },
  1464. { .compatible = "fsl,imx6sl-usdhc", },
  1465. { .compatible = "fsl,imx6q-usdhc", },
  1466. { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
  1467. { .compatible = "fsl,imx7ulp-usdhc", },
  1468. { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1469. { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1470. { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1471. { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1472. { .compatible = "fsl,imxrt-usdhc", },
  1473. { .compatible = "fsl,esdhc", },
  1474. { /* sentinel */ }
  1475. };
  1476. #if CONFIG_IS_ENABLED(BLK)
  1477. static int fsl_esdhc_bind(struct udevice *dev)
  1478. {
  1479. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1480. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  1481. }
  1482. #endif
  1483. U_BOOT_DRIVER(fsl_esdhc) = {
  1484. .name = "fsl_esdhc",
  1485. .id = UCLASS_MMC,
  1486. .of_match = fsl_esdhc_ids,
  1487. .ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata,
  1488. .ops = &fsl_esdhc_ops,
  1489. #if CONFIG_IS_ENABLED(BLK)
  1490. .bind = fsl_esdhc_bind,
  1491. #endif
  1492. .probe = fsl_esdhc_probe,
  1493. .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
  1494. .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
  1495. };
  1496. U_BOOT_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
  1497. #endif