fsl_esdhc.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019-2020 NXP
  5. * Andy Fleming
  6. *
  7. * Based vaguely on the pxa mmc code:
  8. * (C) Copyright 2003
  9. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10. */
  11. #include <config.h>
  12. #include <common.h>
  13. #include <command.h>
  14. #include <cpu_func.h>
  15. #include <errno.h>
  16. #include <hwconfig.h>
  17. #include <mmc.h>
  18. #include <part.h>
  19. #include <malloc.h>
  20. #include <fsl_esdhc.h>
  21. #include <fdt_support.h>
  22. #include <asm/cache.h>
  23. #include <asm/io.h>
  24. #include <dm.h>
  25. #include <dm/device_compat.h>
  26. #include <linux/bitops.h>
  27. #include <linux/delay.h>
  28. #include <linux/dma-mapping.h>
  29. #include <sdhci.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. struct fsl_esdhc {
  32. uint dsaddr; /* SDMA system address register */
  33. uint blkattr; /* Block attributes register */
  34. uint cmdarg; /* Command argument register */
  35. uint xfertyp; /* Transfer type register */
  36. uint cmdrsp0; /* Command response 0 register */
  37. uint cmdrsp1; /* Command response 1 register */
  38. uint cmdrsp2; /* Command response 2 register */
  39. uint cmdrsp3; /* Command response 3 register */
  40. uint datport; /* Buffer data port register */
  41. uint prsstat; /* Present state register */
  42. uint proctl; /* Protocol control register */
  43. uint sysctl; /* System Control Register */
  44. uint irqstat; /* Interrupt status register */
  45. uint irqstaten; /* Interrupt status enable register */
  46. uint irqsigen; /* Interrupt signal enable register */
  47. uint autoc12err; /* Auto CMD error status register */
  48. uint hostcapblt; /* Host controller capabilities register */
  49. uint wml; /* Watermark level register */
  50. char reserved1[8]; /* reserved */
  51. uint fevt; /* Force event register */
  52. uint admaes; /* ADMA error status register */
  53. uint adsaddrl; /* ADMA system address low register */
  54. uint adsaddrh; /* ADMA system address high register */
  55. char reserved2[156];
  56. uint hostver; /* Host controller version register */
  57. char reserved3[4]; /* reserved */
  58. uint dmaerraddr; /* DMA error address register */
  59. char reserved4[4]; /* reserved */
  60. uint dmaerrattr; /* DMA error attribute register */
  61. char reserved5[4]; /* reserved */
  62. uint hostcapblt2; /* Host controller capabilities register 2 */
  63. char reserved6[8]; /* reserved */
  64. uint tbctl; /* Tuning block control register */
  65. char reserved7[32]; /* reserved */
  66. uint sdclkctl; /* SD clock control register */
  67. uint sdtimingctl; /* SD timing control register */
  68. char reserved8[20]; /* reserved */
  69. uint dllcfg0; /* DLL config 0 register */
  70. char reserved9[12]; /* reserved */
  71. uint dllstat0; /* DLL status 0 register */
  72. char reserved10[664];/* reserved */
  73. uint esdhcctl; /* eSDHC control register */
  74. };
  75. struct fsl_esdhc_plat {
  76. struct mmc_config cfg;
  77. struct mmc mmc;
  78. };
  79. /**
  80. * struct fsl_esdhc_priv
  81. *
  82. * @esdhc_regs: registers of the sdhc controller
  83. * @sdhc_clk: Current clk of the sdhc controller
  84. * @bus_width: bus width, 1bit, 4bit or 8bit
  85. * @cfg: mmc config
  86. * @mmc: mmc
  87. * Following is used when Driver Model is enabled for MMC
  88. * @dev: pointer for the device
  89. * @cd_gpio: gpio for card detection
  90. * @wp_gpio: gpio for write protection
  91. */
  92. struct fsl_esdhc_priv {
  93. struct fsl_esdhc *esdhc_regs;
  94. unsigned int sdhc_clk;
  95. bool is_sdhc_per_clk;
  96. unsigned int clock;
  97. #if !CONFIG_IS_ENABLED(DM_MMC)
  98. struct mmc *mmc;
  99. #endif
  100. struct udevice *dev;
  101. struct sdhci_adma_desc *adma_desc_table;
  102. dma_addr_t dma_addr;
  103. };
  104. /* Return the XFERTYP flags for a given command and data packet */
  105. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  106. {
  107. uint xfertyp = 0;
  108. if (data) {
  109. xfertyp |= XFERTYP_DPSEL;
  110. if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
  111. cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
  112. cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
  113. xfertyp |= XFERTYP_DMAEN;
  114. if (data->blocks > 1) {
  115. xfertyp |= XFERTYP_MSBSEL;
  116. xfertyp |= XFERTYP_BCEN;
  117. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
  118. xfertyp |= XFERTYP_AC12EN;
  119. }
  120. if (data->flags & MMC_DATA_READ)
  121. xfertyp |= XFERTYP_DTDSEL;
  122. }
  123. if (cmd->resp_type & MMC_RSP_CRC)
  124. xfertyp |= XFERTYP_CCCEN;
  125. if (cmd->resp_type & MMC_RSP_OPCODE)
  126. xfertyp |= XFERTYP_CICEN;
  127. if (cmd->resp_type & MMC_RSP_136)
  128. xfertyp |= XFERTYP_RSPTYP_136;
  129. else if (cmd->resp_type & MMC_RSP_BUSY)
  130. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  131. else if (cmd->resp_type & MMC_RSP_PRESENT)
  132. xfertyp |= XFERTYP_RSPTYP_48;
  133. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  134. xfertyp |= XFERTYP_CMDTYP_ABORT;
  135. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  136. }
  137. /*
  138. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  139. */
  140. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  141. struct mmc_data *data)
  142. {
  143. struct fsl_esdhc *regs = priv->esdhc_regs;
  144. uint blocks;
  145. char *buffer;
  146. uint databuf;
  147. uint size;
  148. uint irqstat;
  149. ulong start;
  150. if (data->flags & MMC_DATA_READ) {
  151. blocks = data->blocks;
  152. buffer = data->dest;
  153. while (blocks) {
  154. start = get_timer(0);
  155. size = data->blocksize;
  156. irqstat = esdhc_read32(&regs->irqstat);
  157. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  158. if (get_timer(start) > PIO_TIMEOUT) {
  159. printf("\nData Read Failed in PIO Mode.");
  160. return;
  161. }
  162. }
  163. while (size && (!(irqstat & IRQSTAT_TC))) {
  164. udelay(100); /* Wait before last byte transfer complete */
  165. irqstat = esdhc_read32(&regs->irqstat);
  166. databuf = in_le32(&regs->datport);
  167. *((uint *)buffer) = databuf;
  168. buffer += 4;
  169. size -= 4;
  170. }
  171. blocks--;
  172. }
  173. } else {
  174. blocks = data->blocks;
  175. buffer = (char *)data->src;
  176. while (blocks) {
  177. start = get_timer(0);
  178. size = data->blocksize;
  179. irqstat = esdhc_read32(&regs->irqstat);
  180. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  181. if (get_timer(start) > PIO_TIMEOUT) {
  182. printf("\nData Write Failed in PIO Mode.");
  183. return;
  184. }
  185. }
  186. while (size && (!(irqstat & IRQSTAT_TC))) {
  187. udelay(100); /* Wait before last byte transfer complete */
  188. databuf = *((uint *)buffer);
  189. buffer += 4;
  190. size -= 4;
  191. irqstat = esdhc_read32(&regs->irqstat);
  192. out_le32(&regs->datport, databuf);
  193. }
  194. blocks--;
  195. }
  196. }
  197. }
  198. static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
  199. struct mmc_data *data)
  200. {
  201. struct fsl_esdhc *regs = priv->esdhc_regs;
  202. uint wml_value = data->blocksize / 4;
  203. if (data->flags & MMC_DATA_READ) {
  204. if (wml_value > WML_RD_WML_MAX)
  205. wml_value = WML_RD_WML_MAX_VAL;
  206. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  207. } else {
  208. if (wml_value > WML_WR_WML_MAX)
  209. wml_value = WML_WR_WML_MAX_VAL;
  210. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  211. wml_value << 16);
  212. }
  213. }
  214. static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
  215. {
  216. uint trans_bytes = data->blocksize * data->blocks;
  217. struct fsl_esdhc *regs = priv->esdhc_regs;
  218. phys_addr_t adma_addr;
  219. void *buf;
  220. if (data->flags & MMC_DATA_WRITE)
  221. buf = (void *)data->src;
  222. else
  223. buf = data->dest;
  224. priv->dma_addr = dma_map_single(buf, trans_bytes,
  225. mmc_get_dma_dir(data));
  226. if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2) &&
  227. priv->adma_desc_table) {
  228. debug("Using ADMA2\n");
  229. /* prefer ADMA2 if it is available */
  230. sdhci_prepare_adma_table(priv->adma_desc_table, data,
  231. priv->dma_addr);
  232. adma_addr = virt_to_phys(priv->adma_desc_table);
  233. esdhc_write32(&regs->adsaddrl, lower_32_bits(adma_addr));
  234. if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT))
  235. esdhc_write32(&regs->adsaddrh, upper_32_bits(adma_addr));
  236. esdhc_clrsetbits32(&regs->proctl, PROCTL_DMAS_MASK,
  237. PROCTL_DMAS_ADMA2);
  238. } else {
  239. debug("Using SDMA\n");
  240. if (upper_32_bits(priv->dma_addr))
  241. printf("Cannot use 64 bit addresses with SDMA\n");
  242. esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
  243. esdhc_clrsetbits32(&regs->proctl, PROCTL_DMAS_MASK,
  244. PROCTL_DMAS_SDMA);
  245. }
  246. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  247. }
  248. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  249. struct mmc_data *data)
  250. {
  251. int timeout;
  252. bool is_write = data->flags & MMC_DATA_WRITE;
  253. struct fsl_esdhc *regs = priv->esdhc_regs;
  254. if (is_write && !(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
  255. printf("Can not write to locked SD card.\n");
  256. return -EINVAL;
  257. }
  258. if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
  259. esdhc_setup_watermark_level(priv, data);
  260. else
  261. esdhc_setup_dma(priv, data);
  262. /* Calculate the timeout period for data transactions */
  263. /*
  264. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  265. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  266. * So, Number of SD Clock cycles for 0.25sec should be minimum
  267. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  268. * = (mmc->clock * 1/4) SD Clock cycles
  269. * As 1) >= 2)
  270. * => (2^(timeout+13)) >= mmc->clock * 1/4
  271. * Taking log2 both the sides
  272. * => timeout + 13 >= log2(mmc->clock/4)
  273. * Rounding up to next power of 2
  274. * => timeout + 13 = log2(mmc->clock/4) + 1
  275. * => timeout + 13 = fls(mmc->clock/4)
  276. *
  277. * However, the MMC spec "It is strongly recommended for hosts to
  278. * implement more than 500ms timeout value even if the card
  279. * indicates the 250ms maximum busy length." Even the previous
  280. * value of 300ms is known to be insufficient for some cards.
  281. * So, we use
  282. * => timeout + 13 = fls(mmc->clock/2)
  283. */
  284. timeout = fls(mmc->clock/2);
  285. timeout -= 13;
  286. if (timeout > 14)
  287. timeout = 14;
  288. if (timeout < 0)
  289. timeout = 0;
  290. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
  291. (timeout == 4 || timeout == 8 || timeout == 12))
  292. timeout++;
  293. if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
  294. timeout = 0xE;
  295. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  296. return 0;
  297. }
  298. /*
  299. * Sends a command out on the bus. Takes the mmc pointer,
  300. * a command pointer, and an optional data pointer.
  301. */
  302. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  303. struct mmc_cmd *cmd, struct mmc_data *data)
  304. {
  305. int err = 0;
  306. uint xfertyp;
  307. uint irqstat;
  308. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  309. struct fsl_esdhc *regs = priv->esdhc_regs;
  310. unsigned long start;
  311. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
  312. cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  313. return 0;
  314. esdhc_write32(&regs->irqstat, -1);
  315. sync();
  316. /* Wait for the bus to be idle */
  317. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  318. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  319. ;
  320. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  321. ;
  322. /* Wait at least 8 SD clock cycles before the next command */
  323. /*
  324. * Note: This is way more than 8 cycles, but 1ms seems to
  325. * resolve timing issues with some cards
  326. */
  327. udelay(1000);
  328. /* Set up for a data transfer if we have one */
  329. if (data) {
  330. err = esdhc_setup_data(priv, mmc, data);
  331. if(err)
  332. return err;
  333. }
  334. /* Figure out the transfer arguments */
  335. xfertyp = esdhc_xfertyp(cmd, data);
  336. /* Mask all irqs */
  337. esdhc_write32(&regs->irqsigen, 0);
  338. /* Send the command */
  339. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  340. esdhc_write32(&regs->xfertyp, xfertyp);
  341. if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  342. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
  343. flags = IRQSTAT_BRR;
  344. /* Wait for the command to complete */
  345. start = get_timer(0);
  346. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  347. if (get_timer(start) > 1000) {
  348. err = -ETIMEDOUT;
  349. goto out;
  350. }
  351. }
  352. irqstat = esdhc_read32(&regs->irqstat);
  353. if (irqstat & CMD_ERR) {
  354. err = -ECOMM;
  355. goto out;
  356. }
  357. if (irqstat & IRQSTAT_CTOE) {
  358. err = -ETIMEDOUT;
  359. goto out;
  360. }
  361. /* Workaround for ESDHC errata ENGcm03648 */
  362. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  363. int timeout = 6000;
  364. /* Poll on DATA0 line for cmd with busy signal for 600 ms */
  365. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  366. PRSSTAT_DAT0)) {
  367. udelay(100);
  368. timeout--;
  369. }
  370. if (timeout <= 0) {
  371. printf("Timeout waiting for DAT0 to go high!\n");
  372. err = -ETIMEDOUT;
  373. goto out;
  374. }
  375. }
  376. /* Copy the response to the response buffer */
  377. if (cmd->resp_type & MMC_RSP_136) {
  378. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  379. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  380. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  381. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  382. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  383. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  384. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  385. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  386. cmd->response[3] = (cmdrsp0 << 8);
  387. } else
  388. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  389. /* Wait until all of the blocks are transferred */
  390. if (data) {
  391. if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
  392. esdhc_pio_read_write(priv, data);
  393. } else {
  394. flags = DATA_COMPLETE;
  395. if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  396. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
  397. flags = IRQSTAT_BRR;
  398. do {
  399. irqstat = esdhc_read32(&regs->irqstat);
  400. if (irqstat & IRQSTAT_DTOE) {
  401. err = -ETIMEDOUT;
  402. goto out;
  403. }
  404. if (irqstat & DATA_ERR) {
  405. err = -ECOMM;
  406. goto out;
  407. }
  408. } while ((irqstat & flags) != flags);
  409. /*
  410. * Need invalidate the dcache here again to avoid any
  411. * cache-fill during the DMA operations such as the
  412. * speculative pre-fetching etc.
  413. */
  414. dma_unmap_single(priv->dma_addr,
  415. data->blocks * data->blocksize,
  416. mmc_get_dma_dir(data));
  417. }
  418. }
  419. out:
  420. /* Reset CMD and DATA portions on error */
  421. if (err) {
  422. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  423. SYSCTL_RSTC);
  424. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  425. ;
  426. if (data) {
  427. esdhc_write32(&regs->sysctl,
  428. esdhc_read32(&regs->sysctl) |
  429. SYSCTL_RSTD);
  430. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  431. ;
  432. }
  433. }
  434. esdhc_write32(&regs->irqstat, -1);
  435. return err;
  436. }
  437. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  438. {
  439. struct fsl_esdhc *regs = priv->esdhc_regs;
  440. int div = 1;
  441. int pre_div = 2;
  442. unsigned int sdhc_clk = priv->sdhc_clk;
  443. u32 time_out;
  444. u32 value;
  445. uint clk;
  446. if (clock < mmc->cfg->f_min)
  447. clock = mmc->cfg->f_min;
  448. while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
  449. pre_div *= 2;
  450. while (sdhc_clk / (div * pre_div) > clock && div < 16)
  451. div++;
  452. mmc->clock = sdhc_clk / pre_div / div;
  453. priv->clock = mmc->clock;
  454. pre_div >>= 1;
  455. div -= 1;
  456. clk = (pre_div << 8) | (div << 4);
  457. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  458. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  459. time_out = 20;
  460. value = PRSSTAT_SDSTB;
  461. while (!(esdhc_read32(&regs->prsstat) & value)) {
  462. if (time_out == 0) {
  463. printf("fsl_esdhc: Internal clock never stabilised.\n");
  464. break;
  465. }
  466. time_out--;
  467. mdelay(1);
  468. }
  469. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  470. }
  471. static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
  472. {
  473. struct fsl_esdhc *regs = priv->esdhc_regs;
  474. u32 value;
  475. u32 time_out;
  476. value = esdhc_read32(&regs->sysctl);
  477. if (enable)
  478. value |= SYSCTL_CKEN;
  479. else
  480. value &= ~SYSCTL_CKEN;
  481. esdhc_write32(&regs->sysctl, value);
  482. time_out = 20;
  483. value = PRSSTAT_SDSTB;
  484. while (!(esdhc_read32(&regs->prsstat) & value)) {
  485. if (time_out == 0) {
  486. printf("fsl_esdhc: Internal clock never stabilised.\n");
  487. break;
  488. }
  489. time_out--;
  490. mdelay(1);
  491. }
  492. }
  493. static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv)
  494. {
  495. struct fsl_esdhc *regs = priv->esdhc_regs;
  496. u32 time_out;
  497. esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_FAF);
  498. time_out = 20;
  499. while (esdhc_read32(&regs->esdhcctl) & ESDHCCTL_FAF) {
  500. if (time_out == 0) {
  501. printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n");
  502. break;
  503. }
  504. time_out--;
  505. mdelay(1);
  506. }
  507. }
  508. static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv,
  509. bool en)
  510. {
  511. struct fsl_esdhc *regs = priv->esdhc_regs;
  512. esdhc_clock_control(priv, false);
  513. esdhc_flush_async_fifo(priv);
  514. if (en)
  515. esdhc_setbits32(&regs->tbctl, TBCTL_TB_EN);
  516. else
  517. esdhc_clrbits32(&regs->tbctl, TBCTL_TB_EN);
  518. esdhc_clock_control(priv, true);
  519. }
  520. static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv)
  521. {
  522. struct fsl_esdhc *regs = priv->esdhc_regs;
  523. esdhc_clrbits32(&regs->sdtimingctl, FLW_CTL_BG);
  524. esdhc_clrbits32(&regs->sdclkctl, CMD_CLK_CTL);
  525. esdhc_clock_control(priv, false);
  526. esdhc_clrbits32(&regs->tbctl, HS400_MODE);
  527. esdhc_clock_control(priv, true);
  528. esdhc_clrbits32(&regs->dllcfg0, DLL_FREQ_SEL | DLL_ENABLE);
  529. esdhc_clrbits32(&regs->tbctl, HS400_WNDW_ADJUST);
  530. esdhc_tuning_block_enable(priv, false);
  531. }
  532. static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
  533. {
  534. struct fsl_esdhc *regs = priv->esdhc_regs;
  535. ulong start;
  536. u32 val;
  537. /* Exit HS400 mode before setting any other mode */
  538. if (esdhc_read32(&regs->tbctl) & HS400_MODE &&
  539. mode != MMC_HS_400)
  540. esdhc_exit_hs400(priv);
  541. esdhc_clock_control(priv, false);
  542. if (mode == MMC_HS_200)
  543. esdhc_clrsetbits32(&regs->autoc12err, UHSM_MASK,
  544. UHSM_SDR104_HS200);
  545. if (mode == MMC_HS_400) {
  546. esdhc_setbits32(&regs->tbctl, HS400_MODE);
  547. esdhc_setbits32(&regs->sdclkctl, CMD_CLK_CTL);
  548. esdhc_clock_control(priv, true);
  549. if (priv->clock == 200000000)
  550. esdhc_setbits32(&regs->dllcfg0, DLL_FREQ_SEL);
  551. esdhc_setbits32(&regs->dllcfg0, DLL_ENABLE);
  552. esdhc_setbits32(&regs->dllcfg0, DLL_RESET);
  553. udelay(1);
  554. esdhc_clrbits32(&regs->dllcfg0, DLL_RESET);
  555. start = get_timer(0);
  556. val = DLL_STS_SLV_LOCK;
  557. while (!(esdhc_read32(&regs->dllstat0) & val)) {
  558. if (get_timer(start) > 1000) {
  559. printf("fsl_esdhc: delay chain lock timeout\n");
  560. return -ETIMEDOUT;
  561. }
  562. }
  563. esdhc_setbits32(&regs->tbctl, HS400_WNDW_ADJUST);
  564. esdhc_clock_control(priv, false);
  565. esdhc_flush_async_fifo(priv);
  566. }
  567. esdhc_clock_control(priv, true);
  568. return 0;
  569. }
  570. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  571. {
  572. struct fsl_esdhc *regs = priv->esdhc_regs;
  573. int ret;
  574. if (priv->is_sdhc_per_clk) {
  575. /* Select to use peripheral clock */
  576. esdhc_clock_control(priv, false);
  577. esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_PCS);
  578. esdhc_clock_control(priv, true);
  579. }
  580. if (mmc->selected_mode == MMC_HS_400)
  581. esdhc_tuning_block_enable(priv, true);
  582. /* Set the clock speed */
  583. if (priv->clock != mmc->clock)
  584. set_sysctl(priv, mmc, mmc->clock);
  585. /* Set timing */
  586. ret = esdhc_set_timing(priv, mmc->selected_mode);
  587. if (ret)
  588. return ret;
  589. /* Set the bus width */
  590. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  591. if (mmc->bus_width == 4)
  592. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  593. else if (mmc->bus_width == 8)
  594. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  595. return 0;
  596. }
  597. static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
  598. {
  599. #ifdef CONFIG_ARCH_MPC830X
  600. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  601. sysconf83xx_t *sysconf = &immr->sysconf;
  602. setbits_be32(&sysconf->sdhccr, 0x02000000);
  603. #else
  604. esdhc_write32(&regs->esdhcctl, 0x00000040);
  605. #endif
  606. }
  607. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  608. {
  609. struct fsl_esdhc *regs = priv->esdhc_regs;
  610. ulong start;
  611. /* Reset the entire host controller */
  612. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  613. /* Wait until the controller is available */
  614. start = get_timer(0);
  615. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  616. if (get_timer(start) > 1000)
  617. return -ETIMEDOUT;
  618. }
  619. /* Clean TBCTL[TB_EN] which is not able to be reset by reset all */
  620. esdhc_clrbits32(&regs->tbctl, TBCTL_TB_EN);
  621. esdhc_enable_cache_snooping(regs);
  622. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  623. /* Set the initial clock speed */
  624. set_sysctl(priv, mmc, 400000);
  625. /* Disable the BRR and BWR bits in IRQSTAT */
  626. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  627. /* Put the PROCTL reg back to the default */
  628. esdhc_write32(&regs->proctl, PROCTL_INIT);
  629. /* Set timout to the maximum value */
  630. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  631. return 0;
  632. }
  633. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  634. {
  635. struct fsl_esdhc *regs = priv->esdhc_regs;
  636. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  637. if (CONFIG_ESDHC_DETECT_QUIRK)
  638. return 1;
  639. #endif
  640. if (esdhc_read32(&regs->prsstat) & PRSSTAT_CINS)
  641. return 1;
  642. return 0;
  643. }
  644. static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
  645. struct mmc_config *cfg)
  646. {
  647. struct fsl_esdhc *regs = priv->esdhc_regs;
  648. u32 caps;
  649. caps = esdhc_read32(&regs->hostcapblt);
  650. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
  651. caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
  652. if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
  653. caps |= HOSTCAPBLT_VS33;
  654. if (caps & HOSTCAPBLT_VS18)
  655. cfg->voltages |= MMC_VDD_165_195;
  656. if (caps & HOSTCAPBLT_VS30)
  657. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  658. if (caps & HOSTCAPBLT_VS33)
  659. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  660. cfg->name = "FSL_SDHC";
  661. if (caps & HOSTCAPBLT_HSS)
  662. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  663. cfg->f_min = 400000;
  664. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  665. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  666. }
  667. #ifdef CONFIG_OF_LIBFDT
  668. __weak int esdhc_status_fixup(void *blob, const char *compat)
  669. {
  670. if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
  671. do_fixup_by_compat(blob, compat, "status", "disabled",
  672. sizeof("disabled"), 1);
  673. return 1;
  674. }
  675. return 0;
  676. }
  677. #if CONFIG_IS_ENABLED(DM_MMC)
  678. static int fsl_esdhc_get_cd(struct udevice *dev);
  679. static void esdhc_disable_for_no_card(void *blob)
  680. {
  681. struct udevice *dev;
  682. for (uclass_first_device(UCLASS_MMC, &dev);
  683. dev;
  684. uclass_next_device(&dev)) {
  685. char esdhc_path[50];
  686. if (fsl_esdhc_get_cd(dev))
  687. continue;
  688. snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
  689. (unsigned long)dev_read_addr(dev));
  690. do_fixup_by_path(blob, esdhc_path, "status", "disabled",
  691. sizeof("disabled"), 1);
  692. }
  693. }
  694. #else
  695. static void esdhc_disable_for_no_card(void *blob)
  696. {
  697. }
  698. #endif
  699. void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
  700. {
  701. const char *compat = "fsl,esdhc";
  702. if (esdhc_status_fixup(blob, compat))
  703. return;
  704. if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
  705. esdhc_disable_for_no_card(blob);
  706. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  707. gd->arch.sdhc_clk, 1);
  708. }
  709. #endif
  710. #if !CONFIG_IS_ENABLED(DM_MMC)
  711. static int esdhc_getcd(struct mmc *mmc)
  712. {
  713. struct fsl_esdhc_priv *priv = mmc->priv;
  714. return esdhc_getcd_common(priv);
  715. }
  716. static int esdhc_init(struct mmc *mmc)
  717. {
  718. struct fsl_esdhc_priv *priv = mmc->priv;
  719. return esdhc_init_common(priv, mmc);
  720. }
  721. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  722. struct mmc_data *data)
  723. {
  724. struct fsl_esdhc_priv *priv = mmc->priv;
  725. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  726. }
  727. static int esdhc_set_ios(struct mmc *mmc)
  728. {
  729. struct fsl_esdhc_priv *priv = mmc->priv;
  730. return esdhc_set_ios_common(priv, mmc);
  731. }
  732. static const struct mmc_ops esdhc_ops = {
  733. .getcd = esdhc_getcd,
  734. .init = esdhc_init,
  735. .send_cmd = esdhc_send_cmd,
  736. .set_ios = esdhc_set_ios,
  737. };
  738. int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
  739. {
  740. struct fsl_esdhc_plat *plat;
  741. struct fsl_esdhc_priv *priv;
  742. struct mmc_config *mmc_cfg;
  743. struct mmc *mmc;
  744. if (!cfg)
  745. return -EINVAL;
  746. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  747. if (!priv)
  748. return -ENOMEM;
  749. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  750. if (!plat) {
  751. free(priv);
  752. return -ENOMEM;
  753. }
  754. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  755. priv->sdhc_clk = cfg->sdhc_clk;
  756. if (gd->arch.sdhc_per_clk)
  757. priv->is_sdhc_per_clk = true;
  758. mmc_cfg = &plat->cfg;
  759. if (cfg->max_bus_width == 8) {
  760. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
  761. MMC_MODE_8BIT;
  762. } else if (cfg->max_bus_width == 4) {
  763. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
  764. } else if (cfg->max_bus_width == 1) {
  765. mmc_cfg->host_caps |= MMC_MODE_1BIT;
  766. } else {
  767. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
  768. MMC_MODE_8BIT;
  769. printf("No max bus width provided. Assume 8-bit supported.\n");
  770. }
  771. if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
  772. mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
  773. mmc_cfg->ops = &esdhc_ops;
  774. fsl_esdhc_get_cfg_common(priv, mmc_cfg);
  775. mmc = mmc_create(mmc_cfg, priv);
  776. if (!mmc)
  777. return -EIO;
  778. priv->mmc = mmc;
  779. return 0;
  780. }
  781. int fsl_esdhc_mmc_init(struct bd_info *bis)
  782. {
  783. struct fsl_esdhc_cfg *cfg;
  784. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  785. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  786. /* Prefer peripheral clock which provides higher frequency. */
  787. if (gd->arch.sdhc_per_clk)
  788. cfg->sdhc_clk = gd->arch.sdhc_per_clk;
  789. else
  790. cfg->sdhc_clk = gd->arch.sdhc_clk;
  791. return fsl_esdhc_initialize(bis, cfg);
  792. }
  793. #else /* DM_MMC */
  794. static int fsl_esdhc_probe(struct udevice *dev)
  795. {
  796. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  797. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  798. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  799. u32 caps, hostver;
  800. fdt_addr_t addr;
  801. struct mmc *mmc;
  802. int ret;
  803. addr = dev_read_addr(dev);
  804. if (addr == FDT_ADDR_T_NONE)
  805. return -EINVAL;
  806. #ifdef CONFIG_PPC
  807. priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
  808. #else
  809. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  810. #endif
  811. priv->dev = dev;
  812. if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2)) {
  813. /*
  814. * Only newer eSDHC controllers can do ADMA2 if the ADMA flag
  815. * is set in the host capabilities register.
  816. */
  817. caps = esdhc_read32(&priv->esdhc_regs->hostcapblt);
  818. hostver = esdhc_read32(&priv->esdhc_regs->hostver);
  819. if (caps & HOSTCAPBLT_DMAS &&
  820. HOSTVER_VENDOR(hostver) > VENDOR_V_22) {
  821. priv->adma_desc_table = sdhci_adma_init();
  822. if (!priv->adma_desc_table)
  823. debug("Could not allocate ADMA tables, falling back to SDMA\n");
  824. }
  825. }
  826. if (gd->arch.sdhc_per_clk) {
  827. priv->sdhc_clk = gd->arch.sdhc_per_clk;
  828. priv->is_sdhc_per_clk = true;
  829. } else {
  830. priv->sdhc_clk = gd->arch.sdhc_clk;
  831. }
  832. if (priv->sdhc_clk <= 0) {
  833. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  834. return -EINVAL;
  835. }
  836. fsl_esdhc_get_cfg_common(priv, &plat->cfg);
  837. mmc_of_parse(dev, &plat->cfg);
  838. mmc = &plat->mmc;
  839. mmc->cfg = &plat->cfg;
  840. mmc->dev = dev;
  841. upriv->mmc = mmc;
  842. ret = esdhc_init_common(priv, mmc);
  843. if (ret)
  844. return ret;
  845. if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
  846. !fsl_esdhc_get_cd(dev))
  847. esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
  848. return 0;
  849. }
  850. static int fsl_esdhc_get_cd(struct udevice *dev)
  851. {
  852. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  853. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  854. if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
  855. return 1;
  856. return esdhc_getcd_common(priv);
  857. }
  858. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  859. struct mmc_data *data)
  860. {
  861. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  862. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  863. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  864. }
  865. static int fsl_esdhc_set_ios(struct udevice *dev)
  866. {
  867. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  868. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  869. return esdhc_set_ios_common(priv, &plat->mmc);
  870. }
  871. static int fsl_esdhc_reinit(struct udevice *dev)
  872. {
  873. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  874. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  875. return esdhc_init_common(priv, &plat->mmc);
  876. }
  877. #ifdef MMC_SUPPORTS_TUNING
  878. static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
  879. {
  880. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  881. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  882. struct fsl_esdhc *regs = priv->esdhc_regs;
  883. u32 val, irqstaten;
  884. int i;
  885. esdhc_tuning_block_enable(priv, true);
  886. esdhc_setbits32(&regs->autoc12err, EXECUTE_TUNING);
  887. irqstaten = esdhc_read32(&regs->irqstaten);
  888. esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
  889. for (i = 0; i < MAX_TUNING_LOOP; i++) {
  890. mmc_send_tuning(&plat->mmc, opcode, NULL);
  891. mdelay(1);
  892. val = esdhc_read32(&regs->autoc12err);
  893. if (!(val & EXECUTE_TUNING)) {
  894. if (val & SMPCLKSEL)
  895. break;
  896. }
  897. }
  898. esdhc_write32(&regs->irqstaten, irqstaten);
  899. if (i != MAX_TUNING_LOOP) {
  900. if (plat->mmc.hs400_tuning)
  901. esdhc_setbits32(&regs->sdtimingctl, FLW_CTL_BG);
  902. return 0;
  903. }
  904. printf("fsl_esdhc: tuning failed!\n");
  905. esdhc_clrbits32(&regs->autoc12err, SMPCLKSEL);
  906. esdhc_clrbits32(&regs->autoc12err, EXECUTE_TUNING);
  907. esdhc_tuning_block_enable(priv, false);
  908. return -ETIMEDOUT;
  909. }
  910. #endif
  911. int fsl_esdhc_hs400_prepare_ddr(struct udevice *dev)
  912. {
  913. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  914. esdhc_tuning_block_enable(priv, false);
  915. return 0;
  916. }
  917. static const struct dm_mmc_ops fsl_esdhc_ops = {
  918. .get_cd = fsl_esdhc_get_cd,
  919. .send_cmd = fsl_esdhc_send_cmd,
  920. .set_ios = fsl_esdhc_set_ios,
  921. #ifdef MMC_SUPPORTS_TUNING
  922. .execute_tuning = fsl_esdhc_execute_tuning,
  923. #endif
  924. .reinit = fsl_esdhc_reinit,
  925. .hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr,
  926. };
  927. static const struct udevice_id fsl_esdhc_ids[] = {
  928. { .compatible = "fsl,esdhc", },
  929. { /* sentinel */ }
  930. };
  931. static int fsl_esdhc_bind(struct udevice *dev)
  932. {
  933. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  934. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  935. }
  936. U_BOOT_DRIVER(fsl_esdhc) = {
  937. .name = "fsl-esdhc-mmc",
  938. .id = UCLASS_MMC,
  939. .of_match = fsl_esdhc_ids,
  940. .ops = &fsl_esdhc_ops,
  941. .bind = fsl_esdhc_bind,
  942. .probe = fsl_esdhc_probe,
  943. .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
  944. .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
  945. };
  946. #endif