dw_mmc.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Jaehoon Chung <jh80.chung@samsung.com>
  5. * Rajeshawari Shinde <rajeshwari.s@samsung.com>
  6. */
  7. #include <bouncebuf.h>
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <memalign.h>
  14. #include <mmc.h>
  15. #include <dwmmc.h>
  16. #include <wait_bit.h>
  17. #include <asm/cache.h>
  18. #include <linux/delay.h>
  19. #include <power/regulator.h>
  20. #define PAGE_SIZE 4096
  21. static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  22. {
  23. unsigned long timeout = 1000;
  24. u32 ctrl;
  25. dwmci_writel(host, DWMCI_CTRL, value);
  26. while (timeout--) {
  27. ctrl = dwmci_readl(host, DWMCI_CTRL);
  28. if (!(ctrl & DWMCI_RESET_ALL))
  29. return 1;
  30. }
  31. return 0;
  32. }
  33. static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  34. u32 desc0, u32 desc1, u32 desc2)
  35. {
  36. struct dwmci_idmac *desc = idmac;
  37. desc->flags = desc0;
  38. desc->cnt = desc1;
  39. desc->addr = desc2;
  40. desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
  41. }
  42. static void dwmci_prepare_data(struct dwmci_host *host,
  43. struct mmc_data *data,
  44. struct dwmci_idmac *cur_idmac,
  45. void *bounce_buffer)
  46. {
  47. unsigned long ctrl;
  48. unsigned int i = 0, flags, cnt, blk_cnt;
  49. ulong data_start, data_end;
  50. blk_cnt = data->blocks;
  51. dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  52. /* Clear IDMAC interrupt */
  53. dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
  54. data_start = (ulong)cur_idmac;
  55. dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
  56. do {
  57. flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  58. flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  59. if (blk_cnt <= 8) {
  60. flags |= DWMCI_IDMAC_LD;
  61. cnt = data->blocksize * blk_cnt;
  62. } else
  63. cnt = data->blocksize * 8;
  64. dwmci_set_idma_desc(cur_idmac, flags, cnt,
  65. (ulong)bounce_buffer + (i * PAGE_SIZE));
  66. cur_idmac++;
  67. if (blk_cnt <= 8)
  68. break;
  69. blk_cnt -= 8;
  70. i++;
  71. } while(1);
  72. data_end = (ulong)cur_idmac;
  73. flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
  74. ctrl = dwmci_readl(host, DWMCI_CTRL);
  75. ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  76. dwmci_writel(host, DWMCI_CTRL, ctrl);
  77. ctrl = dwmci_readl(host, DWMCI_BMOD);
  78. ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  79. dwmci_writel(host, DWMCI_BMOD, ctrl);
  80. dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  81. dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  82. }
  83. static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
  84. {
  85. u32 timeout = 20000;
  86. *len = dwmci_readl(host, DWMCI_STATUS);
  87. while (--timeout && (*len & bit)) {
  88. udelay(200);
  89. *len = dwmci_readl(host, DWMCI_STATUS);
  90. }
  91. if (!timeout) {
  92. debug("%s: FIFO underflow timeout\n", __func__);
  93. return -ETIMEDOUT;
  94. }
  95. return 0;
  96. }
  97. static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
  98. {
  99. unsigned int timeout;
  100. timeout = size * 8; /* counting in bits */
  101. timeout *= 10; /* wait 10 times as long */
  102. timeout /= mmc->clock;
  103. timeout /= mmc->bus_width;
  104. timeout /= mmc->ddr_mode ? 2 : 1;
  105. timeout *= 1000; /* counting in msec */
  106. timeout = (timeout < 1000) ? 1000 : timeout;
  107. return timeout;
  108. }
  109. static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
  110. {
  111. struct mmc *mmc = host->mmc;
  112. int ret = 0;
  113. u32 timeout, mask, size, i, len = 0;
  114. u32 *buf = NULL;
  115. ulong start = get_timer(0);
  116. u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
  117. RX_WMARK_SHIFT) + 1) * 2;
  118. size = data->blocksize * data->blocks;
  119. if (data->flags == MMC_DATA_READ)
  120. buf = (unsigned int *)data->dest;
  121. else
  122. buf = (unsigned int *)data->src;
  123. timeout = dwmci_get_timeout(mmc, size);
  124. size /= 4;
  125. for (;;) {
  126. mask = dwmci_readl(host, DWMCI_RINTSTS);
  127. /* Error during data transfer. */
  128. if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
  129. debug("%s: DATA ERROR!\n", __func__);
  130. ret = -EINVAL;
  131. break;
  132. }
  133. if (host->fifo_mode && size) {
  134. len = 0;
  135. if (data->flags == MMC_DATA_READ &&
  136. (mask & DWMCI_INTMSK_RXDR)) {
  137. while (size) {
  138. ret = dwmci_fifo_ready(host,
  139. DWMCI_FIFO_EMPTY,
  140. &len);
  141. if (ret < 0)
  142. break;
  143. len = (len >> DWMCI_FIFO_SHIFT) &
  144. DWMCI_FIFO_MASK;
  145. len = min(size, len);
  146. for (i = 0; i < len; i++)
  147. *buf++ =
  148. dwmci_readl(host, DWMCI_DATA);
  149. size = size > len ? (size - len) : 0;
  150. }
  151. dwmci_writel(host, DWMCI_RINTSTS,
  152. DWMCI_INTMSK_RXDR);
  153. } else if (data->flags == MMC_DATA_WRITE &&
  154. (mask & DWMCI_INTMSK_TXDR)) {
  155. while (size) {
  156. ret = dwmci_fifo_ready(host,
  157. DWMCI_FIFO_FULL,
  158. &len);
  159. if (ret < 0)
  160. break;
  161. len = fifo_depth - ((len >>
  162. DWMCI_FIFO_SHIFT) &
  163. DWMCI_FIFO_MASK);
  164. len = min(size, len);
  165. for (i = 0; i < len; i++)
  166. dwmci_writel(host, DWMCI_DATA,
  167. *buf++);
  168. size = size > len ? (size - len) : 0;
  169. }
  170. dwmci_writel(host, DWMCI_RINTSTS,
  171. DWMCI_INTMSK_TXDR);
  172. }
  173. }
  174. /* Data arrived correctly. */
  175. if (mask & DWMCI_INTMSK_DTO) {
  176. ret = 0;
  177. break;
  178. }
  179. /* Check for timeout. */
  180. if (get_timer(start) > timeout) {
  181. debug("%s: Timeout waiting for data!\n",
  182. __func__);
  183. ret = -ETIMEDOUT;
  184. break;
  185. }
  186. }
  187. dwmci_writel(host, DWMCI_RINTSTS, mask);
  188. return ret;
  189. }
  190. static int dwmci_set_transfer_mode(struct dwmci_host *host,
  191. struct mmc_data *data)
  192. {
  193. unsigned long mode;
  194. mode = DWMCI_CMD_DATA_EXP;
  195. if (data->flags & MMC_DATA_WRITE)
  196. mode |= DWMCI_CMD_RW;
  197. return mode;
  198. }
  199. #ifdef CONFIG_DM_MMC
  200. static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  201. struct mmc_data *data)
  202. {
  203. struct mmc *mmc = mmc_get_mmc_dev(dev);
  204. #else
  205. static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  206. struct mmc_data *data)
  207. {
  208. #endif
  209. struct dwmci_host *host = mmc->priv;
  210. ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
  211. data ? DIV_ROUND_UP(data->blocks, 8) : 0);
  212. int ret = 0, flags = 0, i;
  213. unsigned int timeout = 500;
  214. u32 retry = 100000;
  215. u32 mask, ctrl;
  216. ulong start = get_timer(0);
  217. struct bounce_buffer bbstate;
  218. while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
  219. if (get_timer(start) > timeout) {
  220. debug("%s: Timeout on data busy\n", __func__);
  221. return -ETIMEDOUT;
  222. }
  223. }
  224. dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
  225. if (data) {
  226. if (host->fifo_mode) {
  227. dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  228. dwmci_writel(host, DWMCI_BYTCNT,
  229. data->blocksize * data->blocks);
  230. dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  231. } else {
  232. if (data->flags == MMC_DATA_READ) {
  233. ret = bounce_buffer_start(&bbstate,
  234. (void*)data->dest,
  235. data->blocksize *
  236. data->blocks, GEN_BB_WRITE);
  237. } else {
  238. ret = bounce_buffer_start(&bbstate,
  239. (void*)data->src,
  240. data->blocksize *
  241. data->blocks, GEN_BB_READ);
  242. }
  243. if (ret)
  244. return ret;
  245. dwmci_prepare_data(host, data, cur_idmac,
  246. bbstate.bounce_buffer);
  247. }
  248. }
  249. dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
  250. if (data)
  251. flags = dwmci_set_transfer_mode(host, data);
  252. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
  253. return -1;
  254. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  255. flags |= DWMCI_CMD_ABORT_STOP;
  256. else
  257. flags |= DWMCI_CMD_PRV_DAT_WAIT;
  258. if (cmd->resp_type & MMC_RSP_PRESENT) {
  259. flags |= DWMCI_CMD_RESP_EXP;
  260. if (cmd->resp_type & MMC_RSP_136)
  261. flags |= DWMCI_CMD_RESP_LENGTH;
  262. }
  263. if (cmd->resp_type & MMC_RSP_CRC)
  264. flags |= DWMCI_CMD_CHECK_CRC;
  265. flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
  266. debug("Sending CMD%d\n",cmd->cmdidx);
  267. dwmci_writel(host, DWMCI_CMD, flags);
  268. for (i = 0; i < retry; i++) {
  269. mask = dwmci_readl(host, DWMCI_RINTSTS);
  270. if (mask & DWMCI_INTMSK_CDONE) {
  271. if (!data)
  272. dwmci_writel(host, DWMCI_RINTSTS, mask);
  273. break;
  274. }
  275. }
  276. if (i == retry) {
  277. debug("%s: Timeout.\n", __func__);
  278. return -ETIMEDOUT;
  279. }
  280. if (mask & DWMCI_INTMSK_RTO) {
  281. /*
  282. * Timeout here is not necessarily fatal. (e)MMC cards
  283. * will splat here when they receive CMD55 as they do
  284. * not support this command and that is exactly the way
  285. * to tell them apart from SD cards. Thus, this output
  286. * below shall be debug(). eMMC cards also do not favor
  287. * CMD8, please keep that in mind.
  288. */
  289. debug("%s: Response Timeout.\n", __func__);
  290. return -ETIMEDOUT;
  291. } else if (mask & DWMCI_INTMSK_RE) {
  292. debug("%s: Response Error.\n", __func__);
  293. return -EIO;
  294. } else if ((cmd->resp_type & MMC_RSP_CRC) &&
  295. (mask & DWMCI_INTMSK_RCRC)) {
  296. debug("%s: Response CRC Error.\n", __func__);
  297. return -EIO;
  298. }
  299. if (cmd->resp_type & MMC_RSP_PRESENT) {
  300. if (cmd->resp_type & MMC_RSP_136) {
  301. cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
  302. cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
  303. cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
  304. cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
  305. } else {
  306. cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
  307. }
  308. }
  309. if (data) {
  310. ret = dwmci_data_transfer(host, data);
  311. /* only dma mode need it */
  312. if (!host->fifo_mode) {
  313. if (data->flags == MMC_DATA_READ)
  314. mask = DWMCI_IDINTEN_RI;
  315. else
  316. mask = DWMCI_IDINTEN_TI;
  317. ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
  318. mask, true, 1000, false);
  319. if (ret)
  320. debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
  321. __func__, mask);
  322. /* clear interrupts */
  323. dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
  324. ctrl = dwmci_readl(host, DWMCI_CTRL);
  325. ctrl &= ~(DWMCI_DMA_EN);
  326. dwmci_writel(host, DWMCI_CTRL, ctrl);
  327. bounce_buffer_stop(&bbstate);
  328. }
  329. }
  330. udelay(100);
  331. return ret;
  332. }
  333. static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
  334. {
  335. u32 div, status;
  336. int timeout = 10000;
  337. unsigned long sclk;
  338. if ((freq == host->clock) || (freq == 0))
  339. return 0;
  340. /*
  341. * If host->get_mmc_clk isn't defined,
  342. * then assume that host->bus_hz is source clock value.
  343. * host->bus_hz should be set by user.
  344. */
  345. if (host->get_mmc_clk)
  346. sclk = host->get_mmc_clk(host, freq);
  347. else if (host->bus_hz)
  348. sclk = host->bus_hz;
  349. else {
  350. debug("%s: Didn't get source clock value.\n", __func__);
  351. return -EINVAL;
  352. }
  353. if (sclk == freq)
  354. div = 0; /* bypass mode */
  355. else
  356. div = DIV_ROUND_UP(sclk, 2 * freq);
  357. dwmci_writel(host, DWMCI_CLKENA, 0);
  358. dwmci_writel(host, DWMCI_CLKSRC, 0);
  359. dwmci_writel(host, DWMCI_CLKDIV, div);
  360. dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
  361. DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
  362. do {
  363. status = dwmci_readl(host, DWMCI_CMD);
  364. if (timeout-- < 0) {
  365. debug("%s: Timeout!\n", __func__);
  366. return -ETIMEDOUT;
  367. }
  368. } while (status & DWMCI_CMD_START);
  369. dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
  370. DWMCI_CLKEN_LOW_PWR);
  371. dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
  372. DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
  373. timeout = 10000;
  374. do {
  375. status = dwmci_readl(host, DWMCI_CMD);
  376. if (timeout-- < 0) {
  377. debug("%s: Timeout!\n", __func__);
  378. return -ETIMEDOUT;
  379. }
  380. } while (status & DWMCI_CMD_START);
  381. host->clock = freq;
  382. return 0;
  383. }
  384. #ifdef CONFIG_DM_MMC
  385. static int dwmci_set_ios(struct udevice *dev)
  386. {
  387. struct mmc *mmc = mmc_get_mmc_dev(dev);
  388. #else
  389. static int dwmci_set_ios(struct mmc *mmc)
  390. {
  391. #endif
  392. struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
  393. u32 ctype, regs;
  394. debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
  395. dwmci_setup_bus(host, mmc->clock);
  396. switch (mmc->bus_width) {
  397. case 8:
  398. ctype = DWMCI_CTYPE_8BIT;
  399. break;
  400. case 4:
  401. ctype = DWMCI_CTYPE_4BIT;
  402. break;
  403. default:
  404. ctype = DWMCI_CTYPE_1BIT;
  405. break;
  406. }
  407. dwmci_writel(host, DWMCI_CTYPE, ctype);
  408. regs = dwmci_readl(host, DWMCI_UHS_REG);
  409. if (mmc->ddr_mode)
  410. regs |= DWMCI_DDR_MODE;
  411. else
  412. regs &= ~DWMCI_DDR_MODE;
  413. dwmci_writel(host, DWMCI_UHS_REG, regs);
  414. if (host->clksel)
  415. host->clksel(host);
  416. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  417. if (mmc->vqmmc_supply) {
  418. int ret;
  419. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  420. regulator_set_value(mmc->vqmmc_supply, 1800000);
  421. else
  422. regulator_set_value(mmc->vqmmc_supply, 3300000);
  423. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
  424. if (ret)
  425. return ret;
  426. }
  427. #endif
  428. return 0;
  429. }
  430. static int dwmci_init(struct mmc *mmc)
  431. {
  432. struct dwmci_host *host = mmc->priv;
  433. if (host->board_init)
  434. host->board_init(host);
  435. dwmci_writel(host, DWMCI_PWREN, 1);
  436. if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
  437. debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
  438. return -EIO;
  439. }
  440. /* Enumerate at 400KHz */
  441. dwmci_setup_bus(host, mmc->cfg->f_min);
  442. dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
  443. dwmci_writel(host, DWMCI_INTMASK, 0);
  444. dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
  445. dwmci_writel(host, DWMCI_IDINTEN, 0);
  446. dwmci_writel(host, DWMCI_BMOD, 1);
  447. if (!host->fifoth_val) {
  448. uint32_t fifo_size;
  449. fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
  450. fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
  451. host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
  452. TX_WMARK(fifo_size / 2);
  453. }
  454. dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
  455. dwmci_writel(host, DWMCI_CLKENA, 0);
  456. dwmci_writel(host, DWMCI_CLKSRC, 0);
  457. if (!host->fifo_mode)
  458. dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
  459. return 0;
  460. }
  461. #ifdef CONFIG_DM_MMC
  462. int dwmci_probe(struct udevice *dev)
  463. {
  464. struct mmc *mmc = mmc_get_mmc_dev(dev);
  465. return dwmci_init(mmc);
  466. }
  467. const struct dm_mmc_ops dm_dwmci_ops = {
  468. .send_cmd = dwmci_send_cmd,
  469. .set_ios = dwmci_set_ios,
  470. };
  471. #else
  472. static const struct mmc_ops dwmci_ops = {
  473. .send_cmd = dwmci_send_cmd,
  474. .set_ios = dwmci_set_ios,
  475. .init = dwmci_init,
  476. };
  477. #endif
  478. void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
  479. u32 max_clk, u32 min_clk)
  480. {
  481. cfg->name = host->name;
  482. #ifndef CONFIG_DM_MMC
  483. cfg->ops = &dwmci_ops;
  484. #endif
  485. cfg->f_min = min_clk;
  486. cfg->f_max = max_clk;
  487. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  488. cfg->host_caps = host->caps;
  489. if (host->buswidth == 8) {
  490. cfg->host_caps |= MMC_MODE_8BIT;
  491. cfg->host_caps &= ~MMC_MODE_4BIT;
  492. } else {
  493. cfg->host_caps |= MMC_MODE_4BIT;
  494. cfg->host_caps &= ~MMC_MODE_8BIT;
  495. }
  496. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  497. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  498. }
  499. #ifdef CONFIG_BLK
  500. int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
  501. {
  502. return mmc_bind(dev, mmc, cfg);
  503. }
  504. #else
  505. int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
  506. {
  507. dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
  508. host->mmc = mmc_create(&host->cfg, host);
  509. if (host->mmc == NULL)
  510. return -1;
  511. return 0;
  512. }
  513. #endif