bcm2835_sdhci.c 6.9 KB

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  1. /*
  2. * This code was extracted from:
  3. * git://github.com/gonzoua/u-boot-pi.git master
  4. * and hence presumably (C) 2012 Oleksandr Tymoshenko
  5. *
  6. * Tweaks for U-Boot upstreaming
  7. * (C) 2012 Stephen Warren
  8. *
  9. * Portions (e.g. read/write macros, concepts for back-to-back register write
  10. * timing workarounds) obviously extracted from the Linux kernel at:
  11. * https://github.com/raspberrypi/linux.git rpi-3.6.y
  12. *
  13. * The Linux kernel code has the following (c) and license, which is hence
  14. * propagated to Oleksandr's tree and here:
  15. *
  16. * Support for SDHCI device on 2835
  17. * Based on sdhci-bcm2708.c (c) 2010 Broadcom
  18. *
  19. * This program is free software; you can redistribute it and/or modify
  20. * it under the terms of the GNU General Public License version 2 as
  21. * published by the Free Software Foundation.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  31. */
  32. /* Supports:
  33. * SDHCI platform device - Arasan SD controller in BCM2708
  34. *
  35. * Inspired by sdhci-pci.c, by Pierre Ossman
  36. */
  37. #include <common.h>
  38. #include <dm.h>
  39. #include <log.h>
  40. #include <malloc.h>
  41. #include <memalign.h>
  42. #include <sdhci.h>
  43. #include <time.h>
  44. #include <asm/arch/msg.h>
  45. #include <asm/arch/mbox.h>
  46. #include <mach/sdhci.h>
  47. #include <mach/timer.h>
  48. /* 400KHz is max freq for card ID etc. Use that as min */
  49. #define MIN_FREQ 400000
  50. #define SDHCI_BUFFER 0x20
  51. struct bcm2835_sdhci_plat {
  52. struct mmc_config cfg;
  53. struct mmc mmc;
  54. };
  55. struct bcm2835_sdhci_host {
  56. struct sdhci_host host;
  57. uint twoticks_delay;
  58. ulong last_write;
  59. };
  60. static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host)
  61. {
  62. return (struct bcm2835_sdhci_host *)host;
  63. }
  64. static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val,
  65. int reg)
  66. {
  67. struct bcm2835_sdhci_host *bcm_host = to_bcm(host);
  68. /*
  69. * The Arasan has a bugette whereby it may lose the content of
  70. * successive writes to registers that are within two SD-card clock
  71. * cycles of each other (a clock domain crossing problem).
  72. * It seems, however, that the data register does not have this problem.
  73. * (Which is just as well - otherwise we'd have to nobble the DMA engine
  74. * too)
  75. */
  76. if (reg != SDHCI_BUFFER) {
  77. while (timer_get_us() - bcm_host->last_write <
  78. bcm_host->twoticks_delay)
  79. ;
  80. }
  81. writel(val, host->ioaddr + reg);
  82. bcm_host->last_write = timer_get_us();
  83. }
  84. static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
  85. {
  86. return readl(host->ioaddr + reg);
  87. }
  88. static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  89. {
  90. bcm2835_sdhci_raw_writel(host, val, reg);
  91. }
  92. static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  93. {
  94. static u32 shadow;
  95. u32 oldval = (reg == SDHCI_COMMAND) ? shadow :
  96. bcm2835_sdhci_raw_readl(host, reg & ~3);
  97. u32 word_num = (reg >> 1) & 1;
  98. u32 word_shift = word_num * 16;
  99. u32 mask = 0xffff << word_shift;
  100. u32 newval = (oldval & ~mask) | (val << word_shift);
  101. if (reg == SDHCI_TRANSFER_MODE)
  102. shadow = newval;
  103. else
  104. bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
  105. }
  106. static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  107. {
  108. u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3);
  109. u32 byte_num = reg & 3;
  110. u32 byte_shift = byte_num * 8;
  111. u32 mask = 0xff << byte_shift;
  112. u32 newval = (oldval & ~mask) | (val << byte_shift);
  113. bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
  114. }
  115. static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
  116. {
  117. u32 val = bcm2835_sdhci_raw_readl(host, reg);
  118. return val;
  119. }
  120. static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
  121. {
  122. u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
  123. u32 word_num = (reg >> 1) & 1;
  124. u32 word_shift = word_num * 16;
  125. u32 word = (val >> word_shift) & 0xffff;
  126. return word;
  127. }
  128. static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
  129. {
  130. u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
  131. u32 byte_num = reg & 3;
  132. u32 byte_shift = byte_num * 8;
  133. u32 byte = (val >> byte_shift) & 0xff;
  134. return byte;
  135. }
  136. static const struct sdhci_ops bcm2835_ops = {
  137. .write_l = bcm2835_sdhci_writel,
  138. .write_w = bcm2835_sdhci_writew,
  139. .write_b = bcm2835_sdhci_writeb,
  140. .read_l = bcm2835_sdhci_readl,
  141. .read_w = bcm2835_sdhci_readw,
  142. .read_b = bcm2835_sdhci_readb,
  143. };
  144. static int bcm2835_sdhci_bind(struct udevice *dev)
  145. {
  146. struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
  147. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  148. }
  149. static int bcm2835_sdhci_probe(struct udevice *dev)
  150. {
  151. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  152. struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
  153. struct bcm2835_sdhci_host *priv = dev_get_priv(dev);
  154. struct sdhci_host *host = &priv->host;
  155. fdt_addr_t base;
  156. int emmc_freq;
  157. int ret;
  158. int clock_id = (int)dev_get_driver_data(dev);
  159. base = dev_read_addr(dev);
  160. if (base == FDT_ADDR_T_NONE)
  161. return -EINVAL;
  162. ret = bcm2835_get_mmc_clock(clock_id);
  163. if (ret < 0) {
  164. debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret);
  165. return ret;
  166. }
  167. emmc_freq = ret;
  168. /*
  169. * See the comments in bcm2835_sdhci_raw_writel().
  170. *
  171. * This should probably be dynamically calculated based on the actual
  172. * frequency. However, this is the longest we'll have to wait, and
  173. * doesn't seem to slow access down too much, so the added complexity
  174. * doesn't seem worth it for now.
  175. *
  176. * 1/MIN_FREQ is (max) time per tick of eMMC clock.
  177. * 2/MIN_FREQ is time for two ticks.
  178. * Multiply by 1000000 to get uS per two ticks.
  179. * +1 for hack rounding.
  180. */
  181. priv->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1;
  182. priv->last_write = 0;
  183. host->name = dev->name;
  184. host->ioaddr = (void *)(uintptr_t)base;
  185. host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
  186. SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
  187. host->max_clk = emmc_freq;
  188. host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  189. host->ops = &bcm2835_ops;
  190. host->mmc = &plat->mmc;
  191. host->mmc->dev = dev;
  192. ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ);
  193. if (ret) {
  194. debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret);
  195. return ret;
  196. }
  197. upriv->mmc = &plat->mmc;
  198. host->mmc->priv = host;
  199. return sdhci_probe(dev);
  200. }
  201. static const struct udevice_id bcm2835_sdhci_match[] = {
  202. {
  203. .compatible = "brcm,bcm2835-sdhci",
  204. .data = BCM2835_MBOX_CLOCK_ID_EMMC
  205. },
  206. {
  207. .compatible = "brcm,bcm2711-emmc2",
  208. .data = BCM2835_MBOX_CLOCK_ID_EMMC2
  209. },
  210. { /* sentinel */ }
  211. };
  212. U_BOOT_DRIVER(sdhci_cdns) = {
  213. .name = "sdhci-bcm2835",
  214. .id = UCLASS_MMC,
  215. .of_match = bcm2835_sdhci_match,
  216. .bind = bcm2835_sdhci_bind,
  217. .probe = bcm2835_sdhci_probe,
  218. .priv_auto_alloc_size = sizeof(struct bcm2835_sdhci_host),
  219. .platdata_auto_alloc_size = sizeof(struct bcm2835_sdhci_plat),
  220. .ops = &sdhci_ops,
  221. };