arm_pl180_mmci.h 5.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * ARM PrimeCell MultiMedia Card Interface - PL180
  4. *
  5. * Copyright (C) ST-Ericsson SA 2010
  6. *
  7. * Author: Ulf Hansson <ulf.hansson@stericsson.com>
  8. * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
  9. * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
  10. */
  11. #ifndef __ARM_PL180_MMCI_H__
  12. #define __ARM_PL180_MMCI_H__
  13. /* need definition of struct mmc_config */
  14. #include <mmc.h>
  15. #define COMMAND_REG_DELAY 300
  16. #define DATA_REG_DELAY 1000
  17. #define CLK_CHANGE_DELAY 2000
  18. #define INIT_PWR 0xBF /* Power on, full power, not open drain */
  19. #define ARM_MCLK (100*1000*1000)
  20. /* SDI Power Control register bits */
  21. #define SDI_PWR_PWRCTRL_MASK 0x00000003
  22. #define SDI_PWR_PWRCTRL_ON 0x00000003
  23. #define SDI_PWR_PWRCTRL_OFF 0x00000000
  24. #define SDI_PWR_DAT2DIREN 0x00000004
  25. #define SDI_PWR_CMDDIREN 0x00000008
  26. #define SDI_PWR_DAT0DIREN 0x00000010
  27. #define SDI_PWR_DAT31DIREN 0x00000020
  28. #define SDI_PWR_OPD 0x00000040
  29. #define SDI_PWR_FBCLKEN 0x00000080
  30. #define SDI_PWR_DAT74DIREN 0x00000100
  31. #define SDI_PWR_RSTEN 0x00000200
  32. #define VOLTAGE_WINDOW_MMC 0x00FF8080
  33. #define VOLTAGE_WINDOW_SD 0x80010000
  34. /* SDI clock control register bits */
  35. #define SDI_CLKCR_CLKDIV_MASK 0x000000FF
  36. #define SDI_CLKCR_CLKEN 0x00000100
  37. #define SDI_CLKCR_PWRSAV 0x00000200
  38. #define SDI_CLKCR_BYPASS 0x00000400
  39. #define SDI_CLKCR_WIDBUS_MASK 0x00001800
  40. #define SDI_CLKCR_WIDBUS_1 0x00000000
  41. #define SDI_CLKCR_WIDBUS_4 0x00000800
  42. /* V2 only */
  43. #define SDI_CLKCR_WIDBUS_8 0x00001000
  44. #define SDI_CLKCR_NEDGE 0x00002000
  45. #define SDI_CLKCR_HWFC_EN 0x00004000
  46. #define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
  47. #define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD
  48. /* SDI command register bits */
  49. #define SDI_CMD_CMDINDEX_MASK 0x000000FF
  50. #define SDI_CMD_WAITRESP 0x00000040
  51. #define SDI_CMD_LONGRESP 0x00000080
  52. #define SDI_CMD_WAITINT 0x00000100
  53. #define SDI_CMD_WAITPEND 0x00000200
  54. #define SDI_CMD_CPSMEN 0x00000400
  55. #define SDI_CMD_SDIOSUSPEND 0x00000800
  56. #define SDI_CMD_ENDCMDCOMPL 0x00001000
  57. #define SDI_CMD_NIEN 0x00002000
  58. #define SDI_CMD_CE_ATACMD 0x00004000
  59. #define SDI_CMD_CBOOTMODEEN 0x00008000
  60. #define SDI_DTIMER_DEFAULT 0xFFFF0000
  61. /* SDI Status register bits */
  62. #define SDI_STA_CCRCFAIL 0x00000001
  63. #define SDI_STA_DCRCFAIL 0x00000002
  64. #define SDI_STA_CTIMEOUT 0x00000004
  65. #define SDI_STA_DTIMEOUT 0x00000008
  66. #define SDI_STA_TXUNDERR 0x00000010
  67. #define SDI_STA_RXOVERR 0x00000020
  68. #define SDI_STA_CMDREND 0x00000040
  69. #define SDI_STA_CMDSENT 0x00000080
  70. #define SDI_STA_DATAEND 0x00000100
  71. #define SDI_STA_STBITERR 0x00000200
  72. #define SDI_STA_DBCKEND 0x00000400
  73. #define SDI_STA_CMDACT 0x00000800
  74. #define SDI_STA_TXACT 0x00001000
  75. #define SDI_STA_RXACT 0x00002000
  76. #define SDI_STA_TXFIFOBW 0x00004000
  77. #define SDI_STA_RXFIFOBR 0x00008000
  78. #define SDI_STA_TXFIFOF 0x00010000
  79. #define SDI_STA_RXFIFOF 0x00020000
  80. #define SDI_STA_TXFIFOE 0x00040000
  81. #define SDI_STA_RXFIFOE 0x00080000
  82. #define SDI_STA_TXDAVL 0x00100000
  83. #define SDI_STA_RXDAVL 0x00200000
  84. #define SDI_STA_SDIOIT 0x00400000
  85. #define SDI_STA_CEATAEND 0x00800000
  86. #define SDI_STA_CARDBUSY 0x01000000
  87. #define SDI_STA_BOOTMODE 0x02000000
  88. #define SDI_STA_BOOTACKERR 0x04000000
  89. #define SDI_STA_BOOTACKTIMEOUT 0x08000000
  90. #define SDI_STA_RSTNEND 0x10000000
  91. /* SDI Interrupt Clear register bits */
  92. #define SDI_ICR_MASK 0x1DC007FF
  93. #define SDI_ICR_CCRCFAILC 0x00000001
  94. #define SDI_ICR_DCRCFAILC 0x00000002
  95. #define SDI_ICR_CTIMEOUTC 0x00000004
  96. #define SDI_ICR_DTIMEOUTC 0x00000008
  97. #define SDI_ICR_TXUNDERRC 0x00000010
  98. #define SDI_ICR_RXOVERRC 0x00000020
  99. #define SDI_ICR_CMDRENDC 0x00000040
  100. #define SDI_ICR_CMDSENTC 0x00000080
  101. #define SDI_ICR_DATAENDC 0x00000100
  102. #define SDI_ICR_STBITERRC 0x00000200
  103. #define SDI_ICR_DBCKENDC 0x00000400
  104. #define SDI_ICR_SDIOITC 0x00400000
  105. #define SDI_ICR_CEATAENDC 0x00800000
  106. #define SDI_ICR_BUSYENDC 0x01000000
  107. #define SDI_ICR_BOOTACKERRC 0x04000000
  108. #define SDI_ICR_BOOTACKTIMEOUTC 0x08000000
  109. #define SDI_ICR_RSTNENDC 0x10000000
  110. #define SDI_MASK0_MASK 0x1FFFFFFF
  111. /* SDI Data control register bits */
  112. #define SDI_DCTRL_DTEN 0x00000001
  113. #define SDI_DCTRL_DTDIR_IN 0x00000002
  114. #define SDI_DCTRL_DTMODE_STREAM 0x00000004
  115. #define SDI_DCTRL_DMAEN 0x00000008
  116. #define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0
  117. #define SDI_DCTRL_RWSTART 0x00000100
  118. #define SDI_DCTRL_RWSTOP 0x00000200
  119. #define SDI_DCTRL_RWMOD 0x00000200
  120. #define SDI_DCTRL_SDIOEN 0x00000800
  121. #define SDI_DCTRL_DMAREQCTL 0x00001000
  122. #define SDI_DCTRL_DBOOTMODEEN 0x00002000
  123. #define SDI_DCTRL_BUSYMODE 0x00004000
  124. #define SDI_DCTRL_DDR_MODE 0x00008000
  125. #define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000
  126. #define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16
  127. #define SDI_FIFO_BURST_SIZE 8
  128. #define STM32_MMCI_ID 0x00880180
  129. struct sdi_registers {
  130. u32 power; /* 0x00*/
  131. u32 clock; /* 0x04*/
  132. u32 argument; /* 0x08*/
  133. u32 command; /* 0x0c*/
  134. u32 respcommand; /* 0x10*/
  135. u32 response0; /* 0x14*/
  136. u32 response1; /* 0x18*/
  137. u32 response2; /* 0x1c*/
  138. u32 response3; /* 0x20*/
  139. u32 datatimer; /* 0x24*/
  140. u32 datalength; /* 0x28*/
  141. u32 datactrl; /* 0x2c*/
  142. u32 datacount; /* 0x30*/
  143. u32 status; /* 0x34*/
  144. u32 status_clear; /* 0x38*/
  145. u32 mask0; /* 0x3c*/
  146. u32 mask1; /* 0x40*/
  147. u32 card_select; /* 0x44*/
  148. u32 fifo_count; /* 0x48*/
  149. u32 padding1[(0x80-0x4C)>>2];
  150. u32 fifo; /* 0x80*/
  151. u32 padding2[(0xFE0-0x84)>>2];
  152. u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/
  153. u32 periph_id1; /* 0xFE4*/
  154. u32 periph_id2; /* 0xFE8*/
  155. u32 periph_id3; /* 0xFEC*/
  156. u32 pcell_id0; /* 0xFF0*/
  157. u32 pcell_id1; /* 0xFF4*/
  158. u32 pcell_id2; /* 0xFF8*/
  159. u32 pcell_id3; /* 0xFFC*/
  160. };
  161. struct pl180_mmc_host {
  162. struct sdi_registers *base;
  163. char name[32];
  164. unsigned int b_max;
  165. unsigned int voltages;
  166. unsigned int caps;
  167. unsigned int clock_in;
  168. unsigned int clock_min;
  169. unsigned int clock_max;
  170. unsigned int clkdiv_init;
  171. unsigned int pwr_init;
  172. int version2;
  173. struct mmc_config cfg;
  174. #ifdef CONFIG_DM_MMC
  175. struct gpio_desc cd_gpio;
  176. #endif
  177. };
  178. int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc);
  179. #endif