sifive-otp.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
  4. * One-Time-Programmable (OTP) memory used within the SiFive FU540.
  5. * It is documented in the FU540 manual here:
  6. * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
  7. *
  8. * Copyright (C) 2018 Philipp Hug <philipp@hug.cx>
  9. * Copyright (C) 2018 Joey Hewitt <joey@joeyhewitt.com>
  10. *
  11. * Copyright (C) 2020 SiFive, Inc
  12. */
  13. /*
  14. * The FU540 stores 4096x32 bit (16KiB) values.
  15. * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
  16. * Right now first 1KiB is used to store only serial number.
  17. */
  18. #include <common.h>
  19. #include <dm/device.h>
  20. #include <dm/read.h>
  21. #include <linux/bitops.h>
  22. #include <linux/delay.h>
  23. #include <linux/io.h>
  24. #include <misc.h>
  25. #define BYTES_PER_FUSE 4
  26. #define PA_RESET_VAL 0x00
  27. #define PAS_RESET_VAL 0x00
  28. #define PAIO_RESET_VAL 0x00
  29. #define PDIN_RESET_VAL 0x00
  30. #define PTM_RESET_VAL 0x00
  31. #define PCLK_ENABLE_VAL BIT(0)
  32. #define PCLK_DISABLE_VAL 0x00
  33. #define PWE_WRITE_ENABLE BIT(0)
  34. #define PWE_WRITE_DISABLE 0x00
  35. #define PTM_FUSE_PROGRAM_VAL BIT(1)
  36. #define PCE_ENABLE_INPUT BIT(0)
  37. #define PCE_DISABLE_INPUT 0x00
  38. #define PPROG_ENABLE_INPUT BIT(0)
  39. #define PPROG_DISABLE_INPUT 0x00
  40. #define PTRIM_ENABLE_INPUT BIT(0)
  41. #define PTRIM_DISABLE_INPUT 0x00
  42. #define PDSTB_DEEP_STANDBY_ENABLE BIT(0)
  43. #define PDSTB_DEEP_STANDBY_DISABLE 0x00
  44. /* Tpw - Program Pulse width delay */
  45. #define TPW_DELAY 20
  46. /* Tpwi - Program Pulse interval delay */
  47. #define TPWI_DELAY 5
  48. /* Tasp - Program address setup delay */
  49. #define TASP_DELAY 1
  50. /* Tcd - read data access delay */
  51. #define TCD_DELAY 40
  52. /* Tkl - clok pulse low delay */
  53. #define TKL_DELAY 10
  54. /* Tms - PTM mode setup delay */
  55. #define TMS_DELAY 1
  56. struct sifive_otp_regs {
  57. u32 pa; /* Address input */
  58. u32 paio; /* Program address input */
  59. u32 pas; /* Program redundancy cell selection input */
  60. u32 pce; /* OTP Macro enable input */
  61. u32 pclk; /* Clock input */
  62. u32 pdin; /* Write data input */
  63. u32 pdout; /* Read data output */
  64. u32 pdstb; /* Deep standby mode enable input (active low) */
  65. u32 pprog; /* Program mode enable input */
  66. u32 ptc; /* Test column enable input */
  67. u32 ptm; /* Test mode enable input */
  68. u32 ptm_rep;/* Repair function test mode enable input */
  69. u32 ptr; /* Test row enable input */
  70. u32 ptrim; /* Repair function enable input */
  71. u32 pwe; /* Write enable input (defines program cycle) */
  72. };
  73. struct sifive_otp_platdata {
  74. struct sifive_otp_regs __iomem *regs;
  75. u32 total_fuses;
  76. };
  77. /*
  78. * offset and size are assumed aligned to the size of the fuses (32-bit).
  79. */
  80. static int sifive_otp_read(struct udevice *dev, int offset,
  81. void *buf, int size)
  82. {
  83. struct sifive_otp_platdata *plat = dev_get_platdata(dev);
  84. struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
  85. /* Check if offset and size are multiple of BYTES_PER_FUSE */
  86. if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
  87. printf("%s: size and offset must be multiple of 4.\n",
  88. __func__);
  89. return -EINVAL;
  90. }
  91. int fuseidx = offset / BYTES_PER_FUSE;
  92. int fusecount = size / BYTES_PER_FUSE;
  93. /* check bounds */
  94. if (offset < 0 || size < 0)
  95. return -EINVAL;
  96. if (fuseidx >= plat->total_fuses)
  97. return -EINVAL;
  98. if ((fuseidx + fusecount) > plat->total_fuses)
  99. return -EINVAL;
  100. u32 fusebuf[fusecount];
  101. /* init OTP */
  102. writel(PDSTB_DEEP_STANDBY_ENABLE, &regs->pdstb);
  103. writel(PTRIM_ENABLE_INPUT, &regs->ptrim);
  104. writel(PCE_ENABLE_INPUT, &regs->pce);
  105. /* read all requested fuses */
  106. for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
  107. writel(fuseidx, &regs->pa);
  108. /* cycle clock to read */
  109. writel(PCLK_ENABLE_VAL, &regs->pclk);
  110. ndelay(TCD_DELAY * 1000);
  111. writel(PCLK_DISABLE_VAL, &regs->pclk);
  112. ndelay(TKL_DELAY * 1000);
  113. /* read the value */
  114. fusebuf[i] = readl(&regs->pdout);
  115. }
  116. /* shut down */
  117. writel(PCE_DISABLE_INPUT, &regs->pce);
  118. writel(PTRIM_DISABLE_INPUT, &regs->ptrim);
  119. writel(PDSTB_DEEP_STANDBY_DISABLE, &regs->pdstb);
  120. /* copy out */
  121. memcpy(buf, fusebuf, size);
  122. return size;
  123. }
  124. /*
  125. * Caution:
  126. * OTP can be written only once, so use carefully.
  127. *
  128. * offset and size are assumed aligned to the size of the fuses (32-bit).
  129. */
  130. static int sifive_otp_write(struct udevice *dev, int offset,
  131. const void *buf, int size)
  132. {
  133. struct sifive_otp_platdata *plat = dev_get_platdata(dev);
  134. struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
  135. /* Check if offset and size are multiple of BYTES_PER_FUSE */
  136. if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
  137. printf("%s: size and offset must be multiple of 4.\n",
  138. __func__);
  139. return -EINVAL;
  140. }
  141. int fuseidx = offset / BYTES_PER_FUSE;
  142. int fusecount = size / BYTES_PER_FUSE;
  143. u32 *write_buf = (u32 *)buf;
  144. u32 write_data;
  145. int i, pas, bit;
  146. /* check bounds */
  147. if (offset < 0 || size < 0)
  148. return -EINVAL;
  149. if (fuseidx >= plat->total_fuses)
  150. return -EINVAL;
  151. if ((fuseidx + fusecount) > plat->total_fuses)
  152. return -EINVAL;
  153. /* init OTP */
  154. writel(PDSTB_DEEP_STANDBY_ENABLE, &regs->pdstb);
  155. writel(PTRIM_ENABLE_INPUT, &regs->ptrim);
  156. /* reset registers */
  157. writel(PCLK_DISABLE_VAL, &regs->pclk);
  158. writel(PA_RESET_VAL, &regs->pa);
  159. writel(PAS_RESET_VAL, &regs->pas);
  160. writel(PAIO_RESET_VAL, &regs->paio);
  161. writel(PDIN_RESET_VAL, &regs->pdin);
  162. writel(PWE_WRITE_DISABLE, &regs->pwe);
  163. writel(PTM_FUSE_PROGRAM_VAL, &regs->ptm);
  164. ndelay(TMS_DELAY * 1000);
  165. writel(PCE_ENABLE_INPUT, &regs->pce);
  166. writel(PPROG_ENABLE_INPUT, &regs->pprog);
  167. /* write all requested fuses */
  168. for (i = 0; i < fusecount; i++, fuseidx++) {
  169. writel(fuseidx, &regs->pa);
  170. write_data = *(write_buf++);
  171. for (pas = 0; pas < 2; pas++) {
  172. writel(pas, &regs->pas);
  173. for (bit = 0; bit < 32; bit++) {
  174. writel(bit, &regs->paio);
  175. writel(((write_data >> bit) & 1),
  176. &regs->pdin);
  177. ndelay(TASP_DELAY * 1000);
  178. writel(PWE_WRITE_ENABLE, &regs->pwe);
  179. udelay(TPW_DELAY);
  180. writel(PWE_WRITE_DISABLE, &regs->pwe);
  181. udelay(TPWI_DELAY);
  182. }
  183. }
  184. writel(PAS_RESET_VAL, &regs->pas);
  185. }
  186. /* shut down */
  187. writel(PWE_WRITE_DISABLE, &regs->pwe);
  188. writel(PPROG_DISABLE_INPUT, &regs->pprog);
  189. writel(PCE_DISABLE_INPUT, &regs->pce);
  190. writel(PTM_RESET_VAL, &regs->ptm);
  191. writel(PTRIM_DISABLE_INPUT, &regs->ptrim);
  192. writel(PDSTB_DEEP_STANDBY_DISABLE, &regs->pdstb);
  193. return size;
  194. }
  195. static int sifive_otp_ofdata_to_platdata(struct udevice *dev)
  196. {
  197. struct sifive_otp_platdata *plat = dev_get_platdata(dev);
  198. int ret;
  199. plat->regs = dev_read_addr_ptr(dev);
  200. ret = dev_read_u32(dev, "fuse-count", &plat->total_fuses);
  201. if (ret < 0) {
  202. pr_err("\"fuse-count\" not found\n");
  203. return ret;
  204. }
  205. return 0;
  206. }
  207. static const struct misc_ops sifive_otp_ops = {
  208. .read = sifive_otp_read,
  209. .write = sifive_otp_write,
  210. };
  211. static const struct udevice_id sifive_otp_ids[] = {
  212. { .compatible = "sifive,fu540-c000-otp" },
  213. {}
  214. };
  215. U_BOOT_DRIVER(sifive_otp) = {
  216. .name = "sifive_otp",
  217. .id = UCLASS_MISC,
  218. .of_match = sifive_otp_ids,
  219. .ofdata_to_platdata = sifive_otp_ofdata_to_platdata,
  220. .platdata_auto_alloc_size = sizeof(struct sifive_otp_platdata),
  221. .ops = &sifive_otp_ops,
  222. };