p2sb_emul.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PCI emulation device for an x86 Primary-to-Sideband bus
  4. *
  5. * Copyright 2019 Google LLC
  6. * Written by Simon Glass <sjg@chromium.org>
  7. */
  8. #define LOG_CATEGORY UCLASS_MISC
  9. #define LOG_DEBUG
  10. #include <common.h>
  11. #include <axi.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <pci.h>
  15. #include <asm/test.h>
  16. #include <p2sb.h>
  17. /**
  18. * struct p2sb_emul_platdata - platform data for this device
  19. *
  20. * @command: Current PCI command value
  21. * @bar: Current base address values
  22. */
  23. struct p2sb_emul_platdata {
  24. u16 command;
  25. u32 bar[6];
  26. };
  27. enum {
  28. /* This emulator supports 16 different devices */
  29. MEMMAP_SIZE = 16 << PCR_PORTID_SHIFT,
  30. };
  31. static struct pci_bar {
  32. int type;
  33. u32 size;
  34. } barinfo[] = {
  35. { PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE },
  36. { 0, 0 },
  37. { 0, 0 },
  38. { 0, 0 },
  39. { 0, 0 },
  40. { 0, 0 },
  41. };
  42. struct p2sb_emul_priv {
  43. u8 regs[16];
  44. };
  45. static int sandbox_p2sb_emul_read_config(const struct udevice *emul,
  46. uint offset, ulong *valuep,
  47. enum pci_size_t size)
  48. {
  49. struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
  50. switch (offset) {
  51. case PCI_COMMAND:
  52. *valuep = plat->command;
  53. break;
  54. case PCI_HEADER_TYPE:
  55. *valuep = PCI_HEADER_TYPE_NORMAL;
  56. break;
  57. case PCI_VENDOR_ID:
  58. *valuep = SANDBOX_PCI_VENDOR_ID;
  59. break;
  60. case PCI_DEVICE_ID:
  61. *valuep = SANDBOX_PCI_P2SB_EMUL_ID;
  62. break;
  63. case PCI_CLASS_DEVICE:
  64. if (size == PCI_SIZE_8) {
  65. *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
  66. } else {
  67. *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
  68. SANDBOX_PCI_CLASS_SUB_CODE;
  69. }
  70. break;
  71. case PCI_CLASS_CODE:
  72. *valuep = SANDBOX_PCI_CLASS_CODE;
  73. break;
  74. case PCI_BASE_ADDRESS_0:
  75. case PCI_BASE_ADDRESS_1:
  76. case PCI_BASE_ADDRESS_2:
  77. case PCI_BASE_ADDRESS_3:
  78. case PCI_BASE_ADDRESS_4:
  79. case PCI_BASE_ADDRESS_5: {
  80. int barnum;
  81. u32 *bar;
  82. barnum = pci_offset_to_barnum(offset);
  83. bar = &plat->bar[barnum];
  84. *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
  85. barinfo[barnum].size);
  86. break;
  87. }
  88. case PCI_CAPABILITY_LIST:
  89. *valuep = PCI_CAP_ID_PM_OFFSET;
  90. break;
  91. }
  92. return 0;
  93. }
  94. static int sandbox_p2sb_emul_write_config(struct udevice *emul, uint offset,
  95. ulong value, enum pci_size_t size)
  96. {
  97. struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
  98. switch (offset) {
  99. case PCI_COMMAND:
  100. plat->command = value;
  101. break;
  102. case PCI_BASE_ADDRESS_0:
  103. case PCI_BASE_ADDRESS_1: {
  104. int barnum;
  105. u32 *bar;
  106. barnum = pci_offset_to_barnum(offset);
  107. bar = &plat->bar[barnum];
  108. log_debug("w bar %d=%lx\n", barnum, value);
  109. *bar = value;
  110. /* space indicator (bit#0) is read-only */
  111. *bar |= barinfo[barnum].type;
  112. break;
  113. }
  114. }
  115. return 0;
  116. }
  117. static int sandbox_p2sb_emul_find_bar(struct udevice *emul, unsigned int addr,
  118. int *barnump, unsigned int *offsetp)
  119. {
  120. struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
  121. int barnum;
  122. for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
  123. unsigned int size = barinfo[barnum].size;
  124. u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
  125. if (addr >= base && addr < base + size) {
  126. *barnump = barnum;
  127. *offsetp = addr - base;
  128. return 0;
  129. }
  130. }
  131. *barnump = -1;
  132. return -ENOENT;
  133. }
  134. static int sandbox_p2sb_emul_read_io(struct udevice *dev, unsigned int addr,
  135. ulong *valuep, enum pci_size_t size)
  136. {
  137. unsigned int offset;
  138. int barnum;
  139. int ret;
  140. ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
  141. if (ret)
  142. return ret;
  143. if (barnum == 4)
  144. *valuep = offset;
  145. else if (barnum == 0)
  146. *valuep = offset;
  147. return 0;
  148. }
  149. static int sandbox_p2sb_emul_write_io(struct udevice *dev, unsigned int addr,
  150. ulong value, enum pci_size_t size)
  151. {
  152. unsigned int offset;
  153. int barnum;
  154. int ret;
  155. ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
  156. if (ret)
  157. return ret;
  158. return 0;
  159. }
  160. static int find_p2sb_channel(struct udevice *emul, uint offset,
  161. struct udevice **devp)
  162. {
  163. uint pid = offset >> PCR_PORTID_SHIFT;
  164. struct udevice *p2sb, *dev;
  165. int ret;
  166. ret = sandbox_pci_get_client(emul, &p2sb);
  167. if (ret)
  168. return log_msg_ret("No client", ret);
  169. device_foreach_child(dev, p2sb) {
  170. struct p2sb_child_platdata *pplat =
  171. dev_get_parent_platdata(dev);
  172. log_debug(" - child %s, pid %d, want %d\n", dev->name,
  173. pplat->pid, pid);
  174. if (pid == pplat->pid) {
  175. *devp = dev;
  176. return 0;
  177. }
  178. }
  179. return -ENOENT;
  180. }
  181. static int sandbox_p2sb_emul_map_physmem(struct udevice *dev,
  182. phys_addr_t addr, unsigned long *lenp,
  183. void **ptrp)
  184. {
  185. struct p2sb_emul_priv *priv = dev_get_priv(dev);
  186. struct udevice *child = NULL; /* Silence compiler warning */
  187. unsigned int offset;
  188. int barnum;
  189. int ret;
  190. log_debug("map %x: ", (uint)addr);
  191. ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset);
  192. if (ret)
  193. return log_msg_ret("Cannot find bar", ret);
  194. log_debug("bar %d, offset %x\n", barnum, offset);
  195. if (barnum != 0)
  196. return log_msg_ret("Unknown BAR", -EINVAL);
  197. ret = find_p2sb_channel(dev, offset, &child);
  198. if (ret)
  199. return log_msg_ret("Cannot find channel", ret);
  200. offset &= ((1 << PCR_PORTID_SHIFT) - 1);
  201. ret = axi_read(child, offset, priv->regs, AXI_SIZE_32);
  202. if (ret)
  203. return log_msg_ret("Child read failed", ret);
  204. *ptrp = priv->regs + (offset & 3);
  205. *lenp = 4;
  206. return 0;
  207. }
  208. static struct dm_pci_emul_ops sandbox_p2sb_emul_emul_ops = {
  209. .read_config = sandbox_p2sb_emul_read_config,
  210. .write_config = sandbox_p2sb_emul_write_config,
  211. .read_io = sandbox_p2sb_emul_read_io,
  212. .write_io = sandbox_p2sb_emul_write_io,
  213. .map_physmem = sandbox_p2sb_emul_map_physmem,
  214. };
  215. static const struct udevice_id sandbox_p2sb_emul_ids[] = {
  216. { .compatible = "sandbox,p2sb-emul" },
  217. { }
  218. };
  219. U_BOOT_DRIVER(sandbox_p2sb_emul_emul) = {
  220. .name = "sandbox_p2sb_emul_emul",
  221. .id = UCLASS_PCI_EMUL,
  222. .of_match = sandbox_p2sb_emul_ids,
  223. .ops = &sandbox_p2sb_emul_emul_ops,
  224. .priv_auto_alloc_size = sizeof(struct p2sb_emul_priv),
  225. .platdata_auto_alloc_size = sizeof(struct p2sb_emul_platdata),
  226. };
  227. static struct pci_device_id sandbox_p2sb_emul_supported[] = {
  228. { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) },
  229. {},
  230. };
  231. U_BOOT_PCI_DEVICE(sandbox_p2sb_emul_emul, sandbox_p2sb_emul_supported);