mxs_ocotp.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 OCOTP Driver
  4. *
  5. * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  6. *
  7. * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block
  8. * used in i.MX6 . While these blocks are very similar at the first
  9. * glance, by digging deeper, one will notice differences (like the
  10. * tight dependence on MXS power block, some completely new registers
  11. * etc.) which would make common driver an ifdef nightmare :-(
  12. */
  13. #include <common.h>
  14. #include <fuse.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/imx-regs.h>
  20. #include <asm/arch/sys_proto.h>
  21. #define MXS_OCOTP_TIMEOUT 100000
  22. static struct mxs_ocotp_regs *ocotp_regs =
  23. (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
  24. static struct mxs_power_regs *power_regs =
  25. (struct mxs_power_regs *)MXS_POWER_BASE;
  26. static struct mxs_clkctrl_regs *clkctrl_regs =
  27. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  28. static int mxs_ocotp_wait_busy_clear(void)
  29. {
  30. uint32_t reg;
  31. int timeout = MXS_OCOTP_TIMEOUT;
  32. while (--timeout) {
  33. reg = readl(&ocotp_regs->hw_ocotp_ctrl);
  34. if (!(reg & OCOTP_CTRL_BUSY))
  35. break;
  36. udelay(10);
  37. }
  38. if (!timeout)
  39. return -EINVAL;
  40. /* Wait a little as per FSL datasheet's 'write postamble' section. */
  41. udelay(10);
  42. return 0;
  43. }
  44. static void mxs_ocotp_clear_error(void)
  45. {
  46. writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr);
  47. }
  48. static int mxs_ocotp_read_bank_open(bool open)
  49. {
  50. int ret = 0;
  51. if (open) {
  52. writel(OCOTP_CTRL_RD_BANK_OPEN,
  53. &ocotp_regs->hw_ocotp_ctrl_set);
  54. /*
  55. * Wait before polling the BUSY bit, since the BUSY bit might
  56. * be asserted only after a few HCLK cycles and if we were to
  57. * poll immediatelly, we could miss the busy bit.
  58. */
  59. udelay(10);
  60. ret = mxs_ocotp_wait_busy_clear();
  61. } else {
  62. writel(OCOTP_CTRL_RD_BANK_OPEN,
  63. &ocotp_regs->hw_ocotp_ctrl_clr);
  64. }
  65. return ret;
  66. }
  67. static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val)
  68. {
  69. uint32_t scale_val;
  70. if (enter) {
  71. /*
  72. * Enter the fuse programming VDDIO voltage setup. We start
  73. * scaling the voltage from it's current value down to 2.8V
  74. * which is the one and only correct voltage for programming
  75. * the OCOTP fuses (according to datasheet).
  76. */
  77. scale_val = readl(&power_regs->hw_power_vddioctrl);
  78. scale_val &= POWER_VDDIOCTRL_TRG_MASK;
  79. /* Return the original voltage. */
  80. *val = scale_val;
  81. /*
  82. * Start scaling VDDIO down to 0x2, which is 2.8V . Actually,
  83. * the value 0x0 should be 2.8V, but that's not the case on
  84. * most designs due to load etc., so we play safe. Undervolt
  85. * can actually cause incorrect programming of the fuses and
  86. * or reboots of the board.
  87. */
  88. while (scale_val > 2) {
  89. clrsetbits_le32(&power_regs->hw_power_vddioctrl,
  90. POWER_VDDIOCTRL_TRG_MASK, --scale_val);
  91. udelay(500);
  92. }
  93. } else {
  94. /* Start scaling VDDIO up to original value . */
  95. for (scale_val = 2; scale_val <= *val; scale_val++) {
  96. clrsetbits_le32(&power_regs->hw_power_vddioctrl,
  97. POWER_VDDIOCTRL_TRG_MASK, scale_val);
  98. udelay(500);
  99. }
  100. }
  101. mdelay(10);
  102. }
  103. static int mxs_ocotp_wait_hclk_ready(void)
  104. {
  105. uint32_t reg, timeout = MXS_OCOTP_TIMEOUT;
  106. while (--timeout) {
  107. reg = readl(&clkctrl_regs->hw_clkctrl_hbus);
  108. if (!(reg & CLKCTRL_HBUS_ASM_BUSY))
  109. break;
  110. }
  111. if (!timeout)
  112. return -EINVAL;
  113. return 0;
  114. }
  115. static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
  116. {
  117. uint32_t scale_val;
  118. int ret;
  119. ret = mxs_ocotp_wait_hclk_ready();
  120. if (ret)
  121. return ret;
  122. /* Set CPU bypass */
  123. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  124. &clkctrl_regs->hw_clkctrl_clkseq_set);
  125. if (enter) {
  126. /* Return the original HCLK clock speed. */
  127. *val = readl(&clkctrl_regs->hw_clkctrl_hbus);
  128. *val &= CLKCTRL_HBUS_DIV_MASK;
  129. *val >>= CLKCTRL_HBUS_DIV_OFFSET;
  130. /* Scale the HCLK to 454/19 = 23.9 MHz . */
  131. scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
  132. scale_val &= CLKCTRL_HBUS_DIV_MASK;
  133. } else {
  134. /* Scale the HCLK back to original frequency. */
  135. scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET;
  136. scale_val &= CLKCTRL_HBUS_DIV_MASK;
  137. }
  138. writel(CLKCTRL_HBUS_DIV_MASK,
  139. &clkctrl_regs->hw_clkctrl_hbus_set);
  140. writel(scale_val,
  141. &clkctrl_regs->hw_clkctrl_hbus_clr);
  142. mdelay(10);
  143. ret = mxs_ocotp_wait_hclk_ready();
  144. if (ret)
  145. return ret;
  146. /* Disable CPU bypass */
  147. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  148. &clkctrl_regs->hw_clkctrl_clkseq_clr);
  149. mdelay(10);
  150. return 0;
  151. }
  152. static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
  153. {
  154. uint32_t hclk_val, vddio_val;
  155. int ret;
  156. mxs_ocotp_clear_error();
  157. /* Make sure the banks are closed for reading. */
  158. ret = mxs_ocotp_read_bank_open(0);
  159. if (ret) {
  160. puts("Failed closing banks for reading!\n");
  161. return ret;
  162. }
  163. ret = mxs_ocotp_scale_hclk(1, &hclk_val);
  164. if (ret) {
  165. puts("Failed scaling down the HCLK!\n");
  166. return ret;
  167. }
  168. mxs_ocotp_scale_vddio(1, &vddio_val);
  169. ret = mxs_ocotp_wait_busy_clear();
  170. if (ret) {
  171. puts("Failed waiting for ready state!\n");
  172. goto fail;
  173. }
  174. /* Program the fuse address */
  175. writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl);
  176. /* Program the data. */
  177. writel(mask, &ocotp_regs->hw_ocotp_data);
  178. udelay(10);
  179. ret = mxs_ocotp_wait_busy_clear();
  180. if (ret) {
  181. puts("Failed waiting for ready state!\n");
  182. goto fail;
  183. }
  184. /* Check for errors */
  185. if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) {
  186. puts("Failed writing fuses!\n");
  187. ret = -EPERM;
  188. goto fail;
  189. }
  190. fail:
  191. mxs_ocotp_scale_vddio(0, &vddio_val);
  192. if (mxs_ocotp_scale_hclk(0, &hclk_val))
  193. puts("Failed scaling up the HCLK!\n");
  194. return ret;
  195. }
  196. static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val)
  197. {
  198. int ret;
  199. /* Register offset from CUST0 */
  200. reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4);
  201. ret = mxs_ocotp_wait_busy_clear();
  202. if (ret) {
  203. puts("Failed waiting for ready state!\n");
  204. return ret;
  205. }
  206. mxs_ocotp_clear_error();
  207. ret = mxs_ocotp_read_bank_open(1);
  208. if (ret) {
  209. puts("Failed opening banks for reading!\n");
  210. return ret;
  211. }
  212. *val = readl(reg);
  213. ret = mxs_ocotp_read_bank_open(0);
  214. if (ret) {
  215. puts("Failed closing banks for reading!\n");
  216. return ret;
  217. }
  218. return ret;
  219. }
  220. static int mxs_ocotp_valid(u32 bank, u32 word)
  221. {
  222. if (bank > 4)
  223. return -EINVAL;
  224. if (word > 7)
  225. return -EINVAL;
  226. return 0;
  227. }
  228. /*
  229. * The 'fuse' command API
  230. */
  231. int fuse_read(u32 bank, u32 word, u32 *val)
  232. {
  233. int ret;
  234. ret = mxs_ocotp_valid(bank, word);
  235. if (ret)
  236. return ret;
  237. return mxs_ocotp_read_fuse((bank << 3) | word, val);
  238. }
  239. int fuse_prog(u32 bank, u32 word, u32 val)
  240. {
  241. int ret;
  242. ret = mxs_ocotp_valid(bank, word);
  243. if (ret)
  244. return ret;
  245. return mxs_ocotp_write_fuse((bank << 3) | word, val);
  246. }
  247. int fuse_sense(u32 bank, u32 word, u32 *val)
  248. {
  249. /* We do not support sensing :-( */
  250. return -EINVAL;
  251. }
  252. int fuse_override(u32 bank, u32 word, u32 val)
  253. {
  254. /* We do not support overriding :-( */
  255. return -EINVAL;
  256. }