mxc_ocotp.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 ADVANSEE
  4. * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
  5. *
  6. * Based on Dirk Behme's
  7. * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
  8. * which is based on Freescale's
  9. * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
  10. * which is:
  11. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  12. */
  13. #include <common.h>
  14. #include <fuse.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/imx-regs.h>
  20. #include <asm/mach-imx/sys_proto.h>
  21. #define BO_CTRL_WR_UNLOCK 16
  22. #define BM_CTRL_WR_UNLOCK 0xffff0000
  23. #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
  24. #define BM_CTRL_ERROR 0x00000200
  25. #define BM_CTRL_BUSY 0x00000100
  26. #define BO_CTRL_ADDR 0
  27. #ifdef CONFIG_MX7
  28. #define BM_CTRL_ADDR 0x0000000f
  29. #define BM_CTRL_RELOAD 0x00000400
  30. #elif defined(CONFIG_MX7ULP)
  31. #define BM_CTRL_ADDR 0x000000FF
  32. #define BM_CTRL_RELOAD 0x00000400
  33. #define BM_OUT_STATUS_DED 0x00000400
  34. #define BM_OUT_STATUS_LOCKED 0x00000800
  35. #define BM_OUT_STATUS_PROGFAIL 0x00001000
  36. #elif defined(CONFIG_IMX8M)
  37. #ifdef CONFIG_IMX8MP
  38. #undef BM_CTRL_ADDR
  39. #undef BM_CTRL_ERROR
  40. #undef BM_CTRL_BUSY
  41. #define BM_CTRL_ADDR 0x000001ff
  42. #define BM_CTRL_ERROR 0x00000400
  43. #define BM_CTRL_BUSY 0x00000200
  44. #else
  45. #define BM_CTRL_ADDR 0x000000ff
  46. #endif
  47. #else
  48. #define BM_CTRL_ADDR 0x0000007f
  49. #endif
  50. #ifdef CONFIG_MX7
  51. #define BO_TIMING_FSOURCE 12
  52. #define BM_TIMING_FSOURCE 0x0007f000
  53. #define BV_TIMING_FSOURCE_NS 1001
  54. #define BO_TIMING_PROG 0
  55. #define BM_TIMING_PROG 0x00000fff
  56. #define BV_TIMING_PROG_US 10
  57. #else
  58. #define BO_TIMING_STROBE_READ 16
  59. #define BM_TIMING_STROBE_READ 0x003f0000
  60. #define BV_TIMING_STROBE_READ_NS 37
  61. #define BO_TIMING_RELAX 12
  62. #define BM_TIMING_RELAX 0x0000f000
  63. #define BV_TIMING_RELAX_NS 17
  64. #define BO_TIMING_STROBE_PROG 0
  65. #define BM_TIMING_STROBE_PROG 0x00000fff
  66. #define BV_TIMING_STROBE_PROG_US 10
  67. #endif
  68. #define BM_READ_CTRL_READ_FUSE 0x00000001
  69. #define BF(value, field) (((value) << BO_##field) & BM_##field)
  70. #define WRITE_POSTAMBLE_US 2
  71. #if defined(CONFIG_MX6) || defined(CONFIG_VF610)
  72. #define FUSE_BANK_SIZE 0x80
  73. #ifdef CONFIG_MX6SL
  74. #define FUSE_BANKS 8
  75. #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
  76. #define FUSE_BANKS 9
  77. #else
  78. #define FUSE_BANKS 16
  79. #endif
  80. #elif defined CONFIG_MX7
  81. #define FUSE_BANK_SIZE 0x40
  82. #define FUSE_BANKS 16
  83. #elif defined(CONFIG_MX7ULP)
  84. #define FUSE_BANK_SIZE 0x80
  85. #define FUSE_BANKS 31
  86. #elif defined(CONFIG_IMX8M)
  87. #define FUSE_BANK_SIZE 0x40
  88. #ifdef CONFIG_IMX8MP
  89. #define FUSE_BANKS 96
  90. #else
  91. #define FUSE_BANKS 64
  92. #endif
  93. #else
  94. #error "Unsupported architecture\n"
  95. #endif
  96. #if defined(CONFIG_MX6)
  97. /*
  98. * There is a hole in shadow registers address map of size 0x100
  99. * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
  100. * iMX6UL, i.MX6ULL and i.MX6SLL.
  101. * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
  102. * we should account for this hole in address space.
  103. *
  104. * Similar hole exists between bank 14 and bank 15 of size
  105. * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
  106. * Note: iMX6SL has only 0-7 banks and there is no hole.
  107. * Note: iMX6UL doesn't have this one.
  108. *
  109. * This function is to covert user input to physical bank index.
  110. * Only needed when read fuse, because we use register offset, so
  111. * need to calculate real register offset.
  112. * When write, no need to consider hole, always use the bank/word
  113. * index from fuse map.
  114. */
  115. u32 fuse_bank_physical(int index)
  116. {
  117. u32 phy_index;
  118. if (is_mx6sl() || is_mx7ulp()) {
  119. phy_index = index;
  120. } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
  121. if ((is_mx6ull() || is_mx6sll()) && index == 8)
  122. index = 7;
  123. if (index >= 6)
  124. phy_index = fuse_bank_physical(5) + (index - 6) + 3;
  125. else
  126. phy_index = index;
  127. } else {
  128. if (index >= 15)
  129. phy_index = fuse_bank_physical(14) + (index - 15) + 2;
  130. else if (index >= 6)
  131. phy_index = fuse_bank_physical(5) + (index - 6) + 3;
  132. else
  133. phy_index = index;
  134. }
  135. return phy_index;
  136. }
  137. u32 fuse_word_physical(u32 bank, u32 word_index)
  138. {
  139. if (is_mx6ull() || is_mx6sll()) {
  140. if (bank == 8)
  141. word_index = word_index + 4;
  142. }
  143. return word_index;
  144. }
  145. #else
  146. u32 fuse_bank_physical(int index)
  147. {
  148. return index;
  149. }
  150. u32 fuse_word_physical(u32 bank, u32 word_index)
  151. {
  152. return word_index;
  153. }
  154. #endif
  155. static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
  156. {
  157. while (readl(&regs->ctrl) & BM_CTRL_BUSY)
  158. udelay(delay_us);
  159. }
  160. static void clear_error(struct ocotp_regs *regs)
  161. {
  162. writel(BM_CTRL_ERROR, &regs->ctrl_clr);
  163. }
  164. static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
  165. int assert, const char *caller)
  166. {
  167. *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  168. if (bank >= FUSE_BANKS ||
  169. word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
  170. !assert) {
  171. printf("mxc_ocotp %s(): Invalid argument\n", caller);
  172. return -EINVAL;
  173. }
  174. if (is_mx6ull() || is_mx6sll()) {
  175. if ((bank == 7 || bank == 8) &&
  176. word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
  177. printf("mxc_ocotp %s(): Invalid argument\n", caller);
  178. return -EINVAL;
  179. }
  180. }
  181. enable_ocotp_clk(1);
  182. wait_busy(*regs, 1);
  183. clear_error(*regs);
  184. return 0;
  185. }
  186. static int finish_access(struct ocotp_regs *regs, const char *caller)
  187. {
  188. u32 err;
  189. err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
  190. clear_error(regs);
  191. #ifdef CONFIG_MX7ULP
  192. /* Need to power down the OTP memory */
  193. writel(1, &regs->pdn);
  194. #endif
  195. if (err) {
  196. printf("mxc_ocotp %s(): Access protect error\n", caller);
  197. return -EIO;
  198. }
  199. return 0;
  200. }
  201. static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
  202. const char *caller)
  203. {
  204. return prepare_access(regs, bank, word, val != NULL, caller);
  205. }
  206. int fuse_read(u32 bank, u32 word, u32 *val)
  207. {
  208. struct ocotp_regs *regs;
  209. int ret;
  210. u32 phy_bank;
  211. u32 phy_word;
  212. ret = prepare_read(&regs, bank, word, val, __func__);
  213. if (ret)
  214. return ret;
  215. phy_bank = fuse_bank_physical(bank);
  216. phy_word = fuse_word_physical(bank, word);
  217. *val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);
  218. #ifdef CONFIG_MX7ULP
  219. if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
  220. writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
  221. printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
  222. return -EIO;
  223. }
  224. #endif
  225. return finish_access(regs, __func__);
  226. }
  227. #ifdef CONFIG_MX7
  228. static void set_timing(struct ocotp_regs *regs)
  229. {
  230. u32 ipg_clk;
  231. u32 fsource, prog;
  232. u32 timing;
  233. ipg_clk = mxc_get_clock(MXC_IPG_CLK);
  234. fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
  235. + 1000000) + 1;
  236. prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
  237. timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
  238. clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
  239. timing);
  240. }
  241. #elif defined(CONFIG_MX7ULP)
  242. static void set_timing(struct ocotp_regs *regs)
  243. {
  244. /* No timing set for MX7ULP */
  245. }
  246. #else
  247. static void set_timing(struct ocotp_regs *regs)
  248. {
  249. u32 ipg_clk;
  250. u32 relax, strobe_read, strobe_prog;
  251. u32 timing;
  252. ipg_clk = mxc_get_clock(MXC_IPG_CLK);
  253. relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
  254. strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
  255. 1000000000) + 2 * (relax + 1) - 1;
  256. strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
  257. 1000000) + 2 * (relax + 1) - 1;
  258. timing = BF(strobe_read, TIMING_STROBE_READ) |
  259. BF(relax, TIMING_RELAX) |
  260. BF(strobe_prog, TIMING_STROBE_PROG);
  261. clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
  262. BM_TIMING_STROBE_PROG, timing);
  263. }
  264. #endif
  265. static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
  266. int write)
  267. {
  268. u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
  269. #ifdef CONFIG_MX7
  270. u32 addr = bank;
  271. #elif defined CONFIG_IMX8M
  272. u32 addr = bank << 2 | word;
  273. #else
  274. u32 addr;
  275. /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
  276. if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
  277. bank = bank - 1;
  278. word += 4;
  279. }
  280. addr = bank << 3 | word;
  281. #endif
  282. set_timing(regs);
  283. clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
  284. BF(wr_unlock, CTRL_WR_UNLOCK) |
  285. BF(addr, CTRL_ADDR));
  286. }
  287. int fuse_sense(u32 bank, u32 word, u32 *val)
  288. {
  289. struct ocotp_regs *regs;
  290. int ret;
  291. if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) {
  292. printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
  293. return -EPERM;
  294. }
  295. ret = prepare_read(&regs, bank, word, val, __func__);
  296. if (ret)
  297. return ret;
  298. setup_direct_access(regs, bank, word, false);
  299. writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
  300. wait_busy(regs, 1);
  301. #ifdef CONFIG_MX7
  302. *val = readl((&regs->read_fuse_data0) + (word << 2));
  303. #else
  304. *val = readl(&regs->read_fuse_data);
  305. #endif
  306. #ifdef CONFIG_MX7ULP
  307. if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
  308. writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
  309. printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
  310. return -EIO;
  311. }
  312. #endif
  313. return finish_access(regs, __func__);
  314. }
  315. static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
  316. const char *caller)
  317. {
  318. #ifdef CONFIG_MX7ULP
  319. u32 val;
  320. int ret;
  321. /* Only bank 0 and 1 are redundancy mode, others are ECC mode */
  322. if (bank != 0 && bank != 1) {
  323. if ((soc_rev() < CHIP_REV_2_0) ||
  324. ((soc_rev() >= CHIP_REV_2_0) &&
  325. bank != 9 && bank != 10 && bank != 28)) {
  326. ret = fuse_sense(bank, word, &val);
  327. if (ret)
  328. return ret;
  329. if (val != 0) {
  330. printf("mxc_ocotp: The word has been programmed, no more write\n");
  331. return -EPERM;
  332. }
  333. }
  334. }
  335. #endif
  336. return prepare_access(regs, bank, word, true, caller);
  337. }
  338. int fuse_prog(u32 bank, u32 word, u32 val)
  339. {
  340. struct ocotp_regs *regs;
  341. int ret;
  342. ret = prepare_write(&regs, bank, word, __func__);
  343. if (ret)
  344. return ret;
  345. setup_direct_access(regs, bank, word, true);
  346. #ifdef CONFIG_MX7
  347. switch (word) {
  348. case 0:
  349. writel(0, &regs->data1);
  350. writel(0, &regs->data2);
  351. writel(0, &regs->data3);
  352. writel(val, &regs->data0);
  353. break;
  354. case 1:
  355. writel(val, &regs->data1);
  356. writel(0, &regs->data2);
  357. writel(0, &regs->data3);
  358. writel(0, &regs->data0);
  359. break;
  360. case 2:
  361. writel(0, &regs->data1);
  362. writel(val, &regs->data2);
  363. writel(0, &regs->data3);
  364. writel(0, &regs->data0);
  365. break;
  366. case 3:
  367. writel(0, &regs->data1);
  368. writel(0, &regs->data2);
  369. writel(val, &regs->data3);
  370. writel(0, &regs->data0);
  371. break;
  372. }
  373. wait_busy(regs, BV_TIMING_PROG_US);
  374. #else
  375. writel(val, &regs->data);
  376. wait_busy(regs, BV_TIMING_STROBE_PROG_US);
  377. #endif
  378. udelay(WRITE_POSTAMBLE_US);
  379. #ifdef CONFIG_MX7ULP
  380. if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
  381. writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
  382. printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
  383. return -EIO;
  384. }
  385. #endif
  386. return finish_access(regs, __func__);
  387. }
  388. int fuse_override(u32 bank, u32 word, u32 val)
  389. {
  390. struct ocotp_regs *regs;
  391. int ret;
  392. u32 phy_bank;
  393. u32 phy_word;
  394. ret = prepare_write(&regs, bank, word, __func__);
  395. if (ret)
  396. return ret;
  397. phy_bank = fuse_bank_physical(bank);
  398. phy_word = fuse_word_physical(bank, word);
  399. writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);
  400. #ifdef CONFIG_MX7ULP
  401. if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
  402. writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
  403. printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
  404. return -EIO;
  405. }
  406. #endif
  407. return finish_access(regs, __func__);
  408. }