ihs_fpga.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. *
  6. * based on the ioep-fpga driver, which is
  7. *
  8. * (C) Copyright 2014
  9. * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <regmap.h>
  15. #include <asm/gpio.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include "ihs_fpga.h"
  19. /**
  20. * struct ihs_fpga_priv - Private data structure for IHS FPGA driver
  21. * @map: Register map for the FPGA's own register space
  22. * @reset_gpio: GPIO to start FPGA reconfiguration
  23. * @done_gpio: GPOI to read the 'ready' status of the FPGA
  24. */
  25. struct ihs_fpga_priv {
  26. struct regmap *map;
  27. struct gpio_desc reset_gpio;
  28. struct gpio_desc done_gpio;
  29. };
  30. /* Test pattern for reflection test */
  31. const u16 REFLECTION_TESTPATTERN = 0xdead;
  32. /* Delay (in ms) for each round in the reflection test */
  33. const uint REFLECTION_TEST_DELAY = 100;
  34. /* Maximum number of rounds in the reflection test */
  35. const uint REFLECTION_TEST_ROUNDS = 5;
  36. /* Delay (in ms) for each round waiting for the FPGA's done GPIO */
  37. const uint FPGA_DONE_WAIT_DELAY = 100;
  38. /* Maximum number of rounds for waiting for the FPGA's done GPIO */
  39. const uint FPGA_DONE_WAIT_ROUND = 5;
  40. /**
  41. * enum pcb_video_type - Video type of the PCB
  42. * @PCB_DVI_SL: Video type is DVI single-link
  43. * @PCB_DP_165MPIX: Video type is DisplayPort (165Mpix)
  44. * @PCB_DP_300MPIX: Video type is DisplayPort (300Mpix)
  45. * @PCB_HDMI: Video type is HDMI
  46. * @PCB_DP_1_2: Video type is DisplayPort 1.2
  47. * @PCB_HDMI_2_0: Video type is HDMI 2.0
  48. */
  49. enum pcb_video_type {
  50. PCB_DVI_SL,
  51. PCB_DP_165MPIX,
  52. PCB_DP_300MPIX,
  53. PCB_HDMI,
  54. PCB_DP_1_2,
  55. PCB_HDMI_2_0,
  56. };
  57. /**
  58. * enum pcb_transmission_type - Transmission type of the PCB
  59. * @PCB_CAT_1G: Transmission type is 1G Ethernet
  60. * @PCB_FIBER_3G: Transmission type is 3G Fiber
  61. * @PCB_CAT_10G: Transmission type is 10G Ethernet
  62. * @PCB_FIBER_10G: Transmission type is 10G Fiber
  63. */
  64. enum pcb_transmission_type {
  65. PCB_CAT_1G,
  66. PCB_FIBER_3G,
  67. PCB_CAT_10G,
  68. PCB_FIBER_10G,
  69. };
  70. /**
  71. * enum carrier_speed - Speed of the FPGA's carrier
  72. * @CARRIER_SPEED_1G: The carrier speed is 1G
  73. * @CARRIER_SPEED_2_5G: The carrier speed is 2.5G
  74. * @CARRIER_SPEED_3G: The carrier speed is 3G
  75. * @CARRIER_SPEED_10G: The carrier speed is 10G
  76. */
  77. enum carrier_speed {
  78. CARRIER_SPEED_1G,
  79. CARRIER_SPEED_3G,
  80. CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
  81. CARRIER_SPEED_10G,
  82. };
  83. /**
  84. * enum ram_config - FPGA's RAM configuration
  85. * @RAM_DDR2_32BIT_295MBPS: DDR2 32 bit at 295Mb/s
  86. * @RAM_DDR3_32BIT_590MBPS: DDR3 32 bit at 590Mb/s
  87. * @RAM_DDR3_48BIT_590MBPS: DDR3 48 bit at 590Mb/s
  88. * @RAM_DDR3_64BIT_1800MBPS: DDR3 64 bit at 1800Mb/s
  89. * @RAM_DDR3_48BIT_1800MBPS: DDR3 48 bit at 1800Mb/s
  90. */
  91. enum ram_config {
  92. RAM_DDR2_32BIT_295MBPS,
  93. RAM_DDR3_32BIT_590MBPS,
  94. RAM_DDR3_48BIT_590MBPS,
  95. RAM_DDR3_64BIT_1800MBPS,
  96. RAM_DDR3_48BIT_1800MBPS,
  97. };
  98. /**
  99. * enum sysclock - Speed of the FPGA's system clock
  100. * @SYSCLK_147456: System clock is 147.456 MHz
  101. */
  102. enum sysclock {
  103. SYSCLK_147456,
  104. };
  105. /**
  106. * struct fpga_versions - Data read from the versions register
  107. * @video_channel: Is the FPGA for a video channel (true) or main
  108. * channel (false) device?
  109. * @con_side: Is the FPGA for a CON (true) or a CPU (false) device?
  110. * @pcb_video_type: Defines for whch video type the FPGA is configured
  111. * @pcb_transmission_type: Defines for which transmission type the FPGA is
  112. * configured
  113. * @hw_version: Hardware version of the FPGA
  114. */
  115. struct fpga_versions {
  116. bool video_channel;
  117. bool con_side;
  118. enum pcb_video_type pcb_video_type;
  119. enum pcb_transmission_type pcb_transmission_type;
  120. unsigned int hw_version;
  121. };
  122. /**
  123. * struct fpga_features - Data read from the features register
  124. * @video_channels: Number of video channels supported
  125. * @carriers: Number of carrier channels supported
  126. * @carrier_speed: Speed of carriers
  127. * @ram_config: RAM configuration of FPGA
  128. * @sysclock: System clock speed of FPGA
  129. * @pcm_tx: Support for PCM transmission
  130. * @pcm_rx: Support for PCM reception
  131. * @spdif_tx: Support for SPDIF audio transmission
  132. * @spdif_rx: Support for SPDIF audio reception
  133. * @usb2: Support for transparent USB2.0
  134. * @rs232: Support for bidirectional RS232
  135. * @compression_type1: Support for compression type 1
  136. * @compression_type2: Support for compression type 2
  137. * @compression_type3: Support for compression type 3
  138. * @interlace: Support for interlace image formats
  139. * @osd: Support for a OSD
  140. * @compression_pipes: Number of compression pipes supported
  141. */
  142. struct fpga_features {
  143. u8 video_channels;
  144. u8 carriers;
  145. enum carrier_speed carrier_speed;
  146. enum ram_config ram_config;
  147. enum sysclock sysclock;
  148. bool pcm_tx;
  149. bool pcm_rx;
  150. bool spdif_tx;
  151. bool spdif_rx;
  152. bool usb2;
  153. bool rs232;
  154. bool compression_type1;
  155. bool compression_type2;
  156. bool compression_type3;
  157. bool interlace;
  158. bool osd;
  159. bool compression_pipes;
  160. };
  161. #ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
  162. /**
  163. * get_versions() - Fill structure with info from version register.
  164. * @dev: FPGA device to be queried for information
  165. * @versions: Pointer to the structure to fill with information from the
  166. * versions register
  167. * Return: 0
  168. */
  169. static int get_versions(struct udevice *dev, struct fpga_versions *versions)
  170. {
  171. struct ihs_fpga_priv *priv = dev_get_priv(dev);
  172. enum {
  173. VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
  174. VERSIONS_FPGA_CON_SIDE = BIT(13),
  175. VERSIONS_FPGA_SC = BIT(14),
  176. VERSIONS_PCB_CON = BIT(9),
  177. VERSIONS_PCB_SC = BIT(8),
  178. VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
  179. VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
  180. VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
  181. VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
  182. VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
  183. VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
  184. VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
  185. VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
  186. VERSIONS_HW_VER_MASK = 0xf << 0,
  187. };
  188. u16 raw_versions;
  189. memset(versions, 0, sizeof(struct fpga_versions));
  190. ihs_fpga_get(priv->map, versions, &raw_versions);
  191. versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
  192. versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
  193. switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
  194. case VERSIONS_PCB_VIDEO_DP_1_2:
  195. versions->pcb_video_type = PCB_DP_1_2;
  196. break;
  197. case VERSIONS_PCB_VIDEO_HDMI_2_0:
  198. versions->pcb_video_type = PCB_HDMI_2_0;
  199. break;
  200. }
  201. switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
  202. case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
  203. versions->pcb_transmission_type = PCB_FIBER_10G;
  204. break;
  205. case VERSIONS_PCB_TRANSMISSION_CAT_10G:
  206. versions->pcb_transmission_type = PCB_CAT_10G;
  207. break;
  208. case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
  209. versions->pcb_transmission_type = PCB_FIBER_3G;
  210. break;
  211. case VERSIONS_PCB_TRANSMISSION_CAT_1G:
  212. versions->pcb_transmission_type = PCB_CAT_1G;
  213. break;
  214. }
  215. versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
  216. return 0;
  217. }
  218. /**
  219. * get_features() - Fill structure with info from features register.
  220. * @dev: FPGA device to be queried for information
  221. * @features: Pointer to the structure to fill with information from the
  222. * features register
  223. * Return: 0
  224. */
  225. static int get_features(struct udevice *dev, struct fpga_features *features)
  226. {
  227. struct ihs_fpga_priv *priv = dev_get_priv(dev);
  228. enum {
  229. FEATURE_SPDIF_RX = BIT(15),
  230. FEATURE_SPDIF_TX = BIT(14),
  231. FEATURE_PCM_RX = BIT(13),
  232. FEATURE_PCM_TX = BIT(12),
  233. FEATURE_RAM_MASK = GENMASK(11, 8),
  234. FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
  235. FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
  236. FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
  237. FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
  238. FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
  239. FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
  240. FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
  241. FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
  242. FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
  243. FEATURE_CARRIERS_MASK = GENMASK(5, 4),
  244. FEATURE_CARRIERS_0 = 0x0 << 4,
  245. FEATURE_CARRIERS_1 = 0x1 << 4,
  246. FEATURE_CARRIERS_2 = 0x2 << 4,
  247. FEATURE_CARRIERS_4 = 0x3 << 4,
  248. FEATURE_USB2 = BIT(3),
  249. FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
  250. FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
  251. FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
  252. FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
  253. FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
  254. };
  255. enum {
  256. EXT_FEATURE_OSD = BIT(15),
  257. EXT_FEATURE_ETHERNET = BIT(9),
  258. EXT_FEATURE_INTERLACE = BIT(8),
  259. EXT_FEATURE_RS232 = BIT(7),
  260. EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
  261. EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
  262. EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
  263. EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
  264. EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
  265. EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
  266. EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
  267. };
  268. u16 raw_features;
  269. u16 raw_extended_features;
  270. memset(features, 0, sizeof(struct fpga_features));
  271. ihs_fpga_get(priv->map, features, &raw_features);
  272. ihs_fpga_get(priv->map, extended_features, &raw_extended_features);
  273. switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
  274. case FEATURE_VIDEOCHANNELS_0:
  275. features->video_channels = 0;
  276. break;
  277. case FEATURE_VIDEOCHANNELS_1:
  278. features->video_channels = 1;
  279. break;
  280. case FEATURE_VIDEOCHANNELS_1_1:
  281. case FEATURE_VIDEOCHANNELS_2:
  282. features->video_channels = 2;
  283. break;
  284. };
  285. switch (raw_features & FEATURE_CARRIERS_MASK) {
  286. case FEATURE_CARRIERS_0:
  287. features->carriers = 0;
  288. break;
  289. case FEATURE_CARRIERS_1:
  290. features->carriers = 1;
  291. break;
  292. case FEATURE_CARRIERS_2:
  293. features->carriers = 2;
  294. break;
  295. case FEATURE_CARRIERS_4:
  296. features->carriers = 4;
  297. break;
  298. }
  299. switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
  300. case FEATURE_CARRIER_SPEED_1G:
  301. features->carrier_speed = CARRIER_SPEED_1G;
  302. break;
  303. case FEATURE_CARRIER_SPEED_2_5G:
  304. features->carrier_speed = CARRIER_SPEED_2_5G;
  305. break;
  306. case FEATURE_CARRIER_SPEED_10G:
  307. features->carrier_speed = CARRIER_SPEED_10G;
  308. break;
  309. }
  310. switch (raw_features & FEATURE_RAM_MASK) {
  311. case FEATURE_RAM_DDR2_32BIT_295MBPS:
  312. features->ram_config = RAM_DDR2_32BIT_295MBPS;
  313. break;
  314. case FEATURE_RAM_DDR3_32BIT_590MBPS:
  315. features->ram_config = RAM_DDR3_32BIT_590MBPS;
  316. break;
  317. case FEATURE_RAM_DDR3_48BIT_590MBPS:
  318. features->ram_config = RAM_DDR3_48BIT_590MBPS;
  319. break;
  320. case FEATURE_RAM_DDR3_64BIT_1800MBPS:
  321. features->ram_config = RAM_DDR3_64BIT_1800MBPS;
  322. break;
  323. case FEATURE_RAM_DDR3_48BIT_1800MBPS:
  324. features->ram_config = RAM_DDR3_48BIT_1800MBPS;
  325. break;
  326. }
  327. features->pcm_tx = raw_features & FEATURE_PCM_TX;
  328. features->pcm_rx = raw_features & FEATURE_PCM_RX;
  329. features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
  330. features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
  331. features->usb2 = raw_features & FEATURE_USB2;
  332. features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
  333. features->compression_type1 = raw_extended_features &
  334. EXT_FEATURE_COMPRESSION_TYPE1;
  335. features->compression_type2 = raw_extended_features &
  336. EXT_FEATURE_COMPRESSION_TYPE2;
  337. features->compression_type3 = raw_extended_features &
  338. EXT_FEATURE_COMPRESSION_TYPE3;
  339. features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
  340. features->osd = raw_extended_features & EXT_FEATURE_OSD;
  341. features->compression_pipes = raw_extended_features &
  342. EXT_FEATURE_COMPRESSION_PERF_MASK;
  343. return 0;
  344. }
  345. #else
  346. /**
  347. * get_versions() - Fill structure with info from version register.
  348. * @fpga: Identifier of the FPGA device to be queried for information
  349. * @versions: Pointer to the structure to fill with information from the
  350. * versions register
  351. *
  352. * This is the legacy version and should be considered deprecated for new
  353. * devices.
  354. *
  355. * Return: 0
  356. */
  357. static int get_versions(unsigned int fpga, struct fpga_versions *versions)
  358. {
  359. enum {
  360. /* HW version encoding is a mess, leave it for the moment */
  361. VERSIONS_HW_VER_MASK = 0xf << 0,
  362. VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
  363. VERSIONS_SFP = BIT(5),
  364. VERSIONS_VIDEO_MASK = 0x7 << 6,
  365. VERSIONS_VIDEO_DVI = 0x0 << 6,
  366. VERSIONS_VIDEO_DP_165 = 0x1 << 6,
  367. VERSIONS_VIDEO_DP_300 = 0x2 << 6,
  368. VERSIONS_VIDEO_HDMI = 0x3 << 6,
  369. VERSIONS_UT_MASK = 0xf << 12,
  370. VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
  371. VERSIONS_UT_MAIN_USER = 0x1 << 12,
  372. VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
  373. VERSIONS_UT_VIDEO_USER = 0x3 << 12,
  374. };
  375. u16 raw_versions;
  376. memset(versions, 0, sizeof(struct fpga_versions));
  377. FPGA_GET_REG(fpga, versions, &raw_versions);
  378. switch (raw_versions & VERSIONS_UT_MASK) {
  379. case VERSIONS_UT_MAIN_SERVER:
  380. versions->video_channel = false;
  381. versions->con_side = false;
  382. break;
  383. case VERSIONS_UT_MAIN_USER:
  384. versions->video_channel = false;
  385. versions->con_side = true;
  386. break;
  387. case VERSIONS_UT_VIDEO_SERVER:
  388. versions->video_channel = true;
  389. versions->con_side = false;
  390. break;
  391. case VERSIONS_UT_VIDEO_USER:
  392. versions->video_channel = true;
  393. versions->con_side = true;
  394. break;
  395. }
  396. switch (raw_versions & VERSIONS_VIDEO_MASK) {
  397. case VERSIONS_VIDEO_DVI:
  398. versions->pcb_video_type = PCB_DVI_SL;
  399. break;
  400. case VERSIONS_VIDEO_DP_165:
  401. versions->pcb_video_type = PCB_DP_165MPIX;
  402. break;
  403. case VERSIONS_VIDEO_DP_300:
  404. versions->pcb_video_type = PCB_DP_300MPIX;
  405. break;
  406. case VERSIONS_VIDEO_HDMI:
  407. versions->pcb_video_type = PCB_HDMI;
  408. break;
  409. }
  410. versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
  411. if (raw_versions & VERSIONS_SFP)
  412. versions->pcb_transmission_type = PCB_FIBER_3G;
  413. else
  414. versions->pcb_transmission_type = PCB_CAT_1G;
  415. return 0;
  416. }
  417. /**
  418. * get_features() - Fill structure with info from features register.
  419. * @fpga: Identifier of the FPGA device to be queried for information
  420. * @features: Pointer to the structure to fill with information from the
  421. * features register
  422. *
  423. * This is the legacy version and should be considered deprecated for new
  424. * devices.
  425. *
  426. * Return: 0
  427. */
  428. static int get_features(unsigned int fpga, struct fpga_features *features)
  429. {
  430. enum {
  431. FEATURE_CARRIER_SPEED_2_5 = BIT(4),
  432. FEATURE_RAM_MASK = 0x7 << 5,
  433. FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
  434. FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
  435. FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
  436. FEATURE_PCM_AUDIO_TX = BIT(9),
  437. FEATURE_PCM_AUDIO_RX = BIT(10),
  438. FEATURE_OSD = BIT(11),
  439. FEATURE_USB20 = BIT(12),
  440. FEATURE_COMPRESSION_MASK = 7 << 13,
  441. FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
  442. FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
  443. FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
  444. };
  445. enum {
  446. EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
  447. EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
  448. EXTENDED_FEATURE_RS232 = BIT(2),
  449. EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
  450. EXTENDED_FEATURE_INTERLACE = BIT(4),
  451. };
  452. u16 raw_features;
  453. u16 raw_extended_features;
  454. memset(features, 0, sizeof(struct fpga_features));
  455. FPGA_GET_REG(fpga, fpga_features, &raw_features);
  456. FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
  457. features->video_channels = raw_features & 0x3;
  458. features->carriers = (raw_features >> 2) & 0x3;
  459. features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
  460. ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
  461. switch (raw_features & FEATURE_RAM_MASK) {
  462. case FEATURE_RAM_DDR2_32BIT:
  463. features->ram_config = RAM_DDR2_32BIT_295MBPS;
  464. break;
  465. case FEATURE_RAM_DDR3_32BIT:
  466. features->ram_config = RAM_DDR3_32BIT_590MBPS;
  467. break;
  468. case FEATURE_RAM_DDR3_48BIT:
  469. features->ram_config = RAM_DDR3_48BIT_590MBPS;
  470. break;
  471. }
  472. features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
  473. features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
  474. features->spdif_tx = raw_extended_features &
  475. EXTENDED_FEATURE_SPDIF_AUDIO_TX;
  476. features->spdif_rx = raw_extended_features &
  477. EXTENDED_FEATURE_SPDIF_AUDIO_RX;
  478. features->usb2 = raw_features & FEATURE_USB20;
  479. features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
  480. features->compression_type1 = false;
  481. features->compression_type2 = false;
  482. features->compression_type3 = false;
  483. switch (raw_features & FEATURE_COMPRESSION_MASK) {
  484. case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
  485. features->compression_type3 = true;
  486. /* fall-through */
  487. case FEATURE_COMPRESSION_TYPE1_TYPE2:
  488. features->compression_type2 = true;
  489. /* fall-through */
  490. case FEATURE_COMPRESSION_TYPE1:
  491. features->compression_type1 = true;
  492. break;
  493. }
  494. features->interlace = raw_extended_features &
  495. EXTENDED_FEATURE_INTERLACE;
  496. features->osd = raw_features & FEATURE_OSD;
  497. features->compression_pipes = raw_extended_features &
  498. EXTENDED_FEATURE_COMPRESSION_PIPES;
  499. return 0;
  500. }
  501. #endif
  502. /**
  503. * fpga_print_info() - Print information about FPGA device
  504. * @dev: FPGA device to print information about
  505. */
  506. static void fpga_print_info(struct udevice *dev)
  507. {
  508. struct ihs_fpga_priv *priv = dev_get_priv(dev);
  509. u16 fpga_version;
  510. struct fpga_versions versions;
  511. struct fpga_features features;
  512. ihs_fpga_get(priv->map, fpga_version, &fpga_version);
  513. get_versions(dev, &versions);
  514. get_features(dev, &features);
  515. if (versions.video_channel)
  516. printf("Videochannel");
  517. else
  518. printf("Mainchannel");
  519. if (versions.con_side)
  520. printf(" User");
  521. else
  522. printf(" Server");
  523. switch (versions.pcb_transmission_type) {
  524. case PCB_CAT_1G:
  525. case PCB_CAT_10G:
  526. printf(" CAT");
  527. break;
  528. case PCB_FIBER_3G:
  529. case PCB_FIBER_10G:
  530. printf(" Fiber");
  531. break;
  532. };
  533. switch (versions.pcb_video_type) {
  534. case PCB_DVI_SL:
  535. printf(" DVI,");
  536. break;
  537. case PCB_DP_165MPIX:
  538. printf(" DP 165MPix/s,");
  539. break;
  540. case PCB_DP_300MPIX:
  541. printf(" DP 300MPix/s,");
  542. break;
  543. case PCB_HDMI:
  544. printf(" HDMI,");
  545. break;
  546. case PCB_DP_1_2:
  547. printf(" DP 1.2,");
  548. break;
  549. case PCB_HDMI_2_0:
  550. printf(" HDMI 2.0,");
  551. break;
  552. }
  553. printf(" FPGA V %d.%02d\n features: ",
  554. fpga_version / 100, fpga_version % 100);
  555. if (!features.compression_type1 &&
  556. !features.compression_type2 &&
  557. !features.compression_type3)
  558. printf("no compression, ");
  559. if (features.compression_type1)
  560. printf("type1, ");
  561. if (features.compression_type2)
  562. printf("type2, ");
  563. if (features.compression_type3)
  564. printf("type3, ");
  565. printf("%sosd", features.osd ? "" : "no ");
  566. if (features.pcm_rx && features.pcm_tx)
  567. printf(", pcm rx+tx");
  568. else if (features.pcm_rx)
  569. printf(", pcm rx");
  570. else if (features.pcm_tx)
  571. printf(", pcm tx");
  572. if (features.spdif_rx && features.spdif_tx)
  573. printf(", spdif rx+tx");
  574. else if (features.spdif_rx)
  575. printf(", spdif rx");
  576. else if (features.spdif_tx)
  577. printf(", spdif tx");
  578. puts(",\n ");
  579. switch (features.sysclock) {
  580. case SYSCLK_147456:
  581. printf("clock 147.456 MHz");
  582. break;
  583. }
  584. switch (features.ram_config) {
  585. case RAM_DDR2_32BIT_295MBPS:
  586. printf(", RAM 32 bit DDR2");
  587. break;
  588. case RAM_DDR3_32BIT_590MBPS:
  589. printf(", RAM 32 bit DDR3");
  590. break;
  591. case RAM_DDR3_48BIT_590MBPS:
  592. case RAM_DDR3_48BIT_1800MBPS:
  593. printf(", RAM 48 bit DDR3");
  594. break;
  595. case RAM_DDR3_64BIT_1800MBPS:
  596. printf(", RAM 64 bit DDR3");
  597. break;
  598. }
  599. printf(", %d carrier(s)", features.carriers);
  600. switch (features.carrier_speed) {
  601. case CARRIER_SPEED_1G:
  602. printf(", 1Gbit/s");
  603. break;
  604. case CARRIER_SPEED_3G:
  605. printf(", 3Gbit/s");
  606. break;
  607. case CARRIER_SPEED_10G:
  608. printf(", 10Gbit/s");
  609. break;
  610. }
  611. printf(", %d video channel(s)\n", features.video_channels);
  612. }
  613. /**
  614. * do_reflection_test() - Run reflection test on a FPGA device
  615. * @dev: FPGA device to run reflection test on
  616. *
  617. * Return: 0 if reflection test succeeded, -ve on error
  618. */
  619. static int do_reflection_test(struct udevice *dev)
  620. {
  621. struct ihs_fpga_priv *priv = dev_get_priv(dev);
  622. int ctr = 0;
  623. while (1) {
  624. u16 val;
  625. ihs_fpga_set(priv->map, reflection_low, REFLECTION_TESTPATTERN);
  626. ihs_fpga_get(priv->map, reflection_low, &val);
  627. if (val == (~REFLECTION_TESTPATTERN & 0xffff))
  628. return -EIO;
  629. mdelay(REFLECTION_TEST_DELAY);
  630. if (ctr++ > REFLECTION_TEST_ROUNDS)
  631. return 0;
  632. }
  633. }
  634. /**
  635. * wait_for_fpga_done() - Wait until 'done'-flag is set for FPGA device
  636. * @dev: FPGA device whose done flag to wait for
  637. *
  638. * This function waits until it detects that the done-GPIO's value was changed
  639. * to 1 by the FPGA, which indicates that the device is configured and ready to
  640. * use.
  641. *
  642. * Return: 0 if done flag was detected, -ve on error
  643. */
  644. static int wait_for_fpga_done(struct udevice *dev)
  645. {
  646. struct ihs_fpga_priv *priv = dev_get_priv(dev);
  647. int ctr = 0;
  648. int done_val;
  649. while (1) {
  650. done_val = dm_gpio_get_value(&priv->done_gpio);
  651. if (done_val < 0) {
  652. debug("%s: Error while reading done-GPIO (err = %d)\n",
  653. dev->name, done_val);
  654. return done_val;
  655. }
  656. if (done_val)
  657. return 0;
  658. mdelay(FPGA_DONE_WAIT_DELAY);
  659. if (ctr++ > FPGA_DONE_WAIT_ROUND) {
  660. debug("%s: FPGA init failed (done not detected)\n",
  661. dev->name);
  662. return -EIO;
  663. }
  664. }
  665. }
  666. static int ihs_fpga_probe(struct udevice *dev)
  667. {
  668. struct ihs_fpga_priv *priv = dev_get_priv(dev);
  669. int ret;
  670. /* TODO(mario.six@gdsys.cc): Case of FPGA attached to MCLink bus */
  671. ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
  672. if (ret) {
  673. debug("%s: Could not initialize regmap (err = %d)",
  674. dev->name, ret);
  675. return ret;
  676. }
  677. ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
  678. GPIOD_IS_OUT);
  679. if (ret) {
  680. debug("%s: Could not get reset-GPIO (err = %d)\n",
  681. dev->name, ret);
  682. return ret;
  683. }
  684. if (!priv->reset_gpio.dev) {
  685. debug("%s: Could not get reset-GPIO\n", dev->name);
  686. return -ENOENT;
  687. }
  688. ret = gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio,
  689. GPIOD_IS_IN);
  690. if (ret) {
  691. debug("%s: Could not get done-GPIO (err = %d)\n",
  692. dev->name, ret);
  693. return ret;
  694. }
  695. if (!priv->done_gpio.dev) {
  696. debug("%s: Could not get done-GPIO\n", dev->name);
  697. return -ENOENT;
  698. }
  699. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  700. if (ret) {
  701. debug("%s: Error while setting reset-GPIO (err = %d)\n",
  702. dev->name, ret);
  703. return ret;
  704. }
  705. /* If FPGA already runs, don't initialize again */
  706. if (do_reflection_test(dev))
  707. goto reflection_ok;
  708. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  709. if (ret) {
  710. debug("%s: Error while setting reset-GPIO (err = %d)\n",
  711. dev->name, ret);
  712. return ret;
  713. }
  714. ret = wait_for_fpga_done(dev);
  715. if (ret) {
  716. debug("%s: Error while waiting for FPGA done (err = %d)\n",
  717. dev->name, ret);
  718. return ret;
  719. }
  720. udelay(10);
  721. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  722. if (ret) {
  723. debug("%s: Error while setting reset-GPIO (err = %d)\n",
  724. dev->name, ret);
  725. return ret;
  726. }
  727. if (!do_reflection_test(dev)) {
  728. debug("%s: Reflection test FAILED\n", dev->name);
  729. return -EIO;
  730. }
  731. reflection_ok:
  732. printf("%s: Reflection test passed.\n", dev->name);
  733. fpga_print_info(dev);
  734. return 0;
  735. }
  736. static const struct udevice_id ihs_fpga_ids[] = {
  737. { .compatible = "gdsys,iocon_fpga" },
  738. { .compatible = "gdsys,iocpu_fpga" },
  739. { }
  740. };
  741. U_BOOT_DRIVER(ihs_fpga_bus) = {
  742. .name = "ihs_fpga_bus",
  743. .id = UCLASS_MISC,
  744. .of_match = ihs_fpga_ids,
  745. .probe = ihs_fpga_probe,
  746. .priv_auto_alloc_size = sizeof(struct ihs_fpga_priv),
  747. };