tegra-hsp.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <malloc.h>
  8. #include <asm/io.h>
  9. #include <dm.h>
  10. #include <mailbox-uclass.h>
  11. #include <dt-bindings/mailbox/tegra186-hsp.h>
  12. #include <linux/bitops.h>
  13. #define TEGRA_HSP_INT_DIMENSIONING 0x380
  14. #define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT 16
  15. #define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK 0xf
  16. #define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT 12
  17. #define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK 0xf
  18. #define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT 8
  19. #define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK 0xf
  20. #define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT 4
  21. #define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK 0xf
  22. #define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT 0
  23. #define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK 0xf
  24. #define TEGRA_HSP_DB_REG_TRIGGER 0x0
  25. #define TEGRA_HSP_DB_REG_ENABLE 0x4
  26. #define TEGRA_HSP_DB_REG_RAW 0x8
  27. #define TEGRA_HSP_DB_REG_PENDING 0xc
  28. #define TEGRA_HSP_DB_ID_CCPLEX 1
  29. #define TEGRA_HSP_DB_ID_BPMP 3
  30. #define TEGRA_HSP_DB_ID_NUM 7
  31. struct tegra_hsp {
  32. fdt_addr_t regs;
  33. uint32_t db_base;
  34. };
  35. static uint32_t *tegra_hsp_reg(struct tegra_hsp *thsp, uint32_t db_id,
  36. uint32_t reg)
  37. {
  38. return (uint32_t *)(thsp->regs + thsp->db_base + (db_id * 0x100) + reg);
  39. }
  40. static uint32_t tegra_hsp_readl(struct tegra_hsp *thsp, uint32_t db_id,
  41. uint32_t reg)
  42. {
  43. uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
  44. return readl(r);
  45. }
  46. static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
  47. uint32_t db_id, uint32_t reg)
  48. {
  49. uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
  50. writel(val, r);
  51. readl(r);
  52. }
  53. static int tegra_hsp_db_id(ulong chan_id)
  54. {
  55. switch (chan_id) {
  56. case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP:
  57. return TEGRA_HSP_DB_ID_BPMP;
  58. default:
  59. debug("Invalid channel ID\n");
  60. return -EINVAL;
  61. }
  62. }
  63. static int tegra_hsp_of_xlate(struct mbox_chan *chan,
  64. struct ofnode_phandle_args *args)
  65. {
  66. debug("%s(chan=%p)\n", __func__, chan);
  67. if (args->args_count != 2) {
  68. debug("Invaild args_count: %d\n", args->args_count);
  69. return -EINVAL;
  70. }
  71. chan->id = (args->args[0] << 16) | args->args[1];
  72. return 0;
  73. }
  74. static int tegra_hsp_request(struct mbox_chan *chan)
  75. {
  76. int db_id;
  77. debug("%s(chan=%p)\n", __func__, chan);
  78. db_id = tegra_hsp_db_id(chan->id);
  79. if (db_id < 0) {
  80. debug("tegra_hsp_db_id() failed: %d\n", db_id);
  81. return -EINVAL;
  82. }
  83. return 0;
  84. }
  85. static int tegra_hsp_free(struct mbox_chan *chan)
  86. {
  87. debug("%s(chan=%p)\n", __func__, chan);
  88. return 0;
  89. }
  90. static int tegra_hsp_send(struct mbox_chan *chan, const void *data)
  91. {
  92. struct tegra_hsp *thsp = dev_get_priv(chan->dev);
  93. int db_id;
  94. debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
  95. db_id = tegra_hsp_db_id(chan->id);
  96. tegra_hsp_writel(thsp, 1, db_id, TEGRA_HSP_DB_REG_TRIGGER);
  97. return 0;
  98. }
  99. static int tegra_hsp_recv(struct mbox_chan *chan, void *data)
  100. {
  101. struct tegra_hsp *thsp = dev_get_priv(chan->dev);
  102. uint32_t db_id = TEGRA_HSP_DB_ID_CCPLEX;
  103. uint32_t val;
  104. debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
  105. val = tegra_hsp_readl(thsp, db_id, TEGRA_HSP_DB_REG_RAW);
  106. if (!(val & BIT(chan->id)))
  107. return -ENODATA;
  108. tegra_hsp_writel(thsp, BIT(chan->id), db_id, TEGRA_HSP_DB_REG_RAW);
  109. return 0;
  110. }
  111. static int tegra_hsp_bind(struct udevice *dev)
  112. {
  113. debug("%s(dev=%p)\n", __func__, dev);
  114. return 0;
  115. }
  116. static int tegra_hsp_probe(struct udevice *dev)
  117. {
  118. struct tegra_hsp *thsp = dev_get_priv(dev);
  119. u32 val;
  120. int nr_sm, nr_ss, nr_as;
  121. debug("%s(dev=%p)\n", __func__, dev);
  122. thsp->regs = dev_read_addr(dev);
  123. if (thsp->regs == FDT_ADDR_T_NONE)
  124. return -ENODEV;
  125. val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING);
  126. nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) &
  127. TEGRA_HSP_INT_DIMENSIONING_NSM_MASK;
  128. nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) &
  129. TEGRA_HSP_INT_DIMENSIONING_NSS_MASK;
  130. nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) &
  131. TEGRA_HSP_INT_DIMENSIONING_NAS_MASK;
  132. thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16;
  133. return 0;
  134. }
  135. static const struct udevice_id tegra_hsp_ids[] = {
  136. { .compatible = "nvidia,tegra186-hsp" },
  137. { }
  138. };
  139. struct mbox_ops tegra_hsp_mbox_ops = {
  140. .of_xlate = tegra_hsp_of_xlate,
  141. .request = tegra_hsp_request,
  142. .rfree = tegra_hsp_free,
  143. .send = tegra_hsp_send,
  144. .recv = tegra_hsp_recv,
  145. };
  146. U_BOOT_DRIVER(tegra_hsp) = {
  147. .name = "tegra-hsp",
  148. .id = UCLASS_MAILBOX,
  149. .of_match = tegra_hsp_ids,
  150. .bind = tegra_hsp_bind,
  151. .probe = tegra_hsp_probe,
  152. .priv_auto_alloc_size = sizeof(struct tegra_hsp),
  153. .ops = &tegra_hsp_mbox_ops,
  154. };