stm32f7_i2c.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017 STMicroelectronics
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <i2c.h>
  9. #include <log.h>
  10. #include <regmap.h>
  11. #include <reset.h>
  12. #include <syscon.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include <dm/device.h>
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. /* STM32 I2C registers */
  19. struct stm32_i2c_regs {
  20. u32 cr1; /* I2C control register 1 */
  21. u32 cr2; /* I2C control register 2 */
  22. u32 oar1; /* I2C own address 1 register */
  23. u32 oar2; /* I2C own address 2 register */
  24. u32 timingr; /* I2C timing register */
  25. u32 timeoutr; /* I2C timeout register */
  26. u32 isr; /* I2C interrupt and status register */
  27. u32 icr; /* I2C interrupt clear register */
  28. u32 pecr; /* I2C packet error checking register */
  29. u32 rxdr; /* I2C receive data register */
  30. u32 txdr; /* I2C transmit data register */
  31. };
  32. #define STM32_I2C_CR1 0x00
  33. #define STM32_I2C_CR2 0x04
  34. #define STM32_I2C_TIMINGR 0x10
  35. #define STM32_I2C_ISR 0x18
  36. #define STM32_I2C_ICR 0x1C
  37. #define STM32_I2C_RXDR 0x24
  38. #define STM32_I2C_TXDR 0x28
  39. /* STM32 I2C control 1 */
  40. #define STM32_I2C_CR1_ANFOFF BIT(12)
  41. #define STM32_I2C_CR1_ERRIE BIT(7)
  42. #define STM32_I2C_CR1_TCIE BIT(6)
  43. #define STM32_I2C_CR1_STOPIE BIT(5)
  44. #define STM32_I2C_CR1_NACKIE BIT(4)
  45. #define STM32_I2C_CR1_ADDRIE BIT(3)
  46. #define STM32_I2C_CR1_RXIE BIT(2)
  47. #define STM32_I2C_CR1_TXIE BIT(1)
  48. #define STM32_I2C_CR1_PE BIT(0)
  49. /* STM32 I2C control 2 */
  50. #define STM32_I2C_CR2_AUTOEND BIT(25)
  51. #define STM32_I2C_CR2_RELOAD BIT(24)
  52. #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
  53. #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
  54. #define STM32_I2C_CR2_NACK BIT(15)
  55. #define STM32_I2C_CR2_STOP BIT(14)
  56. #define STM32_I2C_CR2_START BIT(13)
  57. #define STM32_I2C_CR2_HEAD10R BIT(12)
  58. #define STM32_I2C_CR2_ADD10 BIT(11)
  59. #define STM32_I2C_CR2_RD_WRN BIT(10)
  60. #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
  61. #define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK)
  62. #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
  63. #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
  64. #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
  65. | STM32_I2C_CR2_NBYTES_MASK \
  66. | STM32_I2C_CR2_SADD7_MASK \
  67. | STM32_I2C_CR2_RELOAD \
  68. | STM32_I2C_CR2_RD_WRN)
  69. /* STM32 I2C Interrupt Status */
  70. #define STM32_I2C_ISR_BUSY BIT(15)
  71. #define STM32_I2C_ISR_ARLO BIT(9)
  72. #define STM32_I2C_ISR_BERR BIT(8)
  73. #define STM32_I2C_ISR_TCR BIT(7)
  74. #define STM32_I2C_ISR_TC BIT(6)
  75. #define STM32_I2C_ISR_STOPF BIT(5)
  76. #define STM32_I2C_ISR_NACKF BIT(4)
  77. #define STM32_I2C_ISR_ADDR BIT(3)
  78. #define STM32_I2C_ISR_RXNE BIT(2)
  79. #define STM32_I2C_ISR_TXIS BIT(1)
  80. #define STM32_I2C_ISR_TXE BIT(0)
  81. #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
  82. | STM32_I2C_ISR_ARLO)
  83. /* STM32 I2C Interrupt Clear */
  84. #define STM32_I2C_ICR_ARLOCF BIT(9)
  85. #define STM32_I2C_ICR_BERRCF BIT(8)
  86. #define STM32_I2C_ICR_STOPCF BIT(5)
  87. #define STM32_I2C_ICR_NACKCF BIT(4)
  88. /* STM32 I2C Timing */
  89. #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
  90. #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
  91. #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
  92. #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
  93. #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
  94. #define STM32_I2C_MAX_LEN 0xff
  95. #define STM32_I2C_DNF_DEFAULT 0
  96. #define STM32_I2C_DNF_MAX 16
  97. #define STM32_I2C_ANALOG_FILTER_ENABLE 1
  98. #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
  99. #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
  100. #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
  101. #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
  102. #define STM32_PRESC_MAX BIT(4)
  103. #define STM32_SCLDEL_MAX BIT(4)
  104. #define STM32_SDADEL_MAX BIT(4)
  105. #define STM32_SCLH_MAX BIT(8)
  106. #define STM32_SCLL_MAX BIT(8)
  107. #define STM32_NSEC_PER_SEC 1000000000L
  108. /**
  109. * struct stm32_i2c_spec - private i2c specification timing
  110. * @rate: I2C bus speed (Hz)
  111. * @rate_min: 80% of I2C bus speed (Hz)
  112. * @rate_max: 120% of I2C bus speed (Hz)
  113. * @fall_max: Max fall time of both SDA and SCL signals (ns)
  114. * @rise_max: Max rise time of both SDA and SCL signals (ns)
  115. * @hddat_min: Min data hold time (ns)
  116. * @vddat_max: Max data valid time (ns)
  117. * @sudat_min: Min data setup time (ns)
  118. * @l_min: Min low period of the SCL clock (ns)
  119. * @h_min: Min high period of the SCL clock (ns)
  120. */
  121. struct stm32_i2c_spec {
  122. u32 rate;
  123. u32 rate_min;
  124. u32 rate_max;
  125. u32 fall_max;
  126. u32 rise_max;
  127. u32 hddat_min;
  128. u32 vddat_max;
  129. u32 sudat_min;
  130. u32 l_min;
  131. u32 h_min;
  132. };
  133. /**
  134. * struct stm32_i2c_setup - private I2C timing setup parameters
  135. * @speed_freq: I2C speed frequency (Hz)
  136. * @clock_src: I2C clock source frequency (Hz)
  137. * @rise_time: Rise time (ns)
  138. * @fall_time: Fall time (ns)
  139. * @dnf: Digital filter coefficient (0-16)
  140. * @analog_filter: Analog filter delay (On/Off)
  141. * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
  142. */
  143. struct stm32_i2c_setup {
  144. u32 speed_freq;
  145. u32 clock_src;
  146. u32 rise_time;
  147. u32 fall_time;
  148. u8 dnf;
  149. bool analog_filter;
  150. u32 fmp_clr_offset;
  151. };
  152. /**
  153. * struct stm32_i2c_timings - private I2C output parameters
  154. * @prec: Prescaler value
  155. * @scldel: Data setup time
  156. * @sdadel: Data hold time
  157. * @sclh: SCL high period (master mode)
  158. * @sclh: SCL low period (master mode)
  159. */
  160. struct stm32_i2c_timings {
  161. struct list_head node;
  162. u8 presc;
  163. u8 scldel;
  164. u8 sdadel;
  165. u8 sclh;
  166. u8 scll;
  167. };
  168. /**
  169. * struct stm32_i2c_priv - private data of the controller
  170. * @regs: I2C registers address
  171. * @clk: hw i2c clock
  172. * @setup: I2C timing setup parameters
  173. * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
  174. * @regmap: holds SYSCFG phandle for Fast Mode Plus bit
  175. * @regmap_sreg: register address for setting Fast Mode Plus bits
  176. * @regmap_creg: register address for clearing Fast Mode Plus bits
  177. * @regmap_mask: mask for Fast Mode Plus bits
  178. */
  179. struct stm32_i2c_priv {
  180. struct stm32_i2c_regs *regs;
  181. struct clk clk;
  182. struct stm32_i2c_setup *setup;
  183. u32 speed;
  184. struct regmap *regmap;
  185. u32 regmap_sreg;
  186. u32 regmap_creg;
  187. u32 regmap_mask;
  188. };
  189. static const struct stm32_i2c_spec i2c_specs[] = {
  190. /* Standard speed - 100 KHz */
  191. [IC_SPEED_MODE_STANDARD] = {
  192. .rate = I2C_SPEED_STANDARD_RATE,
  193. .rate_min = 8000,
  194. .rate_max = 120000,
  195. .fall_max = 300,
  196. .rise_max = 1000,
  197. .hddat_min = 0,
  198. .vddat_max = 3450,
  199. .sudat_min = 250,
  200. .l_min = 4700,
  201. .h_min = 4000,
  202. },
  203. /* Fast speed - 400 KHz */
  204. [IC_SPEED_MODE_FAST] = {
  205. .rate = I2C_SPEED_FAST_RATE,
  206. .rate_min = 320000,
  207. .rate_max = 480000,
  208. .fall_max = 300,
  209. .rise_max = 300,
  210. .hddat_min = 0,
  211. .vddat_max = 900,
  212. .sudat_min = 100,
  213. .l_min = 1300,
  214. .h_min = 600,
  215. },
  216. /* Fast Plus Speed - 1 MHz */
  217. [IC_SPEED_MODE_FAST_PLUS] = {
  218. .rate = I2C_SPEED_FAST_PLUS_RATE,
  219. .rate_min = 800000,
  220. .rate_max = 1200000,
  221. .fall_max = 100,
  222. .rise_max = 120,
  223. .hddat_min = 0,
  224. .vddat_max = 450,
  225. .sudat_min = 50,
  226. .l_min = 500,
  227. .h_min = 260,
  228. },
  229. };
  230. static const struct stm32_i2c_setup stm32f7_setup = {
  231. .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
  232. .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
  233. .dnf = STM32_I2C_DNF_DEFAULT,
  234. .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
  235. };
  236. static const struct stm32_i2c_setup stm32mp15_setup = {
  237. .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
  238. .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
  239. .dnf = STM32_I2C_DNF_DEFAULT,
  240. .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
  241. .fmp_clr_offset = 0x40,
  242. };
  243. static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
  244. {
  245. struct stm32_i2c_regs *regs = i2c_priv->regs;
  246. u32 status = readl(&regs->isr);
  247. if (status & STM32_I2C_ISR_BUSY)
  248. return -EBUSY;
  249. return 0;
  250. }
  251. static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
  252. struct i2c_msg *msg, bool stop)
  253. {
  254. struct stm32_i2c_regs *regs = i2c_priv->regs;
  255. u32 cr2 = readl(&regs->cr2);
  256. /* Set transfer direction */
  257. cr2 &= ~STM32_I2C_CR2_RD_WRN;
  258. if (msg->flags & I2C_M_RD)
  259. cr2 |= STM32_I2C_CR2_RD_WRN;
  260. /* Set slave address */
  261. cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
  262. if (msg->flags & I2C_M_TEN) {
  263. cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
  264. cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
  265. cr2 |= STM32_I2C_CR2_ADD10;
  266. } else {
  267. cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
  268. cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
  269. }
  270. /* Set nb bytes to transfer and reload or autoend bits */
  271. cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
  272. STM32_I2C_CR2_AUTOEND);
  273. if (msg->len > STM32_I2C_MAX_LEN) {
  274. cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
  275. cr2 |= STM32_I2C_CR2_RELOAD;
  276. } else {
  277. cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
  278. }
  279. /* Write configurations register */
  280. writel(cr2, &regs->cr2);
  281. /* START/ReSTART generation */
  282. setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
  283. }
  284. /*
  285. * RELOAD mode must be selected if total number of data bytes to be
  286. * sent is greater than MAX_LEN
  287. */
  288. static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
  289. struct i2c_msg *msg, bool stop)
  290. {
  291. struct stm32_i2c_regs *regs = i2c_priv->regs;
  292. u32 cr2 = readl(&regs->cr2);
  293. cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
  294. if (msg->len > STM32_I2C_MAX_LEN) {
  295. cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
  296. } else {
  297. cr2 &= ~STM32_I2C_CR2_RELOAD;
  298. cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
  299. }
  300. writel(cr2, &regs->cr2);
  301. }
  302. static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
  303. u32 flags, u32 *status)
  304. {
  305. struct stm32_i2c_regs *regs = i2c_priv->regs;
  306. u32 time_start = get_timer(0);
  307. *status = readl(&regs->isr);
  308. while (!(*status & flags)) {
  309. if (get_timer(time_start) > CONFIG_SYS_HZ) {
  310. debug("%s: i2c timeout\n", __func__);
  311. return -ETIMEDOUT;
  312. }
  313. *status = readl(&regs->isr);
  314. }
  315. return 0;
  316. }
  317. static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
  318. {
  319. struct stm32_i2c_regs *regs = i2c_priv->regs;
  320. u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
  321. STM32_I2C_ISR_STOPF;
  322. u32 status;
  323. int ret;
  324. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  325. if (ret)
  326. return ret;
  327. if (status & STM32_I2C_ISR_BERR) {
  328. debug("%s: Bus error\n", __func__);
  329. /* Clear BERR flag */
  330. setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
  331. return -EIO;
  332. }
  333. if (status & STM32_I2C_ISR_ARLO) {
  334. debug("%s: Arbitration lost\n", __func__);
  335. /* Clear ARLO flag */
  336. setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
  337. return -EAGAIN;
  338. }
  339. if (status & STM32_I2C_ISR_NACKF) {
  340. debug("%s: Receive NACK\n", __func__);
  341. /* Clear NACK flag */
  342. setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
  343. /* Wait until STOPF flag is set */
  344. mask = STM32_I2C_ISR_STOPF;
  345. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  346. if (ret)
  347. return ret;
  348. ret = -EIO;
  349. }
  350. if (status & STM32_I2C_ISR_STOPF) {
  351. /* Clear STOP flag */
  352. setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
  353. /* Clear control register 2 */
  354. setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
  355. }
  356. return ret;
  357. }
  358. static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
  359. struct i2c_msg *msg, bool stop)
  360. {
  361. struct stm32_i2c_regs *regs = i2c_priv->regs;
  362. u32 status;
  363. u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
  364. STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
  365. int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
  366. STM32_I2C_MAX_LEN : msg->len;
  367. int ret = 0;
  368. /* Add errors */
  369. mask |= STM32_I2C_ISR_ERRORS;
  370. stm32_i2c_message_start(i2c_priv, msg, stop);
  371. while (msg->len) {
  372. /*
  373. * Wait until TXIS/NACKF/BERR/ARLO flags or
  374. * RXNE/BERR/ARLO flags are set
  375. */
  376. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  377. if (ret)
  378. break;
  379. if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
  380. break;
  381. if (status & STM32_I2C_ISR_RXNE) {
  382. *msg->buf++ = readb(&regs->rxdr);
  383. msg->len--;
  384. bytes_to_rw--;
  385. }
  386. if (status & STM32_I2C_ISR_TXIS) {
  387. writeb(*msg->buf++, &regs->txdr);
  388. msg->len--;
  389. bytes_to_rw--;
  390. }
  391. if (!bytes_to_rw && msg->len) {
  392. /* Wait until TCR flag is set */
  393. mask = STM32_I2C_ISR_TCR;
  394. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  395. if (ret)
  396. break;
  397. bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
  398. STM32_I2C_MAX_LEN : msg->len;
  399. mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
  400. STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
  401. stm32_i2c_handle_reload(i2c_priv, msg, stop);
  402. } else if (!bytes_to_rw) {
  403. /* Wait until TC flag is set */
  404. mask = STM32_I2C_ISR_TC;
  405. ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
  406. if (ret)
  407. break;
  408. if (!stop)
  409. /* Message sent, new message has to be sent */
  410. return 0;
  411. }
  412. }
  413. /* End of transfer, send stop condition */
  414. mask = STM32_I2C_CR2_STOP;
  415. setbits_le32(&regs->cr2, mask);
  416. return stm32_i2c_check_end_of_message(i2c_priv);
  417. }
  418. static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  419. int nmsgs)
  420. {
  421. struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
  422. int ret;
  423. ret = stm32_i2c_check_device_busy(i2c_priv);
  424. if (ret)
  425. return ret;
  426. for (; nmsgs > 0; nmsgs--, msg++) {
  427. ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
  428. if (ret)
  429. return ret;
  430. }
  431. return 0;
  432. }
  433. static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
  434. const struct stm32_i2c_spec *specs,
  435. struct list_head *solutions)
  436. {
  437. struct stm32_i2c_timings *v;
  438. u32 p_prev = STM32_PRESC_MAX;
  439. u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
  440. setup->clock_src);
  441. u32 af_delay_min, af_delay_max;
  442. u16 p, l, a;
  443. int sdadel_min, sdadel_max, scldel_min;
  444. int ret = 0;
  445. af_delay_min = setup->analog_filter ?
  446. STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
  447. af_delay_max = setup->analog_filter ?
  448. STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
  449. sdadel_min = specs->hddat_min + setup->fall_time -
  450. af_delay_min - (setup->dnf + 3) * i2cclk;
  451. sdadel_max = specs->vddat_max - setup->rise_time -
  452. af_delay_max - (setup->dnf + 4) * i2cclk;
  453. scldel_min = setup->rise_time + specs->sudat_min;
  454. if (sdadel_min < 0)
  455. sdadel_min = 0;
  456. if (sdadel_max < 0)
  457. sdadel_max = 0;
  458. debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
  459. sdadel_min, sdadel_max, scldel_min);
  460. /* Compute possible values for PRESC, SCLDEL and SDADEL */
  461. for (p = 0; p < STM32_PRESC_MAX; p++) {
  462. for (l = 0; l < STM32_SCLDEL_MAX; l++) {
  463. int scldel = (l + 1) * (p + 1) * i2cclk;
  464. if (scldel < scldel_min)
  465. continue;
  466. for (a = 0; a < STM32_SDADEL_MAX; a++) {
  467. int sdadel = (a * (p + 1) + 1) * i2cclk;
  468. if (((sdadel >= sdadel_min) &&
  469. (sdadel <= sdadel_max)) &&
  470. (p != p_prev)) {
  471. v = calloc(1, sizeof(*v));
  472. if (!v)
  473. return -ENOMEM;
  474. v->presc = p;
  475. v->scldel = l;
  476. v->sdadel = a;
  477. p_prev = p;
  478. list_add_tail(&v->node, solutions);
  479. break;
  480. }
  481. }
  482. if (p_prev == p)
  483. break;
  484. }
  485. }
  486. if (list_empty(solutions)) {
  487. pr_err("%s: no Prescaler solution\n", __func__);
  488. ret = -EPERM;
  489. }
  490. return ret;
  491. }
  492. static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
  493. const struct stm32_i2c_spec *specs,
  494. struct list_head *solutions,
  495. struct stm32_i2c_timings *s)
  496. {
  497. struct stm32_i2c_timings *v;
  498. u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
  499. setup->speed_freq);
  500. u32 clk_error_prev = i2cbus;
  501. u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
  502. setup->clock_src);
  503. u32 clk_min, clk_max;
  504. u32 af_delay_min;
  505. u32 dnf_delay;
  506. u32 tsync;
  507. u16 l, h;
  508. bool sol_found = false;
  509. int ret = 0;
  510. af_delay_min = setup->analog_filter ?
  511. STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
  512. dnf_delay = setup->dnf * i2cclk;
  513. tsync = af_delay_min + dnf_delay + (2 * i2cclk);
  514. clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
  515. clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
  516. /*
  517. * Among Prescaler possibilities discovered above figures out SCL Low
  518. * and High Period. Provided:
  519. * - SCL Low Period has to be higher than Low Period of the SCL Clock
  520. * defined by I2C Specification. I2C Clock has to be lower than
  521. * (SCL Low Period - Analog/Digital filters) / 4.
  522. * - SCL High Period has to be lower than High Period of the SCL Clock
  523. * defined by I2C Specification
  524. * - I2C Clock has to be lower than SCL High Period
  525. */
  526. list_for_each_entry(v, solutions, node) {
  527. u32 prescaler = (v->presc + 1) * i2cclk;
  528. for (l = 0; l < STM32_SCLL_MAX; l++) {
  529. u32 tscl_l = (l + 1) * prescaler + tsync;
  530. if (tscl_l < specs->l_min ||
  531. (i2cclk >=
  532. ((tscl_l - af_delay_min - dnf_delay) / 4))) {
  533. continue;
  534. }
  535. for (h = 0; h < STM32_SCLH_MAX; h++) {
  536. u32 tscl_h = (h + 1) * prescaler + tsync;
  537. u32 tscl = tscl_l + tscl_h +
  538. setup->rise_time + setup->fall_time;
  539. if ((tscl >= clk_min) && (tscl <= clk_max) &&
  540. (tscl_h >= specs->h_min) &&
  541. (i2cclk < tscl_h)) {
  542. u32 clk_error;
  543. if (tscl > i2cbus)
  544. clk_error = tscl - i2cbus;
  545. else
  546. clk_error = i2cbus - tscl;
  547. if (clk_error < clk_error_prev) {
  548. clk_error_prev = clk_error;
  549. v->scll = l;
  550. v->sclh = h;
  551. sol_found = true;
  552. memcpy(s, v, sizeof(*s));
  553. }
  554. }
  555. }
  556. }
  557. }
  558. if (!sol_found) {
  559. pr_err("%s: no solution at all\n", __func__);
  560. ret = -EPERM;
  561. }
  562. return ret;
  563. }
  564. static const struct stm32_i2c_spec *get_specs(u32 rate)
  565. {
  566. unsigned int i;
  567. for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
  568. if (rate <= i2c_specs[i].rate)
  569. return &i2c_specs[i];
  570. /* NOT REACHED */
  571. return ERR_PTR(-EINVAL);
  572. }
  573. static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
  574. struct stm32_i2c_setup *setup,
  575. struct stm32_i2c_timings *output)
  576. {
  577. const struct stm32_i2c_spec *specs;
  578. struct stm32_i2c_timings *v, *_v;
  579. struct list_head solutions;
  580. int ret;
  581. specs = get_specs(setup->speed_freq);
  582. if (specs == ERR_PTR(-EINVAL)) {
  583. pr_err("%s: speed out of bound {%d}\n", __func__,
  584. setup->speed_freq);
  585. return -EINVAL;
  586. }
  587. if (setup->rise_time > specs->rise_max ||
  588. setup->fall_time > specs->fall_max) {
  589. pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
  590. __func__,
  591. setup->rise_time, specs->rise_max,
  592. setup->fall_time, specs->fall_max);
  593. return -EINVAL;
  594. }
  595. if (setup->dnf > STM32_I2C_DNF_MAX) {
  596. pr_err("%s: DNF out of bound %d/%d\n", __func__,
  597. setup->dnf, STM32_I2C_DNF_MAX);
  598. return -EINVAL;
  599. }
  600. INIT_LIST_HEAD(&solutions);
  601. ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
  602. if (ret)
  603. goto exit;
  604. ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
  605. if (ret)
  606. goto exit;
  607. debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
  608. __func__, output->presc,
  609. output->scldel, output->sdadel,
  610. output->scll, output->sclh);
  611. exit:
  612. /* Release list and memory */
  613. list_for_each_entry_safe(v, _v, &solutions, node) {
  614. list_del(&v->node);
  615. free(v);
  616. }
  617. return ret;
  618. }
  619. static u32 get_lower_rate(u32 rate)
  620. {
  621. int i;
  622. for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
  623. if (rate > i2c_specs[i].rate)
  624. return i2c_specs[i].rate;
  625. return i2c_specs[0].rate;
  626. }
  627. static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
  628. struct stm32_i2c_timings *timing)
  629. {
  630. struct stm32_i2c_setup *setup = i2c_priv->setup;
  631. int ret = 0;
  632. setup->speed_freq = i2c_priv->speed;
  633. setup->clock_src = clk_get_rate(&i2c_priv->clk);
  634. if (!setup->clock_src) {
  635. pr_err("%s: clock rate is 0\n", __func__);
  636. return -EINVAL;
  637. }
  638. do {
  639. ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
  640. if (ret) {
  641. debug("%s: failed to compute I2C timings.\n",
  642. __func__);
  643. if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
  644. setup->speed_freq =
  645. get_lower_rate(setup->speed_freq);
  646. debug("%s: downgrade I2C Speed Freq to (%i)\n",
  647. __func__, setup->speed_freq);
  648. } else {
  649. break;
  650. }
  651. }
  652. } while (ret);
  653. if (ret) {
  654. pr_err("%s: impossible to compute I2C timings.\n", __func__);
  655. return ret;
  656. }
  657. debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
  658. setup->speed_freq, setup->clock_src);
  659. debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
  660. setup->rise_time, setup->fall_time);
  661. debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
  662. setup->analog_filter ? "On" : "Off", setup->dnf);
  663. i2c_priv->speed = setup->speed_freq;
  664. return 0;
  665. }
  666. static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv)
  667. {
  668. int ret;
  669. bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE;
  670. /* Optional */
  671. if (IS_ERR_OR_NULL(i2c_priv->regmap))
  672. return 0;
  673. if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg)
  674. ret = regmap_update_bits(i2c_priv->regmap,
  675. i2c_priv->regmap_sreg,
  676. i2c_priv->regmap_mask,
  677. enable ? i2c_priv->regmap_mask : 0);
  678. else
  679. ret = regmap_write(i2c_priv->regmap,
  680. enable ? i2c_priv->regmap_sreg :
  681. i2c_priv->regmap_creg,
  682. i2c_priv->regmap_mask);
  683. return ret;
  684. }
  685. static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
  686. {
  687. struct stm32_i2c_regs *regs = i2c_priv->regs;
  688. struct stm32_i2c_timings t;
  689. int ret;
  690. u32 timing = 0;
  691. ret = stm32_i2c_setup_timing(i2c_priv, &t);
  692. if (ret)
  693. return ret;
  694. /* Disable I2C */
  695. clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
  696. /* Setup Fast mode plus if necessary */
  697. ret = stm32_i2c_write_fm_plus_bits(i2c_priv);
  698. if (ret)
  699. return ret;
  700. /* Timing settings */
  701. timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
  702. timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
  703. timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
  704. timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
  705. timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
  706. writel(timing, &regs->timingr);
  707. /* Enable I2C */
  708. if (i2c_priv->setup->analog_filter)
  709. clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
  710. else
  711. setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
  712. setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
  713. return 0;
  714. }
  715. static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  716. {
  717. struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
  718. if (speed > I2C_SPEED_FAST_PLUS_RATE) {
  719. debug("%s: Speed %d not supported\n", __func__, speed);
  720. return -EINVAL;
  721. }
  722. i2c_priv->speed = speed;
  723. return stm32_i2c_hw_config(i2c_priv);
  724. }
  725. static int stm32_i2c_probe(struct udevice *dev)
  726. {
  727. struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
  728. struct reset_ctl reset_ctl;
  729. fdt_addr_t addr;
  730. int ret;
  731. addr = dev_read_addr(dev);
  732. if (addr == FDT_ADDR_T_NONE)
  733. return -EINVAL;
  734. i2c_priv->regs = (struct stm32_i2c_regs *)addr;
  735. ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
  736. if (ret)
  737. return ret;
  738. ret = clk_enable(&i2c_priv->clk);
  739. if (ret)
  740. goto clk_free;
  741. ret = reset_get_by_index(dev, 0, &reset_ctl);
  742. if (ret)
  743. goto clk_disable;
  744. reset_assert(&reset_ctl);
  745. udelay(2);
  746. reset_deassert(&reset_ctl);
  747. return 0;
  748. clk_disable:
  749. clk_disable(&i2c_priv->clk);
  750. clk_free:
  751. clk_free(&i2c_priv->clk);
  752. return ret;
  753. }
  754. static int stm32_ofdata_to_platdata(struct udevice *dev)
  755. {
  756. struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
  757. u32 rise_time, fall_time;
  758. int ret;
  759. i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
  760. if (!i2c_priv->setup)
  761. return -EINVAL;
  762. rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
  763. if (rise_time)
  764. i2c_priv->setup->rise_time = rise_time;
  765. fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
  766. if (fall_time)
  767. i2c_priv->setup->fall_time = fall_time;
  768. /* Optional */
  769. i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev,
  770. "st,syscfg-fmp");
  771. if (!IS_ERR(i2c_priv->regmap)) {
  772. u32 fmp[3];
  773. ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3);
  774. if (ret)
  775. return ret;
  776. i2c_priv->regmap_sreg = fmp[1];
  777. i2c_priv->regmap_creg = fmp[1] +
  778. i2c_priv->setup->fmp_clr_offset;
  779. i2c_priv->regmap_mask = fmp[2];
  780. }
  781. return 0;
  782. }
  783. static const struct dm_i2c_ops stm32_i2c_ops = {
  784. .xfer = stm32_i2c_xfer,
  785. .set_bus_speed = stm32_i2c_set_bus_speed,
  786. };
  787. static const struct udevice_id stm32_i2c_of_match[] = {
  788. { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
  789. { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup },
  790. {}
  791. };
  792. U_BOOT_DRIVER(stm32f7_i2c) = {
  793. .name = "stm32f7-i2c",
  794. .id = UCLASS_I2C,
  795. .of_match = stm32_i2c_of_match,
  796. .ofdata_to_platdata = stm32_ofdata_to_platdata,
  797. .probe = stm32_i2c_probe,
  798. .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
  799. .ops = &stm32_i2c_ops,
  800. };