omap24xx_i2c.h 5.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2004-2010
  4. * Texas Instruments, <www.ti.com>
  5. */
  6. #ifndef _OMAP2PLUS_I2C_H_
  7. #define _OMAP2PLUS_I2C_H_
  8. /* I2C masks */
  9. /* I2C Interrupt Enable Register (I2C_IE): */
  10. #define I2C_IE_GC_IE (1 << 5)
  11. #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
  12. #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
  13. #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
  14. #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
  15. #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
  16. /* I2C Status Register (I2C_STAT): */
  17. #define I2C_STAT_SBD (1 << 15) /* Single byte data */
  18. #define I2C_STAT_BB (1 << 12) /* Bus busy */
  19. #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
  20. #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
  21. #define I2C_STAT_AAS (1 << 9) /* Address as slave */
  22. #define I2C_STAT_GC (1 << 5)
  23. #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
  24. #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
  25. #define I2C_STAT_ARDY (1 << 2) /* Register access ready */
  26. #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
  27. #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
  28. /* I2C Interrupt Code Register (I2C_INTCODE): */
  29. #define I2C_INTCODE_MASK 7
  30. #define I2C_INTCODE_NONE 0
  31. #define I2C_INTCODE_AL 1 /* Arbitration lost */
  32. #define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
  33. #define I2C_INTCODE_ARDY 3 /* Register access ready */
  34. #define I2C_INTCODE_RRDY 4 /* Rcv data ready */
  35. #define I2C_INTCODE_XRDY 5 /* Xmit data ready */
  36. /* I2C Buffer Configuration Register (I2C_BUF): */
  37. #define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
  38. #define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
  39. /* I2C Configuration Register (I2C_CON): */
  40. #define I2C_CON_EN (1 << 15) /* I2C module enable */
  41. #define I2C_CON_BE (1 << 14) /* Big endian mode */
  42. #define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
  43. #define I2C_CON_MST (1 << 10) /* Master/slave mode */
  44. #define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
  45. /* (master mode only) */
  46. #define I2C_CON_XA (1 << 8) /* Expand address */
  47. #define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
  48. #define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
  49. /* I2C System Test Register (I2C_SYSTEST): */
  50. #define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
  51. #define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
  52. #define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
  53. #define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
  54. #define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
  55. #define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
  56. #define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
  57. #define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
  58. /* I2C System Status Register (I2C_SYSS): */
  59. #define I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */
  60. #define I2C_SCLL_SCLL 0
  61. #define I2C_SCLL_SCLL_M 0xFF
  62. #define I2C_SCLL_HSSCLL 8
  63. #define I2C_SCLH_HSSCLL_M 0xFF
  64. #define I2C_SCLH_SCLH 0
  65. #define I2C_SCLH_SCLH_M 0xFF
  66. #define I2C_SCLH_HSSCLH 8
  67. #define I2C_SCLH_HSSCLH_M 0xFF
  68. #define SYSTEM_CLOCK_12 12000000
  69. #define SYSTEM_CLOCK_13 13000000
  70. #define SYSTEM_CLOCK_192 19200000
  71. #define SYSTEM_CLOCK_96 96000000
  72. /* Use the reference value of 96MHz if not explicitly set by the board */
  73. #ifndef I2C_IP_CLK
  74. #define I2C_IP_CLK SYSTEM_CLOCK_96
  75. #endif
  76. /*
  77. * The reference minimum clock for high speed is 19.2MHz.
  78. * The linux 2.6.30 kernel uses this value.
  79. * The reference minimum clock for fast mode is 9.6MHz
  80. * The reference minimum clock for standard mode is 4MHz
  81. * In TRM, the value of 12MHz is used.
  82. */
  83. #ifndef I2C_INTERNAL_SAMPLING_CLK
  84. #define I2C_INTERNAL_SAMPLING_CLK 19200000
  85. #endif
  86. /*
  87. * The equation for the low and high time is
  88. * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
  89. * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
  90. *
  91. * If the duty cycle is 50%
  92. *
  93. * tlow = scll + scll_trim = sampling clock / (2 * speed)
  94. * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
  95. *
  96. * In TRM
  97. * scll_trim = 7
  98. * sclh_trim = 5
  99. *
  100. * The linux 4.9 kernel uses
  101. * scll_trim = 7
  102. * sclh_trim = 5
  103. *
  104. * These are the trim values for standard and fast speed
  105. */
  106. #ifndef I2C_FASTSPEED_SCLL_TRIM
  107. #define I2C_FASTSPEED_SCLL_TRIM 7
  108. #endif
  109. #ifndef I2C_FASTSPEED_SCLH_TRIM
  110. #define I2C_FASTSPEED_SCLH_TRIM 5
  111. #endif
  112. /* These are the trim values for high speed */
  113. #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
  114. #define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
  115. #endif
  116. #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
  117. #define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
  118. #endif
  119. #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
  120. #define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
  121. #endif
  122. #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
  123. #define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
  124. #endif
  125. #define I2C_PSC_MAX 0x0f
  126. #define I2C_PSC_MIN 0x00
  127. #endif /* _OMAP24XX_I2C_H_ */