iproc_i2c.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Broadcom
  4. *
  5. */
  6. #include <asm/io.h>
  7. #include <common.h>
  8. #include <config.h>
  9. #include <dm.h>
  10. #include "errno.h"
  11. #include <i2c.h>
  12. #include "iproc_i2c.h"
  13. DECLARE_GLOBAL_DATA_PTR;
  14. struct iproc_i2c_regs {
  15. u32 cfg_reg;
  16. u32 timg_cfg;
  17. u32 addr_reg;
  18. u32 mstr_fifo_ctrl;
  19. u32 slv_fifo_ctrl;
  20. u32 bitbng_ctrl;
  21. u32 blnks[6]; /* Not to be used */
  22. u32 mstr_cmd;
  23. u32 slv_cmd;
  24. u32 evt_en;
  25. u32 evt_sts;
  26. u32 mstr_datawr;
  27. u32 mstr_datard;
  28. u32 slv_datawr;
  29. u32 slv_datard;
  30. };
  31. struct iproc_i2c {
  32. struct iproc_i2c_regs __iomem *base; /* register base */
  33. int bus_speed;
  34. int i2c_init_done;
  35. };
  36. /* Function to read a value from specified register. */
  37. static unsigned int iproc_i2c_reg_read(u32 *reg_addr)
  38. {
  39. unsigned int val;
  40. val = readl((void *)(reg_addr));
  41. return cpu_to_le32(val);
  42. }
  43. /* Function to write a value ('val') in to a specified register. */
  44. static int iproc_i2c_reg_write(u32 *reg_addr, unsigned int val)
  45. {
  46. val = cpu_to_le32(val);
  47. writel(val, (void *)(reg_addr));
  48. return 0;
  49. }
  50. #if defined(DEBUG)
  51. static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
  52. {
  53. struct iproc_i2c_regs *base = bus_prvdata->base;
  54. unsigned int regval;
  55. debug("\n----------------------------------------------\n");
  56. debug("%s: Dumping SMBus registers...\n", __func__);
  57. regval = iproc_i2c_reg_read(&base->cfg_reg);
  58. debug("CCB_SMB_CFG_REG=0x%08X\n", regval);
  59. regval = iproc_i2c_reg_read(&base->timg_cfg);
  60. debug("CCB_SMB_TIMGCFG_REG=0x%08X\n", regval);
  61. regval = iproc_i2c_reg_read(&base->addr_reg);
  62. debug("CCB_SMB_ADDR_REG=0x%08X\n", regval);
  63. regval = iproc_i2c_reg_read(&base->mstr_fifo_ctrl);
  64. debug("CCB_SMB_MSTRFIFOCTL_REG=0x%08X\n", regval);
  65. regval = iproc_i2c_reg_read(&base->slv_fifo_ctrl);
  66. debug("CCB_SMB_SLVFIFOCTL_REG=0x%08X\n", regval);
  67. regval = iproc_i2c_reg_read(&base->bitbng_ctrl);
  68. debug("CCB_SMB_BITBANGCTL_REG=0x%08X\n", regval);
  69. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  70. debug("CCB_SMB_MSTRCMD_REG=0x%08X\n", regval);
  71. regval = iproc_i2c_reg_read(&base->slv_cmd);
  72. debug("CCB_SMB_SLVCMD_REG=0x%08X\n", regval);
  73. regval = iproc_i2c_reg_read(&base->evt_en);
  74. debug("CCB_SMB_EVTEN_REG=0x%08X\n", regval);
  75. regval = iproc_i2c_reg_read(&base->evt_sts);
  76. debug("CCB_SMB_EVTSTS_REG=0x%08X\n", regval);
  77. regval = iproc_i2c_reg_read(&base->mstr_datawr);
  78. debug("CCB_SMB_MSTRDATAWR_REG=0x%08X\n", regval);
  79. regval = iproc_i2c_reg_read(&base->mstr_datard);
  80. debug("CCB_SMB_MSTRDATARD_REG=0x%08X\n", regval);
  81. regval = iproc_i2c_reg_read(&base->slv_datawr);
  82. debug("CCB_SMB_SLVDATAWR_REG=0x%08X\n", regval);
  83. regval = iproc_i2c_reg_read(&base->slv_datard);
  84. debug("CCB_SMB_SLVDATARD_REG=0x%08X\n", regval);
  85. debug("----------------------------------------------\n\n");
  86. return 0;
  87. }
  88. #else
  89. static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
  90. {
  91. return 0;
  92. }
  93. #endif
  94. /*
  95. * Function to ensure that the previous transaction was completed before
  96. * initiating a new transaction. It can also be used in polling mode to
  97. * check status of completion of a command
  98. */
  99. static int iproc_i2c_startbusy_wait(struct iproc_i2c *bus_prvdata)
  100. {
  101. struct iproc_i2c_regs *base = bus_prvdata->base;
  102. unsigned int regval;
  103. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  104. /* Check if an operation is in progress. During probe it won't be.
  105. * But when shutdown/remove was called we want to make sure that
  106. * the transaction in progress completed
  107. */
  108. if (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
  109. unsigned int i = 0;
  110. do {
  111. mdelay(10);
  112. i++;
  113. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  114. /* If start-busy bit cleared, exit the loop */
  115. } while ((regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) &&
  116. (i < IPROC_SMB_MAX_RETRIES));
  117. if (i >= IPROC_SMB_MAX_RETRIES) {
  118. pr_err("%s: START_BUSY bit didn't clear, exiting\n",
  119. __func__);
  120. return -ETIMEDOUT;
  121. }
  122. }
  123. return 0;
  124. }
  125. /*
  126. * This function set clock frequency for SMBus block. As per hardware
  127. * engineering, the clock frequency can be changed dynamically.
  128. */
  129. static int iproc_i2c_set_clk_freq(struct iproc_i2c *bus_prvdata)
  130. {
  131. struct iproc_i2c_regs *base = bus_prvdata->base;
  132. unsigned int regval;
  133. regval = iproc_i2c_reg_read(&base->timg_cfg);
  134. switch (bus_prvdata->bus_speed) {
  135. case I2C_SPEED_STANDARD_RATE:
  136. regval &= ~CCB_SMB_TIMGCFG_MODE400_MASK;
  137. break;
  138. case I2C_SPEED_FAST_RATE:
  139. regval |= CCB_SMB_TIMGCFG_MODE400_MASK;
  140. break;
  141. default:
  142. return -EINVAL;
  143. }
  144. iproc_i2c_reg_write(&base->timg_cfg, regval);
  145. return 0;
  146. }
  147. static int iproc_i2c_init(struct udevice *bus)
  148. {
  149. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  150. struct iproc_i2c_regs *base = bus_prvdata->base;
  151. unsigned int regval;
  152. debug("\nEntering %s\n", __func__);
  153. /* Put controller in reset */
  154. regval = iproc_i2c_reg_read(&base->cfg_reg);
  155. regval |= CCB_SMB_CFG_RST_MASK;
  156. regval &= ~CCB_SMB_CFG_SMBEN_MASK;
  157. iproc_i2c_reg_write(&base->cfg_reg, regval);
  158. /* Wait 100 usec as per spec */
  159. udelay(100);
  160. /* bring controller out of reset */
  161. regval &= ~CCB_SMB_CFG_RST_MASK;
  162. iproc_i2c_reg_write(&base->cfg_reg, regval);
  163. /* Flush Tx, Rx FIFOs. Note we are setting the Rx FIFO threshold to 0.
  164. * May be OK since we are setting RX_EVENT and RX_FIFO_FULL interrupts
  165. */
  166. regval = CCB_SMB_MSTRRXFIFOFLSH_MASK | CCB_SMB_MSTRTXFIFOFLSH_MASK;
  167. iproc_i2c_reg_write(&base->mstr_fifo_ctrl, regval);
  168. /* Enable SMbus block. Note, we are setting MASTER_RETRY_COUNT to zero
  169. * since there will be only one master
  170. */
  171. regval = iproc_i2c_reg_read(&base->cfg_reg);
  172. regval |= CCB_SMB_CFG_SMBEN_MASK;
  173. iproc_i2c_reg_write(&base->cfg_reg, regval);
  174. /* Set default clock frequency */
  175. iproc_i2c_set_clk_freq(bus_prvdata);
  176. /* Disable intrs */
  177. iproc_i2c_reg_write(&base->evt_en, 0);
  178. /* Clear intrs (W1TC) */
  179. regval = iproc_i2c_reg_read(&base->evt_sts);
  180. iproc_i2c_reg_write(&base->evt_sts, regval);
  181. bus_prvdata->i2c_init_done = 1;
  182. iproc_dump_i2c_regs(bus_prvdata);
  183. debug("%s: Init successful\n", __func__);
  184. return 0;
  185. }
  186. /*
  187. * This function copies data to SMBus's Tx FIFO. Valid for write transactions
  188. * only
  189. *
  190. * base_addr: Mapped address of this SMBus instance
  191. * dev_addr: SMBus (I2C) device address. We are assuming 7-bit addresses
  192. * initially
  193. * info: Data to copy in to Tx FIFO. For read commands, the size should be
  194. * set to zero by the caller
  195. *
  196. */
  197. static void iproc_i2c_write_trans_data(struct iproc_i2c *bus_prvdata,
  198. unsigned short dev_addr,
  199. struct iproc_xact_info *info)
  200. {
  201. struct iproc_i2c_regs *base = bus_prvdata->base;
  202. unsigned int regval;
  203. unsigned int i;
  204. unsigned int num_data_bytes = 0;
  205. debug("%s: dev_addr=0x%X cmd_valid=%d cmd=0x%02x size=%u proto=%d buf[] %x\n",
  206. __func__, dev_addr, info->cmd_valid,
  207. info->command, info->size, info->smb_proto, info->data[0]);
  208. /* Write SMBus device address first */
  209. /* Note, we are assuming 7-bit addresses for now. For 10-bit addresses,
  210. * we may have one more write to send the upper 3 bits of 10-bit addr
  211. */
  212. iproc_i2c_reg_write(&base->mstr_datawr, dev_addr);
  213. /* If the protocol needs command code, copy it */
  214. if (info->cmd_valid)
  215. iproc_i2c_reg_write(&base->mstr_datawr, info->command);
  216. /* Depending on the SMBus protocol, we need to write additional
  217. * transaction data in to Tx FIFO. Refer to section 5.5 of SMBus
  218. * spec for sequence for a transaction
  219. */
  220. switch (info->smb_proto) {
  221. case SMBUS_PROT_RECV_BYTE:
  222. /* No additional data to be written */
  223. num_data_bytes = 0;
  224. break;
  225. case SMBUS_PROT_SEND_BYTE:
  226. num_data_bytes = info->size;
  227. break;
  228. case SMBUS_PROT_RD_BYTE:
  229. case SMBUS_PROT_RD_WORD:
  230. case SMBUS_PROT_BLK_RD:
  231. /* Write slave address with R/W~ set (bit #0) */
  232. iproc_i2c_reg_write(&base->mstr_datawr,
  233. dev_addr | 0x1);
  234. num_data_bytes = 0;
  235. break;
  236. case SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL:
  237. iproc_i2c_reg_write(&base->mstr_datawr,
  238. dev_addr | 0x1 |
  239. CCB_SMB_MSTRWRSTS_MASK);
  240. num_data_bytes = 0;
  241. break;
  242. case SMBUS_PROT_WR_BYTE:
  243. case SMBUS_PROT_WR_WORD:
  244. /* No additional bytes to be written.
  245. * Data portion is written in the
  246. * 'for' loop below
  247. */
  248. num_data_bytes = info->size;
  249. break;
  250. case SMBUS_PROT_BLK_WR:
  251. /* 3rd byte is byte count */
  252. iproc_i2c_reg_write(&base->mstr_datawr, info->size);
  253. num_data_bytes = info->size;
  254. break;
  255. default:
  256. return;
  257. }
  258. /* Copy actual data from caller, next. In general, for reads,
  259. * no data is copied
  260. */
  261. for (i = 0; num_data_bytes; --num_data_bytes, i++) {
  262. /* For the last byte, set MASTER_WR_STATUS bit */
  263. regval = (num_data_bytes == 1) ?
  264. info->data[i] | CCB_SMB_MSTRWRSTS_MASK :
  265. info->data[i];
  266. iproc_i2c_reg_write(&base->mstr_datawr, regval);
  267. }
  268. }
  269. static int iproc_i2c_data_send(struct iproc_i2c *bus_prvdata,
  270. unsigned short addr,
  271. struct iproc_xact_info *info)
  272. {
  273. struct iproc_i2c_regs *base = bus_prvdata->base;
  274. int rc, retry = 3;
  275. unsigned int regval;
  276. /* Make sure the previous transaction completed */
  277. rc = iproc_i2c_startbusy_wait(bus_prvdata);
  278. if (rc < 0) {
  279. pr_err("%s: Send: bus is busy, exiting\n", __func__);
  280. return rc;
  281. }
  282. /* Write transaction bytes to Tx FIFO */
  283. iproc_i2c_write_trans_data(bus_prvdata, addr, info);
  284. /* Program master command register (0x30) with protocol type and set
  285. * start_busy_command bit to initiate the write transaction
  286. */
  287. regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
  288. CCB_SMB_MSTRSTARTBUSYCMD_MASK;
  289. iproc_i2c_reg_write(&base->mstr_cmd, regval);
  290. /* Check for Master status */
  291. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  292. while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
  293. mdelay(10);
  294. if (retry-- <= 0)
  295. break;
  296. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  297. }
  298. /* If start_busy bit cleared, check if there are any errors */
  299. if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
  300. /* start_busy bit cleared, check master_status field now */
  301. regval &= CCB_SMB_MSTRSTS_MASK;
  302. regval >>= CCB_SMB_MSTRSTS_SHIFT;
  303. if (regval != MSTR_STS_XACT_SUCCESS) {
  304. /* Error We can flush Tx FIFO here */
  305. pr_err("%s: ERROR: Error in transaction %u, exiting\n",
  306. __func__, regval);
  307. return -EREMOTEIO;
  308. }
  309. }
  310. return 0;
  311. }
  312. static int iproc_i2c_data_recv(struct iproc_i2c *bus_prvdata,
  313. unsigned short addr,
  314. struct iproc_xact_info *info,
  315. unsigned int *num_bytes_read)
  316. {
  317. struct iproc_i2c_regs *base = bus_prvdata->base;
  318. int rc, retry = 3;
  319. unsigned int regval;
  320. /* Make sure the previous transaction completed */
  321. rc = iproc_i2c_startbusy_wait(bus_prvdata);
  322. if (rc < 0) {
  323. pr_err("%s: Receive: Bus is busy, exiting\n", __func__);
  324. return rc;
  325. }
  326. /* Program all transaction bytes into master Tx FIFO */
  327. iproc_i2c_write_trans_data(bus_prvdata, addr, info);
  328. /* Program master command register (0x30) with protocol type and set
  329. * start_busy_command bit to initiate the write transaction
  330. */
  331. regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
  332. CCB_SMB_MSTRSTARTBUSYCMD_MASK | info->size;
  333. iproc_i2c_reg_write(&base->mstr_cmd, regval);
  334. /* Check for Master status */
  335. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  336. while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
  337. udelay(1000);
  338. if (retry-- <= 0)
  339. break;
  340. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  341. }
  342. /* If start_busy bit cleared, check if there are any errors */
  343. if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
  344. /* start_busy bit cleared, check master_status field now */
  345. regval &= CCB_SMB_MSTRSTS_MASK;
  346. regval >>= CCB_SMB_MSTRSTS_SHIFT;
  347. if (regval != MSTR_STS_XACT_SUCCESS) {
  348. /* We can flush Tx FIFO here */
  349. pr_err("%s: Error in transaction %d, exiting\n",
  350. __func__, regval);
  351. return -EREMOTEIO;
  352. }
  353. }
  354. /* Read received byte(s), after TX out address etc */
  355. regval = iproc_i2c_reg_read(&base->mstr_datard);
  356. /* For block read, protocol (hw) returns byte count,
  357. * as the first byte
  358. */
  359. if (info->smb_proto == SMBUS_PROT_BLK_RD) {
  360. int i;
  361. *num_bytes_read = regval & CCB_SMB_MSTRRDDATA_MASK;
  362. /* Limit to reading a max of 32 bytes only; just a safeguard.
  363. * If # bytes read is a number > 32, check transaction set up,
  364. * and contact hw engg. Assumption: PEC is disabled
  365. */
  366. for (i = 0;
  367. (i < *num_bytes_read) && (i < I2C_SMBUS_BLOCK_MAX);
  368. i++) {
  369. /* Read Rx FIFO for data bytes */
  370. regval = iproc_i2c_reg_read(&base->mstr_datard);
  371. info->data[i] = regval & CCB_SMB_MSTRRDDATA_MASK;
  372. }
  373. } else {
  374. /* 1 Byte data */
  375. *info->data = regval & CCB_SMB_MSTRRDDATA_MASK;
  376. *num_bytes_read = 1;
  377. }
  378. return 0;
  379. }
  380. static int i2c_write_byte(struct iproc_i2c *bus_prvdata,
  381. u8 devaddr, u8 regoffset, u8 value)
  382. {
  383. int rc;
  384. struct iproc_xact_info info;
  385. devaddr <<= 1;
  386. info.cmd_valid = 1;
  387. info.command = (unsigned char)regoffset;
  388. info.data = &value;
  389. info.size = 1;
  390. info.flags = 0;
  391. info.smb_proto = SMBUS_PROT_WR_BYTE;
  392. /* Refer to i2c_smbus_write_byte params passed. */
  393. rc = iproc_i2c_data_send(bus_prvdata, devaddr, &info);
  394. if (rc < 0) {
  395. pr_err("%s: %s error accessing device 0x%X\n",
  396. __func__, "Write", devaddr);
  397. return -EREMOTEIO;
  398. }
  399. return 0;
  400. }
  401. int i2c_write(struct udevice *bus,
  402. uchar chip, uint regaddr, int alen, uchar *buffer, int len)
  403. {
  404. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  405. int i, data_len;
  406. u8 *data;
  407. if (len > 256) {
  408. pr_err("I2C write: address out of range\n");
  409. return 1;
  410. }
  411. if (len < 1) {
  412. pr_err("I2C write: Need offset addr and value\n");
  413. return 1;
  414. }
  415. /* buffer contains offset addr followed by value to be written */
  416. regaddr = buffer[0];
  417. data = &buffer[1];
  418. data_len = len - 1;
  419. for (i = 0; i < data_len; i++) {
  420. if (i2c_write_byte(bus_prvdata, chip, regaddr + i, data[i])) {
  421. pr_err("I2C write (%d): I/O error\n", i);
  422. iproc_i2c_init(bus);
  423. return 1;
  424. }
  425. }
  426. return 0;
  427. }
  428. static int i2c_read_byte(struct iproc_i2c *bus_prvdata,
  429. u8 devaddr, u8 regoffset, u8 *value)
  430. {
  431. int rc;
  432. struct iproc_xact_info info;
  433. unsigned int num_bytes_read = 0;
  434. devaddr <<= 1;
  435. info.cmd_valid = 1;
  436. info.command = (unsigned char)regoffset;
  437. info.data = value;
  438. info.size = 1;
  439. info.flags = 0;
  440. info.smb_proto = SMBUS_PROT_RD_BYTE;
  441. /* Refer to i2c_smbus_read_byte for params passed. */
  442. rc = iproc_i2c_data_recv(bus_prvdata, devaddr, &info, &num_bytes_read);
  443. if (rc < 0) {
  444. pr_err("%s: %s error accessing device 0x%X\n",
  445. __func__, "Read", devaddr);
  446. return -EREMOTEIO;
  447. }
  448. return 0;
  449. }
  450. int i2c_read(struct udevice *bus,
  451. uchar chip, uint addr, int alen, uchar *buffer, int len)
  452. {
  453. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  454. int i;
  455. if (len > 256) {
  456. pr_err("I2C read: address out of range\n");
  457. return 1;
  458. }
  459. for (i = 0; i < len; i++) {
  460. if (i2c_read_byte(bus_prvdata, chip, addr + i, &buffer[i])) {
  461. pr_err("I2C read: I/O error\n");
  462. iproc_i2c_init(bus);
  463. return 1;
  464. }
  465. }
  466. return 0;
  467. }
  468. static int iproc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  469. {
  470. int ret = 0;
  471. debug("%s: %d messages\n", __func__, nmsgs);
  472. for (; nmsgs > 0; nmsgs--, msg++) {
  473. if (msg->flags & I2C_M_RD)
  474. ret = i2c_read(bus, msg->addr, 0, 0,
  475. msg->buf, msg->len);
  476. else
  477. ret = i2c_write(bus, msg->addr, 0, 0,
  478. msg->buf, msg->len);
  479. }
  480. return ret;
  481. }
  482. static int iproc_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  483. uint chip_flags)
  484. {
  485. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  486. struct iproc_i2c_regs *base = bus_prvdata->base;
  487. u32 regval;
  488. debug("\n%s: Entering chip probe\n", __func__);
  489. /* Init internal regs, disable intrs (and then clear intrs), set fifo
  490. * thresholds, etc.
  491. */
  492. if (!bus_prvdata->i2c_init_done)
  493. iproc_i2c_init(bus);
  494. regval = (chip_addr << 1);
  495. iproc_i2c_reg_write(&base->mstr_datawr, regval);
  496. regval = ((SMBUS_PROT_QUICK_CMD << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
  497. (1 << CCB_SMB_MSTRSTARTBUSYCMD_SHIFT));
  498. iproc_i2c_reg_write(&base->mstr_cmd, regval);
  499. do {
  500. udelay(100);
  501. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  502. regval &= CCB_SMB_MSTRSTARTBUSYCMD_MASK;
  503. } while (regval);
  504. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  505. if ((regval & CCB_SMB_MSTRSTS_MASK) != 0)
  506. return -1;
  507. iproc_dump_i2c_regs(bus_prvdata);
  508. debug("%s: chip probe successful\n", __func__);
  509. return 0;
  510. }
  511. static int iproc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  512. {
  513. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  514. bus_prvdata->bus_speed = speed;
  515. return iproc_i2c_set_clk_freq(bus_prvdata);
  516. }
  517. /**
  518. * i2c_get_bus_speed - get i2c bus speed
  519. *
  520. * This function returns the speed of operation in Hz
  521. */
  522. int iproc_i2c_get_bus_speed(struct udevice *bus)
  523. {
  524. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  525. struct iproc_i2c_regs *base = bus_prvdata->base;
  526. unsigned int regval;
  527. int ret = 0;
  528. regval = iproc_i2c_reg_read(&base->timg_cfg);
  529. regval = (regval & CCB_SMB_TIMGCFG_MODE400_MASK) >>
  530. CCB_SMB_TIMGCFG_MODE400_SHIFT;
  531. switch (regval) {
  532. case 0:
  533. ret = I2C_SPEED_STANDARD_RATE;
  534. break;
  535. case 1:
  536. ret = I2C_SPEED_FAST_RATE;
  537. break;
  538. default:
  539. ret = -EINVAL;
  540. break;
  541. }
  542. return ret;
  543. }
  544. static int iproc_i2c_probe(struct udevice *bus)
  545. {
  546. return iproc_i2c_init(bus);
  547. }
  548. static int iproc_i2c_ofdata_to_platdata(struct udevice *bus)
  549. {
  550. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  551. int node = dev_of_offset(bus);
  552. const void *blob = gd->fdt_blob;
  553. bus_prvdata->base = map_physmem(dev_read_addr(bus),
  554. sizeof(void *),
  555. MAP_NOCACHE);
  556. bus_prvdata->bus_speed =
  557. fdtdec_get_int(blob, node, "bus-frequency",
  558. I2C_SPEED_STANDARD_RATE);
  559. return 0;
  560. }
  561. static const struct dm_i2c_ops iproc_i2c_ops = {
  562. .xfer = iproc_i2c_xfer,
  563. .probe_chip = iproc_i2c_probe_chip,
  564. .set_bus_speed = iproc_i2c_set_bus_speed,
  565. .get_bus_speed = iproc_i2c_get_bus_speed,
  566. };
  567. static const struct udevice_id iproc_i2c_ids[] = {
  568. { .compatible = "brcm,iproc-i2c" },
  569. { }
  570. };
  571. U_BOOT_DRIVER(iproc_i2c) = {
  572. .name = "iproc_i2c",
  573. .id = UCLASS_I2C,
  574. .of_match = iproc_i2c_ids,
  575. .ofdata_to_platdata = iproc_i2c_ofdata_to_platdata,
  576. .probe = iproc_i2c_probe,
  577. .priv_auto_alloc_size = sizeof(struct iproc_i2c),
  578. .ops = &iproc_i2c_ops,
  579. .flags = DM_FLAG_PRE_RELOC,
  580. };