intel_i2c.c 7.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. *
  6. * SMBus block read/write support added by Stefan Roese:
  7. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <i2c.h>
  12. #include <log.h>
  13. #include <pci.h>
  14. #include <asm/io.h>
  15. /* PCI Configuration Space (D31:F3): SMBus */
  16. #define SMB_BASE 0x20
  17. #define HOSTC 0x40
  18. #define HST_EN (1 << 0)
  19. #define SMB_RCV_SLVA 0x09
  20. /* SMBus I/O bits. */
  21. #define SMBHSTSTAT 0x0
  22. #define SMBHSTCTL 0x2
  23. #define SMBHSTCMD 0x3
  24. #define SMBXMITADD 0x4
  25. #define SMBHSTDAT0 0x5
  26. #define SMBHSTDAT1 0x6
  27. #define SMBBLKDAT 0x7
  28. #define SMBTRNSADD 0x9
  29. #define SMBSLVDATA 0xa
  30. #define SMBAUXCTL 0xd
  31. #define SMLINK_PIN_CTL 0xe
  32. #define SMBUS_PIN_CTL 0xf
  33. /* I801 Hosts Status register bits */
  34. #define SMBHSTSTS_BYTE_DONE 0x80
  35. #define SMBHSTSTS_INUSE_STS 0x40
  36. #define SMBHSTSTS_SMBALERT_STS 0x20
  37. #define SMBHSTSTS_FAILED 0x10
  38. #define SMBHSTSTS_BUS_ERR 0x08
  39. #define SMBHSTSTS_DEV_ERR 0x04
  40. #define SMBHSTSTS_INTR 0x02
  41. #define SMBHSTSTS_HOST_BUSY 0x01
  42. /* I801 Host Control register bits */
  43. #define SMBHSTCNT_INTREN 0x01
  44. #define SMBHSTCNT_KILL 0x02
  45. #define SMBHSTCNT_LAST_BYTE 0x20
  46. #define SMBHSTCNT_START 0x40
  47. #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
  48. /* Auxiliary control register bits, ICH4+ only */
  49. #define SMBAUXCTL_CRC 1
  50. #define SMBAUXCTL_E32B 2
  51. #define SMBUS_TIMEOUT 100 /* 100 ms */
  52. struct intel_i2c {
  53. u32 base;
  54. int running;
  55. };
  56. static int smbus_wait_until_ready(u32 base)
  57. {
  58. unsigned long ts;
  59. u8 byte;
  60. ts = get_timer(0);
  61. do {
  62. byte = inb(base + SMBHSTSTAT);
  63. if (!(byte & 1))
  64. return 0;
  65. } while (get_timer(ts) < SMBUS_TIMEOUT);
  66. return -ETIMEDOUT;
  67. }
  68. static int smbus_wait_until_done(u32 base)
  69. {
  70. unsigned long ts;
  71. u8 byte;
  72. ts = get_timer(0);
  73. do {
  74. byte = inb(base + SMBHSTSTAT);
  75. if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0))
  76. return 0;
  77. } while (get_timer(ts) < SMBUS_TIMEOUT);
  78. return -ETIMEDOUT;
  79. }
  80. static int smbus_block_read(u32 base, u8 dev, u8 *buffer,
  81. int offset, int len)
  82. {
  83. u8 buf_temp[32];
  84. int count;
  85. int i;
  86. debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n",
  87. __func__, __LINE__, dev, offset, len);
  88. if (smbus_wait_until_ready(base) < 0)
  89. return -ETIMEDOUT;
  90. /* Setup transaction */
  91. /* Reset the data buffer index */
  92. inb(base + SMBHSTCTL);
  93. /* Set the device I'm talking too */
  94. outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD);
  95. /* Set the command/address... */
  96. outb(offset & 0xff, base + SMBHSTCMD);
  97. /* Set up for a block read */
  98. outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),
  99. (base + SMBHSTCTL));
  100. /* Clear any lingering errors, so the transaction will run */
  101. outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);
  102. /* Start the command */
  103. outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);
  104. /* Poll for transaction completion */
  105. if (smbus_wait_until_done(base) < 0) {
  106. printf("SMBUS read transaction timeout (dev=0x%x)\n", dev);
  107. return -ETIMEDOUT;
  108. }
  109. count = inb(base + SMBHSTDAT0);
  110. debug("%s (%d): count=%d (len=%d)\n", __func__, __LINE__, count, len);
  111. if (count == 0) {
  112. debug("ERROR: len=0 on read\n");
  113. return -EIO;
  114. }
  115. if (count < len) {
  116. debug("ERROR: too few bytes read\n");
  117. return -EIO;
  118. }
  119. if (count > 32) {
  120. debug("ERROR: count=%d too high\n", count);
  121. return -EIO;
  122. }
  123. /* Read all available bytes from buffer */
  124. for (i = 0; i < count; i++)
  125. buf_temp[i] = inb(base + SMBBLKDAT);
  126. memcpy(buffer, buf_temp, len);
  127. /* Return results of transaction */
  128. if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))
  129. return -EIO;
  130. return 0;
  131. }
  132. static int smbus_block_write(u32 base, u8 dev, u8 *buffer,
  133. int offset, int len)
  134. {
  135. int i;
  136. debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n",
  137. __func__, __LINE__, dev, offset, len);
  138. if (smbus_wait_until_ready(base) < 0)
  139. return -ETIMEDOUT;
  140. /* Setup transaction */
  141. /* Set the device I'm talking too */
  142. outb(((dev & 0x7f) << 1) & ~0x01, base + SMBXMITADD);
  143. /* Set the command/address... */
  144. outb(offset, base + SMBHSTCMD);
  145. /* Set up for a block write */
  146. outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),
  147. (base + SMBHSTCTL));
  148. /* Clear any lingering errors, so the transaction will run */
  149. outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);
  150. /* Write count in DAT0 register */
  151. outb(len, base + SMBHSTDAT0);
  152. /* Write data bytes... */
  153. for (i = 0; i < len; i++)
  154. outb(*buffer++, base + SMBBLKDAT);
  155. /* Start the command */
  156. outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);
  157. /* Poll for transaction completion */
  158. if (smbus_wait_until_done(base) < 0) {
  159. printf("SMBUS write transaction timeout (dev=0x%x)\n", dev);
  160. return -ETIMEDOUT;
  161. }
  162. /* Return results of transaction */
  163. if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))
  164. return -EIO;
  165. return 0;
  166. }
  167. static int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  168. {
  169. struct intel_i2c *i2c = dev_get_priv(bus);
  170. struct i2c_msg *dmsg, *omsg, dummy;
  171. debug("i2c_xfer: %d messages\n", nmsgs);
  172. memset(&dummy, 0, sizeof(struct i2c_msg));
  173. /*
  174. * We expect either two messages (one with an offset and one with the
  175. * actucal data) or one message (just data)
  176. */
  177. if (nmsgs > 2 || nmsgs == 0) {
  178. debug("%s: Only one or two messages are supported", __func__);
  179. return -EIO;
  180. }
  181. omsg = nmsgs == 1 ? &dummy : msg;
  182. dmsg = nmsgs == 1 ? msg : msg + 1;
  183. if (dmsg->flags & I2C_M_RD)
  184. return smbus_block_read(i2c->base, dmsg->addr, &dmsg->buf[0],
  185. omsg->buf[0], dmsg->len);
  186. else
  187. return smbus_block_write(i2c->base, dmsg->addr, &dmsg->buf[1],
  188. dmsg->buf[0], dmsg->len - 1);
  189. }
  190. static int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  191. uint chip_flags)
  192. {
  193. struct intel_i2c *i2c = dev_get_priv(bus);
  194. u8 buf[4];
  195. return smbus_block_read(i2c->base, chip_addr, buf, 0, 1);
  196. }
  197. static int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  198. {
  199. return 0;
  200. }
  201. static int intel_i2c_probe(struct udevice *dev)
  202. {
  203. struct intel_i2c *priv = dev_get_priv(dev);
  204. ulong base;
  205. /* Save base address from PCI BAR */
  206. priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
  207. PCI_REGION_IO);
  208. base = priv->base;
  209. /* Set SMBus enable. */
  210. dm_pci_write_config8(dev, HOSTC, HST_EN);
  211. /* Disable interrupts */
  212. outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL);
  213. /* Set 32-byte data buffer mode */
  214. outb(inb(base + SMBAUXCTL) | SMBAUXCTL_E32B, base + SMBAUXCTL);
  215. return 0;
  216. }
  217. static int intel_i2c_bind(struct udevice *dev)
  218. {
  219. static int num_cards __attribute__ ((section(".data")));
  220. char name[20];
  221. /* Create a unique device name for PCI type devices */
  222. if (device_is_on_pci_bus(dev)) {
  223. /*
  224. * ToDo:
  225. * Setting req_seq in the driver is probably not recommended.
  226. * But without a DT alias the number is not configured. And
  227. * using this driver is impossible for PCIe I2C devices.
  228. * This can be removed, once a better (correct) way for this
  229. * is found and implemented.
  230. */
  231. dev->req_seq = num_cards;
  232. sprintf(name, "intel_i2c#%u", num_cards++);
  233. device_set_name(dev, name);
  234. }
  235. return 0;
  236. }
  237. static const struct dm_i2c_ops intel_i2c_ops = {
  238. .xfer = intel_i2c_xfer,
  239. .probe_chip = intel_i2c_probe_chip,
  240. .set_bus_speed = intel_i2c_set_bus_speed,
  241. };
  242. static const struct udevice_id intel_i2c_ids[] = {
  243. { .compatible = "intel,ich-i2c" },
  244. { }
  245. };
  246. U_BOOT_DRIVER(intel_i2c) = {
  247. .name = "i2c_intel",
  248. .id = UCLASS_I2C,
  249. .of_match = intel_i2c_ids,
  250. .ops = &intel_i2c_ops,
  251. .priv_auto_alloc_size = sizeof(struct intel_i2c),
  252. .bind = intel_i2c_bind,
  253. .probe = intel_i2c_probe,
  254. };
  255. static struct pci_device_id intel_smbus_pci_supported[] = {
  256. /* Intel BayTrail SMBus on the PCI bus */
  257. { PCI_VDEVICE(INTEL, 0x0f12) },
  258. /* Intel IvyBridge (Panther Point PCH) SMBus on the PCI bus */
  259. { PCI_VDEVICE(INTEL, 0x1e22) },
  260. {},
  261. };
  262. U_BOOT_PCI_DEVICE(intel_i2c, intel_smbus_pci_supported);