fsl_i2c.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2006,2009 Freescale Semiconductor, Inc.
  4. *
  5. * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. * Changes for multibus/multiadapter I2C support.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <i2c.h> /* Functional interface */
  11. #include <log.h>
  12. #include <time.h>
  13. #include <asm/io.h>
  14. #include <asm/fsl_i2c.h> /* HW definitions */
  15. #include <clk.h>
  16. #include <dm.h>
  17. #include <mapmem.h>
  18. #include <linux/delay.h>
  19. /* The maximum number of microseconds we will wait until another master has
  20. * released the bus. If not defined in the board header file, then use a
  21. * generic value.
  22. */
  23. #ifndef CONFIG_I2C_MBB_TIMEOUT
  24. #define CONFIG_I2C_MBB_TIMEOUT 100000
  25. #endif
  26. /* The maximum number of microseconds we will wait for a read or write
  27. * operation to complete. If not defined in the board header file, then use a
  28. * generic value.
  29. */
  30. #ifndef CONFIG_I2C_TIMEOUT
  31. #define CONFIG_I2C_TIMEOUT 100000
  32. #endif
  33. #define I2C_READ_BIT 1
  34. #define I2C_WRITE_BIT 0
  35. DECLARE_GLOBAL_DATA_PTR;
  36. #ifndef CONFIG_DM_I2C
  37. static const struct fsl_i2c_base *i2c_base[4] = {
  38. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
  39. #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  40. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
  41. #endif
  42. #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  43. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
  44. #endif
  45. #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  46. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
  47. #endif
  48. };
  49. #endif
  50. /* I2C speed map for a DFSR value of 1 */
  51. #ifdef __M68K__
  52. /*
  53. * Map I2C frequency dividers to FDR and DFSR values
  54. *
  55. * This structure is used to define the elements of a table that maps I2C
  56. * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
  57. * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
  58. * Sampling Rate (DFSR) registers.
  59. *
  60. * The actual table should be defined in the board file, and it must be called
  61. * fsl_i2c_speed_map[].
  62. *
  63. * The last entry of the table must have a value of {-1, X}, where X is same
  64. * FDR/DFSR values as the second-to-last entry. This guarantees that any
  65. * search through the array will always find a match.
  66. *
  67. * The values of the divider must be in increasing numerical order, i.e.
  68. * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
  69. *
  70. * For this table, the values are based on a value of 1 for the DFSR
  71. * register. See the application note AN2919 "Determining the I2C Frequency
  72. * Divider Ratio for SCL"
  73. *
  74. * ColdFire I2C frequency dividers for FDR values are different from
  75. * PowerPC. The protocol to use the I2C module is still the same.
  76. * A different table is defined and are based on MCF5xxx user manual.
  77. *
  78. */
  79. static const struct {
  80. unsigned short divider;
  81. u8 fdr;
  82. } fsl_i2c_speed_map[] = {
  83. {20, 32}, {22, 33}, {24, 34}, {26, 35},
  84. {28, 0}, {28, 36}, {30, 1}, {32, 37},
  85. {34, 2}, {36, 38}, {40, 3}, {40, 39},
  86. {44, 4}, {48, 5}, {48, 40}, {56, 6},
  87. {56, 41}, {64, 42}, {68, 7}, {72, 43},
  88. {80, 8}, {80, 44}, {88, 9}, {96, 41},
  89. {104, 10}, {112, 42}, {128, 11}, {128, 43},
  90. {144, 12}, {160, 13}, {160, 48}, {192, 14},
  91. {192, 49}, {224, 50}, {240, 15}, {256, 51},
  92. {288, 16}, {320, 17}, {320, 52}, {384, 18},
  93. {384, 53}, {448, 54}, {480, 19}, {512, 55},
  94. {576, 20}, {640, 21}, {640, 56}, {768, 22},
  95. {768, 57}, {960, 23}, {896, 58}, {1024, 59},
  96. {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
  97. {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
  98. {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
  99. {-1, 31}
  100. };
  101. #endif
  102. /**
  103. * Set the I2C bus speed for a given I2C device
  104. *
  105. * @param base: the I2C device registers
  106. * @i2c_clk: I2C bus clock frequency
  107. * @speed: the desired speed of the bus
  108. *
  109. * The I2C device must be stopped before calling this function.
  110. *
  111. * The return value is the actual bus speed that is set.
  112. */
  113. static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
  114. uint i2c_clk, uint speed)
  115. {
  116. ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
  117. /*
  118. * We want to choose an FDR/DFSR that generates an I2C bus speed that
  119. * is equal to or lower than the requested speed. That means that we
  120. * want the first divider that is equal to or greater than the
  121. * calculated divider.
  122. */
  123. #ifdef __PPC__
  124. u8 dfsr, fdr = 0x31; /* Default if no FDR found */
  125. /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
  126. ushort a, b, ga, gb;
  127. ulong c_div, est_div;
  128. #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
  129. dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
  130. #else
  131. /* Condition 1: dfsr <= 50/T */
  132. dfsr = (5 * (i2c_clk / 1000)) / 100000;
  133. #endif
  134. #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
  135. fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
  136. speed = i2c_clk / divider; /* Fake something */
  137. #else
  138. debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
  139. if (!dfsr)
  140. dfsr = 1;
  141. est_div = ~0;
  142. for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
  143. for (gb = 0; gb < 8; gb++) {
  144. b = 16 << gb;
  145. c_div = b * (a + ((3 * dfsr) / b) * 2);
  146. if (c_div > divider && c_div < est_div) {
  147. ushort bin_gb, bin_ga;
  148. est_div = c_div;
  149. bin_gb = gb << 2;
  150. bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
  151. fdr = bin_gb | bin_ga;
  152. speed = i2c_clk / est_div;
  153. debug("FDR: 0x%.2x, ", fdr);
  154. debug("div: %ld, ", est_div);
  155. debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
  156. debug("a: %d, b: %d, speed: %d\n", a, b, speed);
  157. /* Condition 2 not accounted for */
  158. debug("Tr <= %d ns\n",
  159. (b - 3 * dfsr) * 1000000 /
  160. (i2c_clk / 1000));
  161. }
  162. }
  163. if (a == 20)
  164. a += 2;
  165. if (a == 24)
  166. a += 4;
  167. }
  168. debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
  169. debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
  170. #endif
  171. writeb(dfsr, &base->dfsrr); /* set default filter */
  172. writeb(fdr, &base->fdr); /* set bus speed */
  173. #else
  174. uint i;
  175. for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
  176. if (fsl_i2c_speed_map[i].divider >= divider) {
  177. u8 fdr;
  178. fdr = fsl_i2c_speed_map[i].fdr;
  179. speed = i2c_clk / fsl_i2c_speed_map[i].divider;
  180. writeb(fdr, &base->fdr); /* set bus speed */
  181. break;
  182. }
  183. #endif
  184. return speed;
  185. }
  186. #ifndef CONFIG_DM_I2C
  187. static uint get_i2c_clock(int bus)
  188. {
  189. if (bus)
  190. return gd->arch.i2c2_clk; /* I2C2 clock */
  191. else
  192. return gd->arch.i2c1_clk; /* I2C1 clock */
  193. }
  194. #endif
  195. static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
  196. {
  197. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  198. unsigned long long timeval = 0;
  199. int ret = -1;
  200. uint flags = 0;
  201. #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  202. uint svr = get_svr();
  203. if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
  204. (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
  205. flags = I2C_CR_BIT6;
  206. #endif
  207. writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
  208. timeval = get_ticks();
  209. while (!(readb(&base->sr) & I2C_SR_MBB)) {
  210. if ((get_ticks() - timeval) > timeout)
  211. goto err;
  212. }
  213. if (readb(&base->sr) & I2C_SR_MAL) {
  214. /* SDA is stuck low */
  215. writeb(0, &base->cr);
  216. udelay(100);
  217. writeb(I2C_CR_MSTA | flags, &base->cr);
  218. writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
  219. }
  220. readb(&base->dr);
  221. timeval = get_ticks();
  222. while (!(readb(&base->sr) & I2C_SR_MIF)) {
  223. if ((get_ticks() - timeval) > timeout)
  224. goto err;
  225. }
  226. ret = 0;
  227. err:
  228. writeb(I2C_CR_MEN | flags, &base->cr);
  229. writeb(0, &base->sr);
  230. udelay(100);
  231. return ret;
  232. }
  233. static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
  234. slaveadd, int i2c_clk, int busnum)
  235. {
  236. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  237. unsigned long long timeval;
  238. #ifdef CONFIG_SYS_I2C_INIT_BOARD
  239. /* Call board specific i2c bus reset routine before accessing the
  240. * environment, which might be in a chip on that bus. For details
  241. * about this problem see doc/I2C_Edge_Conditions.
  242. */
  243. i2c_init_board();
  244. #endif
  245. writeb(0, &base->cr); /* stop I2C controller */
  246. udelay(5); /* let it shutdown in peace */
  247. set_i2c_bus_speed(base, i2c_clk, speed);
  248. writeb(slaveadd << 1, &base->adr);/* write slave address */
  249. writeb(0x0, &base->sr); /* clear status register */
  250. writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
  251. timeval = get_ticks();
  252. while (readb(&base->sr) & I2C_SR_MBB) {
  253. if ((get_ticks() - timeval) < timeout)
  254. continue;
  255. if (fsl_i2c_fixup(base))
  256. debug("i2c_init: BUS#%d failed to init\n",
  257. busnum);
  258. break;
  259. }
  260. }
  261. static int i2c_wait4bus(const struct fsl_i2c_base *base)
  262. {
  263. unsigned long long timeval = get_ticks();
  264. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  265. while (readb(&base->sr) & I2C_SR_MBB) {
  266. if ((get_ticks() - timeval) > timeout)
  267. return -1;
  268. }
  269. return 0;
  270. }
  271. static int i2c_wait(const struct fsl_i2c_base *base, int write)
  272. {
  273. u32 csr;
  274. unsigned long long timeval = get_ticks();
  275. const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
  276. do {
  277. csr = readb(&base->sr);
  278. if (!(csr & I2C_SR_MIF))
  279. continue;
  280. /* Read again to allow register to stabilise */
  281. csr = readb(&base->sr);
  282. writeb(0x0, &base->sr);
  283. if (csr & I2C_SR_MAL) {
  284. debug("%s: MAL\n", __func__);
  285. return -1;
  286. }
  287. if (!(csr & I2C_SR_MCF)) {
  288. debug("%s: unfinished\n", __func__);
  289. return -1;
  290. }
  291. if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
  292. debug("%s: No RXACK\n", __func__);
  293. return -1;
  294. }
  295. return 0;
  296. } while ((get_ticks() - timeval) < timeout);
  297. debug("%s: timed out\n", __func__);
  298. return -1;
  299. }
  300. static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
  301. u8 dir, int rsta)
  302. {
  303. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
  304. | (rsta ? I2C_CR_RSTA : 0),
  305. &base->cr);
  306. writeb((dev << 1) | dir, &base->dr);
  307. if (i2c_wait(base, I2C_WRITE_BIT) < 0)
  308. return 0;
  309. return 1;
  310. }
  311. static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
  312. int length)
  313. {
  314. int i;
  315. for (i = 0; i < length; i++) {
  316. writeb(data[i], &base->dr);
  317. if (i2c_wait(base, I2C_WRITE_BIT) < 0)
  318. break;
  319. }
  320. return i;
  321. }
  322. static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
  323. int length)
  324. {
  325. int i;
  326. writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
  327. &base->cr);
  328. /* dummy read */
  329. readb(&base->dr);
  330. for (i = 0; i < length; i++) {
  331. if (i2c_wait(base, I2C_READ_BIT) < 0)
  332. break;
  333. /* Generate ack on last next to last byte */
  334. if (i == length - 2)
  335. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
  336. &base->cr);
  337. /* Do not generate stop on last byte */
  338. if (i == length - 1)
  339. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
  340. &base->cr);
  341. data[i] = readb(&base->dr);
  342. }
  343. return i;
  344. }
  345. static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
  346. int olen, u8 *data, int dlen)
  347. {
  348. int ret = -1; /* signal error */
  349. if (i2c_wait4bus(base) < 0)
  350. return -1;
  351. /* Some drivers use offset lengths in excess of 4 bytes. These drivers
  352. * adhere to the following convention:
  353. * - the offset length is passed as negative (that is, the absolute
  354. * value of olen is the actual offset length)
  355. * - the offset itself is passed in data, which is overwritten by the
  356. * subsequent read operation
  357. */
  358. if (olen < 0) {
  359. if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
  360. ret = __i2c_write_data(base, data, -olen);
  361. if (ret != -olen)
  362. return -1;
  363. if (dlen && i2c_write_addr(base, chip_addr,
  364. I2C_READ_BIT, 1) != 0)
  365. ret = __i2c_read_data(base, data, dlen);
  366. } else {
  367. if ((!dlen || olen > 0) &&
  368. i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
  369. __i2c_write_data(base, offset, olen) == olen)
  370. ret = 0; /* No error so far */
  371. if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
  372. olen ? 1 : 0) != 0)
  373. ret = __i2c_read_data(base, data, dlen);
  374. }
  375. writeb(I2C_CR_MEN, &base->cr);
  376. if (i2c_wait4bus(base)) /* Wait until STOP */
  377. debug("i2c_read: wait4bus timed out\n");
  378. if (ret == dlen)
  379. return 0;
  380. return -1;
  381. }
  382. static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
  383. u8 *offset, int olen, u8 *data, int dlen)
  384. {
  385. int ret = -1; /* signal error */
  386. if (i2c_wait4bus(base) < 0)
  387. return -1;
  388. if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
  389. __i2c_write_data(base, offset, olen) == olen) {
  390. ret = __i2c_write_data(base, data, dlen);
  391. }
  392. writeb(I2C_CR_MEN, &base->cr);
  393. if (i2c_wait4bus(base)) /* Wait until STOP */
  394. debug("i2c_write: wait4bus timed out\n");
  395. if (ret == dlen)
  396. return 0;
  397. return -1;
  398. }
  399. static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
  400. {
  401. /* For unknown reason the controller will ACK when
  402. * probing for a slave with the same address, so skip
  403. * it.
  404. */
  405. if (chip == (readb(&base->adr) >> 1))
  406. return -1;
  407. return __i2c_read(base, chip, 0, 0, NULL, 0);
  408. }
  409. static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
  410. uint speed, int i2c_clk)
  411. {
  412. writeb(0, &base->cr); /* stop controller */
  413. set_i2c_bus_speed(base, i2c_clk, speed);
  414. writeb(I2C_CR_MEN, &base->cr); /* start controller */
  415. return 0;
  416. }
  417. #ifndef CONFIG_DM_I2C
  418. static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  419. {
  420. __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
  421. get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
  422. }
  423. static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
  424. {
  425. return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
  426. }
  427. static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
  428. int olen, u8 *data, int dlen)
  429. {
  430. u8 *o = (u8 *)&offset;
  431. return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
  432. olen, data, dlen);
  433. }
  434. static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
  435. int olen, u8 *data, int dlen)
  436. {
  437. u8 *o = (u8 *)&offset;
  438. return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
  439. olen, data, dlen);
  440. }
  441. static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  442. {
  443. return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
  444. get_i2c_clock(adap->hwadapnr));
  445. }
  446. /*
  447. * Register fsl i2c adapters
  448. */
  449. U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  450. fsl_i2c_write, fsl_i2c_set_bus_speed,
  451. CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
  452. 0)
  453. #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  454. U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  455. fsl_i2c_write, fsl_i2c_set_bus_speed,
  456. CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
  457. 1)
  458. #endif
  459. #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  460. U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  461. fsl_i2c_write, fsl_i2c_set_bus_speed,
  462. CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
  463. 2)
  464. #endif
  465. #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  466. U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  467. fsl_i2c_write, fsl_i2c_set_bus_speed,
  468. CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
  469. 3)
  470. #endif
  471. #else /* CONFIG_DM_I2C */
  472. static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  473. u32 chip_flags)
  474. {
  475. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  476. return __i2c_probe_chip(dev->base, chip_addr);
  477. }
  478. static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
  479. {
  480. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  481. return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
  482. }
  483. static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
  484. {
  485. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  486. struct clk clock;
  487. dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
  488. if (!dev->base)
  489. return -ENOMEM;
  490. dev->index = dev_read_u32_default(bus, "cell-index", -1);
  491. dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
  492. 0x7f);
  493. dev->speed = dev_read_u32_default(bus, "clock-frequency",
  494. I2C_SPEED_FAST_RATE);
  495. if (!clk_get_by_index(bus, 0, &clock))
  496. dev->i2c_clk = clk_get_rate(&clock);
  497. else
  498. dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
  499. gd->arch.i2c1_clk;
  500. return 0;
  501. }
  502. static int fsl_i2c_probe(struct udevice *bus)
  503. {
  504. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  505. __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
  506. dev->index);
  507. return 0;
  508. }
  509. static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  510. {
  511. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  512. struct i2c_msg *dmsg, *omsg, dummy;
  513. memset(&dummy, 0, sizeof(struct i2c_msg));
  514. /* We expect either two messages (one with an offset and one with the
  515. * actual data) or one message (just data)
  516. */
  517. if (nmsgs > 2 || nmsgs == 0) {
  518. debug("%s: Only one or two messages are supported.", __func__);
  519. return -1;
  520. }
  521. omsg = nmsgs == 1 ? &dummy : msg;
  522. dmsg = nmsgs == 1 ? msg : msg + 1;
  523. if (dmsg->flags & I2C_M_RD)
  524. return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
  525. dmsg->buf, dmsg->len);
  526. else
  527. return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
  528. dmsg->buf, dmsg->len);
  529. }
  530. static const struct dm_i2c_ops fsl_i2c_ops = {
  531. .xfer = fsl_i2c_xfer,
  532. .probe_chip = fsl_i2c_probe_chip,
  533. .set_bus_speed = fsl_i2c_set_bus_speed,
  534. };
  535. static const struct udevice_id fsl_i2c_ids[] = {
  536. { .compatible = "fsl-i2c", },
  537. { /* sentinel */ }
  538. };
  539. U_BOOT_DRIVER(i2c_fsl) = {
  540. .name = "i2c_fsl",
  541. .id = UCLASS_I2C,
  542. .of_match = fsl_i2c_ids,
  543. .probe = fsl_i2c_probe,
  544. .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
  545. .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
  546. .ops = &fsl_i2c_ops,
  547. };
  548. #endif /* CONFIG_DM_I2C */