ast_i2c.h 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012-2020 ASPEED Technology Inc.
  4. * Copyright 2016 IBM Corporation
  5. * Copyright 2017 Google, Inc.
  6. */
  7. #ifndef __AST_I2C_H_
  8. #define __AST_I2C_H_
  9. struct ast_i2c_regs {
  10. u32 fcr;
  11. u32 cactcr1;
  12. u32 cactcr2;
  13. u32 icr;
  14. u32 isr;
  15. u32 csr;
  16. u32 sdar;
  17. u32 pbcr;
  18. u32 trbbr;
  19. #ifdef CONFIG_ASPEED_AST2500
  20. u32 dma_mbar;
  21. u32 dma_tlr;
  22. #endif
  23. };
  24. /* Device Register Definition */
  25. /* 0x00 : I2CD Function Control Register */
  26. #define I2CD_BUFF_SEL_MASK (0x7 << 20)
  27. #define I2CD_BUFF_SEL(x) (x << 20)
  28. #define I2CD_M_SDA_LOCK_EN (0x1 << 16)
  29. #define I2CD_MULTI_MASTER_DIS (0x1 << 15)
  30. #define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
  31. #define I2CD_MSB_STS (0x1 << 9)
  32. #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
  33. #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
  34. #define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
  35. #define I2CD_DEF_ADDR_EN (0x1 << 5)
  36. #define I2CD_DEF_ALERT_EN (0x1 << 4)
  37. #define I2CD_DEF_ARP_EN (0x1 << 3)
  38. #define I2CD_DEF_GCALL_EN (0x1 << 2)
  39. #define I2CD_SLAVE_EN (0x1 << 1)
  40. #define I2CD_MASTER_EN (0x1)
  41. /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
  42. /* Base register value. These bits are always set by the driver. */
  43. #define I2CD_CACTC_BASE 0xfff00300
  44. #define I2CD_TCKHIGH_SHIFT 16
  45. #define I2CD_TCKLOW_SHIFT 12
  46. #define I2CD_THDDAT_SHIFT 10
  47. #define I2CD_TO_DIV_SHIFT 8
  48. #define I2CD_BASE_DIV_SHIFT 0
  49. /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
  50. #define I2CD_tTIMEOUT 1
  51. #define I2CD_NO_TIMEOUT_CTRL 0
  52. /* 0x0c : I2CD Interrupt Control Register &
  53. * 0x10 : I2CD Interrupt Status Register
  54. *
  55. * These share bit definitions, so use the same values for the enable &
  56. * status bits.
  57. */
  58. #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
  59. #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
  60. #define I2CD_INTR_SMBUS_ALERT (0x1 << 12)
  61. #define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11)
  62. #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10)
  63. #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9)
  64. #define I2CD_INTR_GCALL_ADDR (0x1 << 8)
  65. #define I2CD_INTR_SLAVE_MATCH (0x1 << 7)
  66. #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
  67. #define I2CD_INTR_ABNORMAL (0x1 << 5)
  68. #define I2CD_INTR_NORMAL_STOP (0x1 << 4)
  69. #define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
  70. #define I2CD_INTR_RX_DONE (0x1 << 2)
  71. #define I2CD_INTR_TX_NAK (0x1 << 1)
  72. #define I2CD_INTR_TX_ACK (0x1 << 0)
  73. /* 0x14 : I2CD Command/Status Register */
  74. #define I2CD_SDA_OE (0x1 << 28)
  75. #define I2CD_SDA_O (0x1 << 27)
  76. #define I2CD_SCL_OE (0x1 << 26)
  77. #define I2CD_SCL_O (0x1 << 25)
  78. #define I2CD_TX_TIMING (0x1 << 24)
  79. #define I2CD_TX_STATUS (0x1 << 23)
  80. /* Tx State Machine */
  81. #define I2CD_IDLE 0x0
  82. #define I2CD_MACTIVE 0x8
  83. #define I2CD_MSTART 0x9
  84. #define I2CD_MSTARTR 0xa
  85. #define I2CD_MSTOP 0xb
  86. #define I2CD_MTXD 0xc
  87. #define I2CD_MRXACK 0xd
  88. #define I2CD_MRXD 0xe
  89. #define I2CD_MTXACK 0xf
  90. #define I2CD_SWAIT 0x1
  91. #define I2CD_SRXD 0x4
  92. #define I2CD_STXACK 0x5
  93. #define I2CD_STXD 0x6
  94. #define I2CD_SRXACK 0x7
  95. #define I2CD_RECOVER 0x3
  96. #define I2CD_SCL_LINE_STS (0x1 << 18)
  97. #define I2CD_SDA_LINE_STS (0x1 << 17)
  98. #define I2CD_BUS_BUSY_STS (0x1 << 16)
  99. #define I2CD_SDA_OE_OUT_DIR (0x1 << 15)
  100. #define I2CD_SDA_O_OUT_DIR (0x1 << 14)
  101. #define I2CD_SCL_OE_OUT_DIR (0x1 << 13)
  102. #define I2CD_SCL_O_OUT_DIR (0x1 << 12)
  103. #define I2CD_BUS_RECOVER_CMD (0x1 << 11)
  104. #define I2CD_S_ALT_EN (0x1 << 10)
  105. #define I2CD_RX_DMA_ENABLE (0x1 << 9)
  106. #define I2CD_TX_DMA_ENABLE (0x1 << 8)
  107. /* Command Bit */
  108. #define I2CD_RX_BUFF_ENABLE (0x1 << 7)
  109. #define I2CD_TX_BUFF_ENABLE (0x1 << 6)
  110. #define I2CD_M_STOP_CMD (0x1 << 5)
  111. #define I2CD_M_S_RX_CMD_LAST (0x1 << 4)
  112. #define I2CD_M_RX_CMD (0x1 << 3)
  113. #define I2CD_S_TX_CMD (0x1 << 2)
  114. #define I2CD_M_TX_CMD (0x1 << 1)
  115. #define I2CD_M_START_CMD 0x1
  116. #define I2CD_RX_DATA_SHIFT 8
  117. #define I2CD_RX_DATA_MASK (0xff << I2CD_RX_DATA_SHIFT)
  118. #endif /* __AST_I2C_H_ */