xilinx_gpio.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2013 - 2018 Xilinx, Michal Simek
  4. */
  5. #include <common.h>
  6. #include <errno.h>
  7. #include <log.h>
  8. #include <malloc.h>
  9. #include <linux/list.h>
  10. #include <asm/io.h>
  11. #include <asm/gpio.h>
  12. #include <dm.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. #define XILINX_GPIO_MAX_BANK 2
  15. /* Gpio simple map */
  16. struct gpio_regs {
  17. u32 gpiodata;
  18. u32 gpiodir;
  19. };
  20. struct xilinx_gpio_platdata {
  21. struct gpio_regs *regs;
  22. int bank_max[XILINX_GPIO_MAX_BANK];
  23. int bank_input[XILINX_GPIO_MAX_BANK];
  24. int bank_output[XILINX_GPIO_MAX_BANK];
  25. u32 dout_default[XILINX_GPIO_MAX_BANK];
  26. };
  27. struct xilinx_gpio_privdata {
  28. u32 output_val[XILINX_GPIO_MAX_BANK];
  29. };
  30. static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
  31. u32 *bank_pin_num, struct udevice *dev)
  32. {
  33. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  34. u32 bank, max_pins;
  35. /* the first gpio is 0 not 1 */
  36. u32 pin_num = offset;
  37. for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
  38. max_pins = platdata->bank_max[bank];
  39. if (pin_num < max_pins) {
  40. debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
  41. bank, pin_num);
  42. *bank_num = bank;
  43. *bank_pin_num = pin_num;
  44. return 0;
  45. }
  46. pin_num -= max_pins;
  47. }
  48. return -EINVAL;
  49. }
  50. static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
  51. int value)
  52. {
  53. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  54. struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
  55. int val, ret;
  56. u32 bank, pin;
  57. ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
  58. if (ret)
  59. return ret;
  60. val = priv->output_val[bank];
  61. debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
  62. __func__, (ulong)platdata->regs, value, offset, bank, pin, val);
  63. if (value)
  64. val = val | (1 << pin);
  65. else
  66. val = val & ~(1 << pin);
  67. writel(val, &platdata->regs->gpiodata + bank * 2);
  68. priv->output_val[bank] = val;
  69. return 0;
  70. };
  71. static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
  72. {
  73. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  74. struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
  75. int val, ret;
  76. u32 bank, pin;
  77. ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
  78. if (ret)
  79. return ret;
  80. debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
  81. (ulong)platdata->regs, offset, bank, pin);
  82. if (platdata->bank_output[bank]) {
  83. debug("%s: Read saved output value\n", __func__);
  84. val = priv->output_val[bank];
  85. } else {
  86. debug("%s: Read input value from reg\n", __func__);
  87. val = readl(&platdata->regs->gpiodata + bank * 2);
  88. }
  89. val = !!(val & (1 << pin));
  90. return val;
  91. };
  92. static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
  93. {
  94. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  95. int val, ret;
  96. u32 bank, pin;
  97. ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
  98. if (ret)
  99. return ret;
  100. /* Check if all pins are inputs */
  101. if (platdata->bank_input[bank])
  102. return GPIOF_INPUT;
  103. /* Check if all pins are outputs */
  104. if (platdata->bank_output[bank])
  105. return GPIOF_OUTPUT;
  106. /* FIXME test on dual */
  107. val = readl(&platdata->regs->gpiodir + bank * 2);
  108. val = !(val & (1 << pin));
  109. /* input is 1 in reg but GPIOF_INPUT is 0 */
  110. /* output is 0 in reg but GPIOF_OUTPUT is 1 */
  111. return val;
  112. }
  113. static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
  114. int value)
  115. {
  116. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  117. int val, ret;
  118. u32 bank, pin;
  119. ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
  120. if (ret)
  121. return ret;
  122. /* can't change it if all is input by default */
  123. if (platdata->bank_input[bank])
  124. return -EINVAL;
  125. xilinx_gpio_set_value(dev, offset, value);
  126. if (!platdata->bank_output[bank]) {
  127. val = readl(&platdata->regs->gpiodir + bank * 2);
  128. val = val & ~(1 << pin);
  129. writel(val, &platdata->regs->gpiodir + bank * 2);
  130. }
  131. return 0;
  132. }
  133. static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
  134. {
  135. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  136. int val, ret;
  137. u32 bank, pin;
  138. ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
  139. if (ret)
  140. return ret;
  141. /* Already input */
  142. if (platdata->bank_input[bank])
  143. return 0;
  144. /* can't change it if all is output by default */
  145. if (platdata->bank_output[bank])
  146. return -EINVAL;
  147. val = readl(&platdata->regs->gpiodir + bank * 2);
  148. val = val | (1 << pin);
  149. writel(val, &platdata->regs->gpiodir + bank * 2);
  150. return 0;
  151. }
  152. static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
  153. struct ofnode_phandle_args *args)
  154. {
  155. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  156. desc->offset = args->args[0];
  157. debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
  158. args->args_count, args->args[0], args->args[1], args->args[2]);
  159. /*
  160. * The second cell is channel offset:
  161. * 0 is first channel, 8 is second channel
  162. *
  163. * U-Boot driver just combine channels together that's why simply
  164. * add amount of pins in second channel if present.
  165. */
  166. if (args->args[1]) {
  167. if (!platdata->bank_max[1]) {
  168. printf("%s: %s has no second channel\n",
  169. __func__, dev->name);
  170. return -EINVAL;
  171. }
  172. desc->offset += platdata->bank_max[0];
  173. }
  174. /* The third cell is optional */
  175. if (args->args_count > 2)
  176. desc->flags = (args->args[2] &
  177. GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
  178. debug("%s: offset %x, flags %lx\n",
  179. __func__, desc->offset, desc->flags);
  180. return 0;
  181. }
  182. static const struct dm_gpio_ops xilinx_gpio_ops = {
  183. .direction_input = xilinx_gpio_direction_input,
  184. .direction_output = xilinx_gpio_direction_output,
  185. .get_value = xilinx_gpio_get_value,
  186. .set_value = xilinx_gpio_set_value,
  187. .get_function = xilinx_gpio_get_function,
  188. .xlate = xilinx_gpio_xlate,
  189. };
  190. static int xilinx_gpio_probe(struct udevice *dev)
  191. {
  192. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  193. struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
  194. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  195. const void *label_ptr;
  196. label_ptr = dev_read_prop(dev, "label", NULL);
  197. if (label_ptr) {
  198. uc_priv->bank_name = strdup(label_ptr);
  199. if (!uc_priv->bank_name)
  200. return -ENOMEM;
  201. } else {
  202. uc_priv->bank_name = dev->name;
  203. }
  204. uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
  205. priv->output_val[0] = platdata->dout_default[0];
  206. if (platdata->bank_max[1])
  207. priv->output_val[1] = platdata->dout_default[1];
  208. return 0;
  209. }
  210. static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
  211. {
  212. struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
  213. int is_dual;
  214. platdata->regs = (struct gpio_regs *)dev_read_addr(dev);
  215. platdata->bank_max[0] = dev_read_u32_default(dev,
  216. "xlnx,gpio-width", 0);
  217. platdata->bank_input[0] = dev_read_u32_default(dev,
  218. "xlnx,all-inputs", 0);
  219. platdata->bank_output[0] = dev_read_u32_default(dev,
  220. "xlnx,all-outputs", 0);
  221. platdata->dout_default[0] = dev_read_u32_default(dev,
  222. "xlnx,dout-default",
  223. 0);
  224. is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
  225. if (is_dual) {
  226. platdata->bank_max[1] = dev_read_u32_default(dev,
  227. "xlnx,gpio2-width", 0);
  228. platdata->bank_input[1] = dev_read_u32_default(dev,
  229. "xlnx,all-inputs-2", 0);
  230. platdata->bank_output[1] = dev_read_u32_default(dev,
  231. "xlnx,all-outputs-2", 0);
  232. platdata->dout_default[1] = dev_read_u32_default(dev,
  233. "xlnx,dout-default-2", 0);
  234. }
  235. return 0;
  236. }
  237. static const struct udevice_id xilinx_gpio_ids[] = {
  238. { .compatible = "xlnx,xps-gpio-1.00.a",},
  239. { }
  240. };
  241. U_BOOT_DRIVER(xilinx_gpio) = {
  242. .name = "xlnx_gpio",
  243. .id = UCLASS_GPIO,
  244. .ops = &xilinx_gpio_ops,
  245. .of_match = xilinx_gpio_ids,
  246. .ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
  247. .probe = xilinx_gpio_probe,
  248. .platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
  249. .priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),
  250. };