sh_pfc.c 13 KB

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  1. /*
  2. * Pinmuxed GPIO support for SuperH.
  3. * Copy from linux kernel driver/sh/pfc.c
  4. *
  5. * Copyright (C) 2008 Magnus Damm
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <asm/bitops.h>
  15. #include <asm/io.h>
  16. #include <sh_pfc.h>
  17. #include <linux/bitops.h>
  18. #include <linux/bug.h>
  19. static struct pinmux_info *gpioc;
  20. #define pfc_phys_to_virt(p, a) ((void *)a)
  21. static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
  22. {
  23. if (enum_id < r->begin)
  24. return 0;
  25. if (enum_id > r->end)
  26. return 0;
  27. return 1;
  28. }
  29. static unsigned long gpio_read_raw_reg(void *mapped_reg,
  30. unsigned long reg_width)
  31. {
  32. switch (reg_width) {
  33. case 8:
  34. return readb(mapped_reg);
  35. case 16:
  36. return readw(mapped_reg);
  37. case 32:
  38. return readl(mapped_reg);
  39. }
  40. BUG();
  41. return 0;
  42. }
  43. static void gpio_write_raw_reg(void *mapped_reg,
  44. unsigned long reg_width,
  45. unsigned long data)
  46. {
  47. switch (reg_width) {
  48. case 8:
  49. writeb(data, mapped_reg);
  50. return;
  51. case 16:
  52. writew(data, mapped_reg);
  53. return;
  54. case 32:
  55. writel(data, mapped_reg);
  56. return;
  57. }
  58. BUG();
  59. }
  60. static int gpio_read_bit(struct pinmux_data_reg *dr,
  61. unsigned long offset,
  62. unsigned long in_pos)
  63. {
  64. unsigned long pos;
  65. pos = dr->reg_width - (in_pos + 1);
  66. debug("read_bit: addr = %lx, pos = %ld, r_width = %ld\n",
  67. dr->reg + offset, pos, dr->reg_width);
  68. return (gpio_read_raw_reg(dr->mapped_reg + offset,
  69. dr->reg_width) >> pos) & 1;
  70. }
  71. static void gpio_write_bit(struct pinmux_data_reg *dr,
  72. unsigned long in_pos, unsigned long value)
  73. {
  74. unsigned long pos;
  75. pos = dr->reg_width - (in_pos + 1);
  76. debug("write_bit addr = %lx, value = %d, pos = %ld, "
  77. "r_width = %ld\n",
  78. dr->reg, !!value, pos, dr->reg_width);
  79. if (value)
  80. __set_bit(pos, &dr->reg_shadow);
  81. else
  82. __clear_bit(pos, &dr->reg_shadow);
  83. gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
  84. }
  85. static void config_reg_helper(struct pinmux_info *gpioc,
  86. struct pinmux_cfg_reg *crp,
  87. unsigned long in_pos,
  88. #if 0
  89. void __iomem **mapped_regp,
  90. #else
  91. void **mapped_regp,
  92. #endif
  93. unsigned long *maskp,
  94. unsigned long *posp)
  95. {
  96. int k;
  97. *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
  98. if (crp->field_width) {
  99. *maskp = (1 << crp->field_width) - 1;
  100. *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
  101. } else {
  102. *maskp = (1 << crp->var_field_width[in_pos]) - 1;
  103. *posp = crp->reg_width;
  104. for (k = 0; k <= in_pos; k++)
  105. *posp -= crp->var_field_width[k];
  106. }
  107. }
  108. static int read_config_reg(struct pinmux_info *gpioc,
  109. struct pinmux_cfg_reg *crp,
  110. unsigned long field)
  111. {
  112. void *mapped_reg;
  113. unsigned long mask, pos;
  114. config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
  115. debug("read_reg: addr = %lx, field = %ld, "
  116. "r_width = %ld, f_width = %ld\n",
  117. crp->reg, field, crp->reg_width, crp->field_width);
  118. return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
  119. }
  120. static void write_config_reg(struct pinmux_info *gpioc,
  121. struct pinmux_cfg_reg *crp,
  122. unsigned long field, unsigned long value)
  123. {
  124. void *mapped_reg;
  125. unsigned long mask, pos, data;
  126. config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
  127. debug("write_reg addr = %lx, value = %ld, field = %ld, "
  128. "r_width = %ld, f_width = %ld\n",
  129. crp->reg, value, field, crp->reg_width, crp->field_width);
  130. mask = ~(mask << pos);
  131. value = value << pos;
  132. data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
  133. data &= mask;
  134. data |= value;
  135. if (gpioc->unlock_reg)
  136. gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
  137. 32, ~data);
  138. gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
  139. }
  140. static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
  141. {
  142. struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
  143. struct pinmux_data_reg *data_reg;
  144. int k, n;
  145. if (!enum_in_range(gpiop->enum_id, &gpioc->data))
  146. return -1;
  147. k = 0;
  148. while (1) {
  149. data_reg = gpioc->data_regs + k;
  150. if (!data_reg->reg_width)
  151. break;
  152. data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
  153. for (n = 0; n < data_reg->reg_width; n++) {
  154. if (data_reg->enum_ids[n] == gpiop->enum_id) {
  155. gpiop->flags &= ~PINMUX_FLAG_DREG;
  156. gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
  157. gpiop->flags &= ~PINMUX_FLAG_DBIT;
  158. gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
  159. return 0;
  160. }
  161. }
  162. k++;
  163. }
  164. BUG();
  165. return -1;
  166. }
  167. static void setup_data_regs(struct pinmux_info *gpioc)
  168. {
  169. struct pinmux_data_reg *drp;
  170. int k;
  171. for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
  172. setup_data_reg(gpioc, k);
  173. k = 0;
  174. while (1) {
  175. drp = gpioc->data_regs + k;
  176. if (!drp->reg_width)
  177. break;
  178. drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
  179. drp->reg_width);
  180. k++;
  181. }
  182. }
  183. static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
  184. struct pinmux_data_reg **drp, int *bitp)
  185. {
  186. struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
  187. int k, n;
  188. if (!enum_in_range(gpiop->enum_id, &gpioc->data))
  189. return -1;
  190. k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
  191. n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
  192. *drp = gpioc->data_regs + k;
  193. *bitp = n;
  194. return 0;
  195. }
  196. static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
  197. struct pinmux_cfg_reg **crp,
  198. int *fieldp, int *valuep,
  199. unsigned long **cntp)
  200. {
  201. struct pinmux_cfg_reg *config_reg;
  202. unsigned long r_width, f_width, curr_width, ncomb;
  203. int k, m, n, pos, bit_pos;
  204. k = 0;
  205. while (1) {
  206. config_reg = gpioc->cfg_regs + k;
  207. r_width = config_reg->reg_width;
  208. f_width = config_reg->field_width;
  209. if (!r_width)
  210. break;
  211. pos = 0;
  212. m = 0;
  213. for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
  214. if (f_width)
  215. curr_width = f_width;
  216. else
  217. curr_width = config_reg->var_field_width[m];
  218. ncomb = 1 << curr_width;
  219. for (n = 0; n < ncomb; n++) {
  220. if (config_reg->enum_ids[pos + n] == enum_id) {
  221. *crp = config_reg;
  222. *fieldp = m;
  223. *valuep = n;
  224. *cntp = &config_reg->cnt[m];
  225. return 0;
  226. }
  227. }
  228. pos += ncomb;
  229. m++;
  230. }
  231. k++;
  232. }
  233. return -1;
  234. }
  235. static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
  236. int pos, pinmux_enum_t *enum_idp)
  237. {
  238. pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
  239. pinmux_enum_t *data = gpioc->gpio_data;
  240. int k;
  241. if (!enum_in_range(enum_id, &gpioc->data)) {
  242. if (!enum_in_range(enum_id, &gpioc->mark)) {
  243. debug("non data/mark enum_id for gpio %d\n", gpio);
  244. return -1;
  245. }
  246. }
  247. if (pos) {
  248. *enum_idp = data[pos + 1];
  249. return pos + 1;
  250. }
  251. for (k = 0; k < gpioc->gpio_data_size; k++) {
  252. if (data[k] == enum_id) {
  253. *enum_idp = data[k + 1];
  254. return k + 1;
  255. }
  256. }
  257. debug("cannot locate data/mark enum_id for gpio %d\n", gpio);
  258. return -1;
  259. }
  260. enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
  261. static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
  262. int pinmux_type, int cfg_mode)
  263. {
  264. struct pinmux_cfg_reg *cr = NULL;
  265. pinmux_enum_t enum_id;
  266. struct pinmux_range *range;
  267. int in_range, pos, field, value;
  268. unsigned long *cntp;
  269. switch (pinmux_type) {
  270. case PINMUX_TYPE_FUNCTION:
  271. range = NULL;
  272. break;
  273. case PINMUX_TYPE_OUTPUT:
  274. range = &gpioc->output;
  275. break;
  276. case PINMUX_TYPE_INPUT:
  277. range = &gpioc->input;
  278. break;
  279. case PINMUX_TYPE_INPUT_PULLUP:
  280. range = &gpioc->input_pu;
  281. break;
  282. case PINMUX_TYPE_INPUT_PULLDOWN:
  283. range = &gpioc->input_pd;
  284. break;
  285. default:
  286. goto out_err;
  287. }
  288. pos = 0;
  289. enum_id = 0;
  290. field = 0;
  291. value = 0;
  292. while (1) {
  293. pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
  294. if (pos <= 0)
  295. goto out_err;
  296. if (!enum_id)
  297. break;
  298. /* first check if this is a function enum */
  299. in_range = enum_in_range(enum_id, &gpioc->function);
  300. if (!in_range) {
  301. /* not a function enum */
  302. if (range) {
  303. /*
  304. * other range exists, so this pin is
  305. * a regular GPIO pin that now is being
  306. * bound to a specific direction.
  307. *
  308. * for this case we only allow function enums
  309. * and the enums that match the other range.
  310. */
  311. in_range = enum_in_range(enum_id, range);
  312. /*
  313. * special case pass through for fixed
  314. * input-only or output-only pins without
  315. * function enum register association.
  316. */
  317. if (in_range && enum_id == range->force)
  318. continue;
  319. } else {
  320. /*
  321. * no other range exists, so this pin
  322. * must then be of the function type.
  323. *
  324. * allow function type pins to select
  325. * any combination of function/in/out
  326. * in their MARK lists.
  327. */
  328. in_range = 1;
  329. }
  330. }
  331. if (!in_range)
  332. continue;
  333. if (get_config_reg(gpioc, enum_id, &cr,
  334. &field, &value, &cntp) != 0)
  335. goto out_err;
  336. switch (cfg_mode) {
  337. case GPIO_CFG_DRYRUN:
  338. if (!*cntp ||
  339. (read_config_reg(gpioc, cr, field) != value))
  340. continue;
  341. break;
  342. case GPIO_CFG_REQ:
  343. write_config_reg(gpioc, cr, field, value);
  344. *cntp = *cntp + 1;
  345. break;
  346. case GPIO_CFG_FREE:
  347. *cntp = *cntp - 1;
  348. break;
  349. }
  350. }
  351. return 0;
  352. out_err:
  353. return -1;
  354. }
  355. #if 0
  356. static DEFINE_SPINLOCK(gpio_lock);
  357. static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
  358. {
  359. return container_of(chip, struct pinmux_info, chip);
  360. }
  361. #endif
  362. static int sh_gpio_request(unsigned offset)
  363. {
  364. struct pinmux_data_reg *dummy;
  365. int i, ret, pinmux_type;
  366. ret = -1;
  367. if (!gpioc)
  368. goto err_out;
  369. if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
  370. goto err_out;
  371. /* setup pin function here if no data is associated with pin */
  372. if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
  373. pinmux_type = PINMUX_TYPE_FUNCTION;
  374. else
  375. pinmux_type = PINMUX_TYPE_GPIO;
  376. if (pinmux_type == PINMUX_TYPE_FUNCTION) {
  377. if (pinmux_config_gpio(gpioc, offset,
  378. pinmux_type,
  379. GPIO_CFG_DRYRUN) != 0)
  380. goto err_out;
  381. if (pinmux_config_gpio(gpioc, offset,
  382. pinmux_type,
  383. GPIO_CFG_REQ) != 0)
  384. BUG();
  385. }
  386. gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
  387. gpioc->gpios[offset].flags |= pinmux_type;
  388. ret = 0;
  389. err_out:
  390. return ret;
  391. }
  392. static void sh_gpio_free(unsigned offset)
  393. {
  394. int pinmux_type;
  395. if (!gpioc)
  396. return;
  397. pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
  398. pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
  399. gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
  400. gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
  401. }
  402. static int pinmux_direction(struct pinmux_info *gpioc,
  403. unsigned gpio, int new_pinmux_type)
  404. {
  405. int pinmux_type;
  406. int ret = -1;
  407. if (!gpioc)
  408. goto err_out;
  409. pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
  410. switch (pinmux_type) {
  411. case PINMUX_TYPE_GPIO:
  412. break;
  413. case PINMUX_TYPE_OUTPUT:
  414. case PINMUX_TYPE_INPUT:
  415. case PINMUX_TYPE_INPUT_PULLUP:
  416. case PINMUX_TYPE_INPUT_PULLDOWN:
  417. pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
  418. break;
  419. default:
  420. goto err_out;
  421. }
  422. if (pinmux_config_gpio(gpioc, gpio,
  423. new_pinmux_type,
  424. GPIO_CFG_DRYRUN) != 0)
  425. goto err_out;
  426. if (pinmux_config_gpio(gpioc, gpio,
  427. new_pinmux_type,
  428. GPIO_CFG_REQ) != 0)
  429. BUG();
  430. gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
  431. gpioc->gpios[gpio].flags |= new_pinmux_type;
  432. ret = 0;
  433. err_out:
  434. return ret;
  435. }
  436. static int sh_gpio_direction_input(unsigned offset)
  437. {
  438. return pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
  439. }
  440. static void sh_gpio_set_value(struct pinmux_info *gpioc,
  441. unsigned gpio, int value)
  442. {
  443. struct pinmux_data_reg *dr = NULL;
  444. int bit = 0;
  445. if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
  446. BUG();
  447. else
  448. gpio_write_bit(dr, bit, value);
  449. }
  450. static int sh_gpio_direction_output(unsigned offset, int value)
  451. {
  452. sh_gpio_set_value(gpioc, offset, value);
  453. return pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
  454. }
  455. static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
  456. {
  457. struct pinmux_data_reg *dr = NULL;
  458. int bit = 0, offset = 0;
  459. if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
  460. return -1;
  461. #if defined(CONFIG_RCAR_GEN3)
  462. if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT)
  463. offset += 4;
  464. #endif
  465. return gpio_read_bit(dr, offset, bit);
  466. }
  467. static int sh_gpio_get(unsigned offset)
  468. {
  469. return sh_gpio_get_value(gpioc, offset);
  470. }
  471. static void sh_gpio_set(unsigned offset, int value)
  472. {
  473. sh_gpio_set_value(gpioc, offset, value);
  474. }
  475. int register_pinmux(struct pinmux_info *pip)
  476. {
  477. if (pip != NULL) {
  478. gpioc = pip;
  479. debug("%s deregistering\n", pip->name);
  480. setup_data_regs(gpioc);
  481. }
  482. return 0;
  483. }
  484. int unregister_pinmux(struct pinmux_info *pip)
  485. {
  486. debug("%s deregistering\n", pip->name);
  487. if (gpioc != pip)
  488. return -1;
  489. gpioc = NULL;
  490. return 0;
  491. }
  492. int gpio_request(unsigned gpio, const char *label)
  493. {
  494. sh_gpio_request(gpio);
  495. return 0;
  496. }
  497. int gpio_free(unsigned gpio)
  498. {
  499. sh_gpio_free(gpio);
  500. return 0;
  501. }
  502. int gpio_direction_input(unsigned gpio)
  503. {
  504. return sh_gpio_direction_input(gpio);
  505. }
  506. int gpio_direction_output(unsigned gpio, int value)
  507. {
  508. return sh_gpio_direction_output(gpio, value);
  509. }
  510. void gpio_set_value(unsigned gpio, int value)
  511. {
  512. sh_gpio_set(gpio, value);
  513. }
  514. int gpio_get_value(unsigned gpio)
  515. {
  516. return sh_gpio_get(gpio);
  517. }