pca953x_gpio.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
  4. *
  5. * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
  6. *
  7. */
  8. /*
  9. * Note:
  10. * The driver's compatible table is borrowed from Linux Kernel,
  11. * but now max supported gpio pins is 24 and only PCA953X_TYPE
  12. * is supported. PCA957X_TYPE is not supported now.
  13. * Also the Polarity Inversion feature is not supported now.
  14. *
  15. * TODO:
  16. * 1. Support PCA957X_TYPE
  17. * 2. Support Polarity Inversion
  18. */
  19. #include <common.h>
  20. #include <errno.h>
  21. #include <dm.h>
  22. #include <fdtdec.h>
  23. #include <i2c.h>
  24. #include <malloc.h>
  25. #include <asm/gpio.h>
  26. #include <asm/io.h>
  27. #include <dm/device_compat.h>
  28. #include <dt-bindings/gpio/gpio.h>
  29. #include <linux/bitops.h>
  30. #define PCA953X_INPUT 0
  31. #define PCA953X_OUTPUT 1
  32. #define PCA953X_INVERT 2
  33. #define PCA953X_DIRECTION 3
  34. #define PCA_GPIO_MASK 0x00FF
  35. #define PCA_INT 0x0100
  36. #define PCA953X_TYPE 0x1000
  37. #define PCA957X_TYPE 0x2000
  38. #define PCA_TYPE_MASK 0xF000
  39. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  40. enum {
  41. PCA953X_DIRECTION_IN,
  42. PCA953X_DIRECTION_OUT,
  43. };
  44. #define MAX_BANK 5
  45. #define BANK_SZ 8
  46. /*
  47. * struct pca953x_info - Data for pca953x
  48. *
  49. * @dev: udevice structure for the device
  50. * @addr: i2c slave address
  51. * @invert: Polarity inversion or not
  52. * @gpio_count: the number of gpio pins that the device supports
  53. * @chip_type: indicate the chip type,PCA953X or PCA957X
  54. * @bank_count: the number of banks that the device supports
  55. * @reg_output: array to hold the value of output registers
  56. * @reg_direction: array to hold the value of direction registers
  57. */
  58. struct pca953x_info {
  59. struct udevice *dev;
  60. int addr;
  61. int invert;
  62. int gpio_count;
  63. int chip_type;
  64. int bank_count;
  65. u8 reg_output[MAX_BANK];
  66. u8 reg_direction[MAX_BANK];
  67. };
  68. static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
  69. int offset)
  70. {
  71. struct pca953x_info *info = dev_get_platdata(dev);
  72. int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
  73. int off = offset / BANK_SZ;
  74. int ret = 0;
  75. ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1);
  76. if (ret) {
  77. dev_err(dev, "%s error\n", __func__);
  78. return ret;
  79. }
  80. return 0;
  81. }
  82. static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
  83. int offset)
  84. {
  85. struct pca953x_info *info = dev_get_platdata(dev);
  86. int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
  87. int off = offset / BANK_SZ;
  88. int ret;
  89. u8 byte;
  90. ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1);
  91. if (ret) {
  92. dev_err(dev, "%s error\n", __func__);
  93. return ret;
  94. }
  95. *val = byte;
  96. return 0;
  97. }
  98. static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
  99. {
  100. struct pca953x_info *info = dev_get_platdata(dev);
  101. int ret = 0;
  102. if (info->gpio_count <= 8) {
  103. ret = dm_i2c_read(dev, reg, val, 1);
  104. } else if (info->gpio_count <= 16) {
  105. ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
  106. } else if (info->gpio_count <= 24) {
  107. /* Auto increment */
  108. ret = dm_i2c_read(dev, (reg << 2) | 0x80, val,
  109. info->bank_count);
  110. } else if (info->gpio_count == 40) {
  111. /* Auto increment */
  112. ret = dm_i2c_read(dev, (reg << 3) | 0x80, val,
  113. info->bank_count);
  114. } else {
  115. dev_err(dev, "Unsupported now\n");
  116. return -EINVAL;
  117. }
  118. return ret;
  119. }
  120. static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val)
  121. {
  122. struct pca953x_info *info = dev_get_platdata(dev);
  123. int ret = 0;
  124. if (info->gpio_count <= 8) {
  125. ret = dm_i2c_write(dev, reg, val, 1);
  126. } else if (info->gpio_count <= 16) {
  127. ret = dm_i2c_write(dev, reg << 1, val, info->bank_count);
  128. } else if (info->gpio_count <= 24) {
  129. /* Auto increment */
  130. ret = dm_i2c_write(dev, (reg << 2) | 0x80, val,
  131. info->bank_count);
  132. } else if (info->gpio_count == 40) {
  133. /* Auto increment */
  134. ret = dm_i2c_write(dev, (reg << 3) | 0x80, val, info->bank_count);
  135. } else {
  136. return -EINVAL;
  137. }
  138. return ret;
  139. }
  140. static int pca953x_is_output(struct udevice *dev, int offset)
  141. {
  142. struct pca953x_info *info = dev_get_platdata(dev);
  143. int bank = offset / BANK_SZ;
  144. int off = offset % BANK_SZ;
  145. /*0: output; 1: input */
  146. return !(info->reg_direction[bank] & (1 << off));
  147. }
  148. static int pca953x_get_value(struct udevice *dev, uint offset)
  149. {
  150. int ret;
  151. u8 val = 0;
  152. int off = offset % BANK_SZ;
  153. ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
  154. if (ret)
  155. return ret;
  156. return (val >> off) & 0x1;
  157. }
  158. static int pca953x_set_value(struct udevice *dev, uint offset, int value)
  159. {
  160. struct pca953x_info *info = dev_get_platdata(dev);
  161. int bank = offset / BANK_SZ;
  162. int off = offset % BANK_SZ;
  163. u8 val;
  164. int ret;
  165. if (value)
  166. val = info->reg_output[bank] | (1 << off);
  167. else
  168. val = info->reg_output[bank] & ~(1 << off);
  169. ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
  170. if (ret)
  171. return ret;
  172. info->reg_output[bank] = val;
  173. return 0;
  174. }
  175. static int pca953x_set_direction(struct udevice *dev, uint offset, int dir)
  176. {
  177. struct pca953x_info *info = dev_get_platdata(dev);
  178. int bank = offset / BANK_SZ;
  179. int off = offset % BANK_SZ;
  180. u8 val;
  181. int ret;
  182. if (dir == PCA953X_DIRECTION_IN)
  183. val = info->reg_direction[bank] | (1 << off);
  184. else
  185. val = info->reg_direction[bank] & ~(1 << off);
  186. ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
  187. if (ret)
  188. return ret;
  189. info->reg_direction[bank] = val;
  190. return 0;
  191. }
  192. static int pca953x_direction_input(struct udevice *dev, uint offset)
  193. {
  194. return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
  195. }
  196. static int pca953x_direction_output(struct udevice *dev, uint offset, int value)
  197. {
  198. /* Configure output value. */
  199. pca953x_set_value(dev, offset, value);
  200. /* Configure direction as output. */
  201. pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT);
  202. return 0;
  203. }
  204. static int pca953x_get_function(struct udevice *dev, uint offset)
  205. {
  206. if (pca953x_is_output(dev, offset))
  207. return GPIOF_OUTPUT;
  208. else
  209. return GPIOF_INPUT;
  210. }
  211. static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc,
  212. struct ofnode_phandle_args *args)
  213. {
  214. desc->offset = args->args[0];
  215. desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
  216. return 0;
  217. }
  218. static const struct dm_gpio_ops pca953x_ops = {
  219. .direction_input = pca953x_direction_input,
  220. .direction_output = pca953x_direction_output,
  221. .get_value = pca953x_get_value,
  222. .set_value = pca953x_set_value,
  223. .get_function = pca953x_get_function,
  224. .xlate = pca953x_xlate,
  225. };
  226. static int pca953x_probe(struct udevice *dev)
  227. {
  228. struct pca953x_info *info = dev_get_platdata(dev);
  229. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  230. char name[32], label[8], *str;
  231. int addr;
  232. ulong driver_data;
  233. int ret;
  234. int size;
  235. const u8 *tmp;
  236. u8 val[MAX_BANK];
  237. addr = dev_read_addr(dev);
  238. if (addr == 0)
  239. return -ENODEV;
  240. info->addr = addr;
  241. driver_data = dev_get_driver_data(dev);
  242. info->gpio_count = driver_data & PCA_GPIO_MASK;
  243. if (info->gpio_count > MAX_BANK * BANK_SZ) {
  244. dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
  245. return -EINVAL;
  246. }
  247. info->chip_type = PCA_CHIP_TYPE(driver_data);
  248. if (info->chip_type != PCA953X_TYPE) {
  249. dev_err(dev, "Only support PCA953X chip type now.\n");
  250. return -EINVAL;
  251. }
  252. info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
  253. ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
  254. if (ret) {
  255. dev_err(dev, "Error reading output register\n");
  256. return ret;
  257. }
  258. ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
  259. if (ret) {
  260. dev_err(dev, "Error reading direction register\n");
  261. return ret;
  262. }
  263. tmp = dev_read_prop(dev, "label", &size);
  264. if (tmp) {
  265. memcpy(label, tmp, sizeof(label) - 1);
  266. label[sizeof(label) - 1] = '\0';
  267. snprintf(name, sizeof(name), "%s@%x_", label, info->addr);
  268. } else {
  269. snprintf(name, sizeof(name), "gpio@%x_", info->addr);
  270. }
  271. /* Clear the polarity registers to no invert */
  272. memset(val, 0, MAX_BANK);
  273. ret = pca953x_write_regs(dev, PCA953X_INVERT, val);
  274. if (ret < 0) {
  275. dev_err(dev, "Error writing invert register\n");
  276. return ret;
  277. }
  278. str = strdup(name);
  279. if (!str)
  280. return -ENOMEM;
  281. uc_priv->bank_name = str;
  282. uc_priv->gpio_count = info->gpio_count;
  283. dev_dbg(dev, "%s is ready\n", str);
  284. return 0;
  285. }
  286. #define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int)
  287. #define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int)
  288. static const struct udevice_id pca953x_ids[] = {
  289. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  290. { .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), },
  291. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  292. { .compatible = "nxp,pca9536", .data = OF_953X(4, 0), },
  293. { .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), },
  294. { .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), },
  295. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  296. { .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), },
  297. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  298. { .compatible = "nxp,pca9556", .data = OF_953X(8, 0), },
  299. { .compatible = "nxp,pca9557", .data = OF_953X(8, 0), },
  300. { .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), },
  301. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  302. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  303. { .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
  304. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  305. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  306. { .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), },
  307. { .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), },
  308. { .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
  309. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  310. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  311. { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
  312. { .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
  313. { .compatible = "exar,xra1202", .data = OF_953X(8, 0), },
  314. { }
  315. };
  316. U_BOOT_DRIVER(pca953x) = {
  317. .name = "pca953x",
  318. .id = UCLASS_GPIO,
  319. .ops = &pca953x_ops,
  320. .probe = pca953x_probe,
  321. .platdata_auto_alloc_size = sizeof(struct pca953x_info),
  322. .of_match = pca953x_ids,
  323. };