mxs_gpio.c 7.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 GPIO control code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <linux/bitops.h>
  12. #include <linux/errno.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/imx-regs.h>
  16. #if defined(CONFIG_MX23)
  17. #define PINCTRL_BANKS 3
  18. #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
  19. #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
  20. #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
  21. #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
  22. #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
  23. #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
  24. #elif defined(CONFIG_MX28)
  25. #define PINCTRL_BANKS 5
  26. #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
  27. #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
  28. #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
  29. #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
  30. #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
  31. #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
  32. #else
  33. #error "Please select CONFIG_MX23 or CONFIG_MX28"
  34. #endif
  35. #define GPIO_INT_FALL_EDGE 0x0
  36. #define GPIO_INT_LOW_LEV 0x1
  37. #define GPIO_INT_RISE_EDGE 0x2
  38. #define GPIO_INT_HIGH_LEV 0x3
  39. #define GPIO_INT_LEV_MASK (1 << 0)
  40. #define GPIO_INT_POL_MASK (1 << 1)
  41. void mxs_gpio_init(void)
  42. {
  43. int i;
  44. for (i = 0; i < PINCTRL_BANKS; i++) {
  45. writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
  46. writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
  47. /* Use SCT address here to clear the IRQSTAT bits */
  48. writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
  49. }
  50. }
  51. #if !CONFIG_IS_ENABLED(DM_GPIO)
  52. int gpio_get_value(unsigned gpio)
  53. {
  54. uint32_t bank = PAD_BANK(gpio);
  55. uint32_t offset = PINCTRL_DIN(bank);
  56. struct mxs_register_32 *reg =
  57. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  58. return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
  59. }
  60. void gpio_set_value(unsigned gpio, int value)
  61. {
  62. uint32_t bank = PAD_BANK(gpio);
  63. uint32_t offset = PINCTRL_DOUT(bank);
  64. struct mxs_register_32 *reg =
  65. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  66. if (value)
  67. writel(1 << PAD_PIN(gpio), &reg->reg_set);
  68. else
  69. writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  70. }
  71. int gpio_direction_input(unsigned gpio)
  72. {
  73. uint32_t bank = PAD_BANK(gpio);
  74. uint32_t offset = PINCTRL_DOE(bank);
  75. struct mxs_register_32 *reg =
  76. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  77. writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  78. return 0;
  79. }
  80. int gpio_direction_output(unsigned gpio, int value)
  81. {
  82. uint32_t bank = PAD_BANK(gpio);
  83. uint32_t offset = PINCTRL_DOE(bank);
  84. struct mxs_register_32 *reg =
  85. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  86. gpio_set_value(gpio, value);
  87. writel(1 << PAD_PIN(gpio), &reg->reg_set);
  88. return 0;
  89. }
  90. int gpio_request(unsigned gpio, const char *label)
  91. {
  92. if (PAD_BANK(gpio) >= PINCTRL_BANKS)
  93. return -1;
  94. return 0;
  95. }
  96. int gpio_free(unsigned gpio)
  97. {
  98. return 0;
  99. }
  100. int name_to_gpio(const char *name)
  101. {
  102. unsigned bank, pin;
  103. char *end;
  104. bank = simple_strtoul(name, &end, 10);
  105. if (!*end || *end != ':')
  106. return bank;
  107. pin = simple_strtoul(end + 1, NULL, 10);
  108. return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
  109. }
  110. #else /* DM_GPIO */
  111. #include <dm.h>
  112. #include <asm/gpio.h>
  113. #include <dt-structs.h>
  114. #include <asm/arch/gpio.h>
  115. #define MXS_MAX_GPIO_PER_BANK 32
  116. DECLARE_GLOBAL_DATA_PTR;
  117. /*
  118. * According to i.MX28 Reference Manual:
  119. * 'i.MX28 Applications Processor Reference Manual, Rev. 1, 2010'
  120. * The i.MX28 has following number of GPIOs available:
  121. * Bank 0: 0-28 -> 29 PINS
  122. * Bank 1: 0-31 -> 32 PINS
  123. * Bank 2: 0-27 -> 28 PINS
  124. * Bank 3: 0-30 -> 31 PINS
  125. * Bank 4: 0-20 -> 21 PINS
  126. */
  127. struct mxs_gpio_platdata {
  128. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  129. struct dtd_fsl_imx23_gpio dtplat;
  130. #endif
  131. unsigned int bank;
  132. int gpio_ranges;
  133. };
  134. struct mxs_gpio_priv {
  135. unsigned int bank;
  136. };
  137. static int mxs_gpio_get_value(struct udevice *dev, unsigned offset)
  138. {
  139. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  140. struct mxs_register_32 *reg =
  141. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  142. PINCTRL_DIN(priv->bank));
  143. return (readl(&reg->reg) >> offset) & 1;
  144. }
  145. static int mxs_gpio_set_value(struct udevice *dev, unsigned offset,
  146. int value)
  147. {
  148. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  149. struct mxs_register_32 *reg =
  150. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  151. PINCTRL_DOUT(priv->bank));
  152. if (value)
  153. writel(BIT(offset), &reg->reg_set);
  154. else
  155. writel(BIT(offset), &reg->reg_clr);
  156. return 0;
  157. }
  158. static int mxs_gpio_direction_input(struct udevice *dev, unsigned offset)
  159. {
  160. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  161. struct mxs_register_32 *reg =
  162. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  163. PINCTRL_DOE(priv->bank));
  164. writel(BIT(offset), &reg->reg_clr);
  165. return 0;
  166. }
  167. static int mxs_gpio_direction_output(struct udevice *dev, unsigned offset,
  168. int value)
  169. {
  170. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  171. struct mxs_register_32 *reg =
  172. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  173. PINCTRL_DOE(priv->bank));
  174. mxs_gpio_set_value(dev, offset, value);
  175. writel(BIT(offset), &reg->reg_set);
  176. return 0;
  177. }
  178. static int mxs_gpio_get_function(struct udevice *dev, unsigned offset)
  179. {
  180. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  181. struct mxs_register_32 *reg =
  182. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  183. PINCTRL_DOE(priv->bank));
  184. bool is_output = !!(readl(&reg->reg) >> offset);
  185. return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
  186. }
  187. static const struct dm_gpio_ops gpio_mxs_ops = {
  188. .direction_input = mxs_gpio_direction_input,
  189. .direction_output = mxs_gpio_direction_output,
  190. .get_value = mxs_gpio_get_value,
  191. .set_value = mxs_gpio_set_value,
  192. .get_function = mxs_gpio_get_function,
  193. };
  194. static int mxs_gpio_probe(struct udevice *dev)
  195. {
  196. struct mxs_gpio_platdata *plat = dev_get_platdata(dev);
  197. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  198. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  199. char name[16], *str;
  200. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  201. struct dtd_fsl_imx23_gpio *dtplat = &plat->dtplat;
  202. priv->bank = (unsigned int)dtplat->reg[0];
  203. uc_priv->gpio_count = dtplat->gpio_ranges[3];
  204. #else
  205. priv->bank = (unsigned int)plat->bank;
  206. uc_priv->gpio_count = plat->gpio_ranges;
  207. #endif
  208. snprintf(name, sizeof(name), "GPIO%d_", priv->bank);
  209. str = strdup(name);
  210. if (!str)
  211. return -ENOMEM;
  212. uc_priv->bank_name = str;
  213. debug("%s: %s: %d pins base: 0x%x\n", __func__, uc_priv->bank_name,
  214. uc_priv->gpio_count, priv->bank);
  215. return 0;
  216. }
  217. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  218. static int mxs_ofdata_to_platdata(struct udevice *dev)
  219. {
  220. struct mxs_gpio_platdata *plat = dev->platdata;
  221. struct fdtdec_phandle_args args;
  222. int node = dev_of_offset(dev);
  223. int ret;
  224. plat->bank = dev_read_addr(dev);
  225. if (plat->bank == FDT_ADDR_T_NONE) {
  226. printf("%s: No 'reg' property defined!\n", __func__);
  227. return -EINVAL;
  228. }
  229. ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
  230. NULL, 3, 0, &args);
  231. if (ret)
  232. printf("%s: 'gpio-ranges' not defined - using default!\n",
  233. __func__);
  234. plat->gpio_ranges = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK;
  235. return 0;
  236. }
  237. static const struct udevice_id mxs_gpio_ids[] = {
  238. { .compatible = "fsl,imx23-gpio" },
  239. { .compatible = "fsl,imx28-gpio" },
  240. { }
  241. };
  242. #endif
  243. U_BOOT_DRIVER(fsl_imx23_gpio) = {
  244. .name = "fsl_imx23_gpio",
  245. .id = UCLASS_GPIO,
  246. .ops = &gpio_mxs_ops,
  247. .probe = mxs_gpio_probe,
  248. .priv_auto_alloc_size = sizeof(struct mxs_gpio_priv),
  249. .platdata_auto_alloc_size = sizeof(struct mxs_gpio_platdata),
  250. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  251. .of_match = mxs_gpio_ids,
  252. .ofdata_to_platdata = mxs_ofdata_to_platdata,
  253. #endif
  254. };
  255. U_BOOT_DRIVER_ALIAS(fsl_imx23_gpio, fsl_imx28_gpio)
  256. #endif /* DM_GPIO */