mt7621_gpio.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Stefan Roese <sr@denx.de>
  4. *
  5. * Based on the Linux driver version which is:
  6. * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  7. * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <fdtdec.h>
  13. #include <malloc.h>
  14. #include <linux/bitops.h>
  15. #include <linux/io.h>
  16. #include <asm/io.h>
  17. #include <asm/gpio.h>
  18. #include <dm/device-internal.h>
  19. #include <dt-bindings/gpio/gpio.h>
  20. #define MTK_MAX_BANK 3
  21. #define MTK_BANK_WIDTH 32
  22. enum mediatek_gpio_reg {
  23. GPIO_REG_CTRL = 0,
  24. GPIO_REG_POL,
  25. GPIO_REG_DATA,
  26. GPIO_REG_DSET,
  27. GPIO_REG_DCLR,
  28. GPIO_REG_REDGE,
  29. GPIO_REG_FEDGE,
  30. GPIO_REG_HLVL,
  31. GPIO_REG_LLVL,
  32. GPIO_REG_STAT,
  33. GPIO_REG_EDGE,
  34. };
  35. static void __iomem *mediatek_gpio_membase;
  36. struct mediatek_gpio_platdata {
  37. char bank_name[3]; /* Name of bank, e.g. "PA", "PB" etc */
  38. int gpio_count;
  39. int bank;
  40. };
  41. static u32 reg_offs(struct mediatek_gpio_platdata *plat, int reg)
  42. {
  43. return (reg * 0x10) + (plat->bank * 0x4);
  44. }
  45. static int mediatek_gpio_get_value(struct udevice *dev, unsigned int offset)
  46. {
  47. struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
  48. return !!(ioread32(mediatek_gpio_membase +
  49. reg_offs(plat, GPIO_REG_DATA)) & BIT(offset));
  50. }
  51. static int mediatek_gpio_set_value(struct udevice *dev, unsigned int offset,
  52. int value)
  53. {
  54. struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
  55. iowrite32(BIT(offset), mediatek_gpio_membase +
  56. reg_offs(plat, value ? GPIO_REG_DSET : GPIO_REG_DCLR));
  57. return 0;
  58. }
  59. static int mediatek_gpio_direction_input(struct udevice *dev, unsigned int offset)
  60. {
  61. struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
  62. clrbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
  63. BIT(offset));
  64. return 0;
  65. }
  66. static int mediatek_gpio_direction_output(struct udevice *dev, unsigned int offset,
  67. int value)
  68. {
  69. struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
  70. setbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
  71. BIT(offset));
  72. mediatek_gpio_set_value(dev, offset, value);
  73. return 0;
  74. }
  75. static int mediatek_gpio_get_function(struct udevice *dev, unsigned int offset)
  76. {
  77. struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
  78. u32 t;
  79. t = ioread32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL));
  80. if (t & BIT(offset))
  81. return GPIOF_OUTPUT;
  82. return GPIOF_INPUT;
  83. }
  84. static const struct dm_gpio_ops gpio_mediatek_ops = {
  85. .direction_input = mediatek_gpio_direction_input,
  86. .direction_output = mediatek_gpio_direction_output,
  87. .get_value = mediatek_gpio_get_value,
  88. .set_value = mediatek_gpio_set_value,
  89. .get_function = mediatek_gpio_get_function,
  90. };
  91. static int gpio_mediatek_probe(struct udevice *dev)
  92. {
  93. struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
  94. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  95. /* Tell the uclass how many GPIOs we have */
  96. if (plat) {
  97. uc_priv->gpio_count = plat->gpio_count;
  98. uc_priv->bank_name = plat->bank_name;
  99. }
  100. return 0;
  101. }
  102. /**
  103. * We have a top-level GPIO device with no actual GPIOs. It has a child
  104. * device for each Mediatek bank.
  105. */
  106. static int gpio_mediatek_bind(struct udevice *parent)
  107. {
  108. struct mediatek_gpio_platdata *plat = parent->platdata;
  109. ofnode node;
  110. int bank = 0;
  111. int ret;
  112. /* If this is a child device, there is nothing to do here */
  113. if (plat)
  114. return 0;
  115. mediatek_gpio_membase = dev_remap_addr(parent);
  116. if (!mediatek_gpio_membase)
  117. return -EINVAL;
  118. for (node = dev_read_first_subnode(parent); ofnode_valid(node);
  119. node = dev_read_next_subnode(node)) {
  120. struct mediatek_gpio_platdata *plat;
  121. struct udevice *dev;
  122. plat = calloc(1, sizeof(*plat));
  123. if (!plat)
  124. return -ENOMEM;
  125. plat->bank_name[0] = 'P';
  126. plat->bank_name[1] = 'A' + bank;
  127. plat->bank_name[2] = '\0';
  128. plat->gpio_count = MTK_BANK_WIDTH;
  129. plat->bank = bank;
  130. ret = device_bind(parent, parent->driver,
  131. plat->bank_name, plat, -1, &dev);
  132. if (ret)
  133. return ret;
  134. dev->node = node;
  135. bank++;
  136. }
  137. return 0;
  138. }
  139. static const struct udevice_id mediatek_gpio_ids[] = {
  140. { .compatible = "mtk,mt7621-gpio" },
  141. { }
  142. };
  143. U_BOOT_DRIVER(gpio_mediatek) = {
  144. .name = "gpio_mediatek",
  145. .id = UCLASS_GPIO,
  146. .ops = &gpio_mediatek_ops,
  147. .of_match = mediatek_gpio_ids,
  148. .bind = gpio_mediatek_bind,
  149. .probe = gpio_mediatek_probe,
  150. };