lpc32xx_gpio.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * LPC32xxGPIO driver
  4. *
  5. * (C) Copyright 2014 DENX Software Engineering GmbH
  6. * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch-lpc32xx/cpu.h>
  11. #include <asm/arch-lpc32xx/gpio.h>
  12. #include <asm-generic/gpio.h>
  13. #include <dm.h>
  14. /**
  15. * LPC32xx GPIOs work in banks but are non-homogeneous:
  16. * - each bank holds a different number of GPIOs
  17. * - some GPIOs are input/ouput, some input only, some output only;
  18. * - some GPIOs have different meanings as an input and as an output;
  19. * - some GPIOs are controlled on a given port and bit index, but
  20. * read on another one.
  21. *
  22. * In order to keep this code simple, GPIOS are considered here as
  23. * homogeneous and linear, from 0 to 159.
  24. *
  25. * ** WARNING #1 **
  26. *
  27. * Client code is responsible for properly using valid GPIO numbers,
  28. * including cases where a single physical GPIO has differing numbers
  29. * for setting its direction, reading it and/or writing to it.
  30. *
  31. * ** WARNING #2 **
  32. *
  33. * Please read NOTE in description of lpc32xx_gpio_get_function().
  34. */
  35. #define LPC32XX_GPIOS 160
  36. struct lpc32xx_gpio_priv {
  37. struct gpio_regs *regs;
  38. /* GPIO FUNCTION: SEE WARNING #2 */
  39. signed char function[LPC32XX_GPIOS];
  40. };
  41. /**
  42. * We have 4 GPIO ports of 32 bits each
  43. *
  44. * Port mapping offset (32 bits each):
  45. * - Port 0: 0
  46. * - Port 1: 32
  47. * - Port 2: 64
  48. * - Port 3: GPO / GPIO (output): 96
  49. * - Port 3: GPI: 128
  50. */
  51. #define MAX_GPIO 160
  52. #define GPIO_TO_PORT(gpio) ((gpio / 32) & 7)
  53. #define GPIO_TO_RANK(gpio) (gpio % 32)
  54. #define GPIO_TO_MASK(gpio) (1 << (gpio % 32))
  55. /**
  56. * Configure a GPIO number 'offset' as input
  57. */
  58. static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
  59. {
  60. int port, mask;
  61. struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
  62. struct gpio_regs *regs = gpio_priv->regs;
  63. port = GPIO_TO_PORT(offset);
  64. mask = GPIO_TO_MASK(offset);
  65. switch (port) {
  66. case 0:
  67. writel(mask, &regs->p0_dir_clr);
  68. break;
  69. case 1:
  70. writel(mask, &regs->p1_dir_clr);
  71. break;
  72. case 2:
  73. /* ports 2 and 3 share a common direction */
  74. writel(mask, &regs->p2_p3_dir_clr);
  75. break;
  76. case 3:
  77. /* Setup direction only for GPIO_xx. */
  78. if ((mask >= 25) && (mask <= 30))
  79. writel(mask, &regs->p2_p3_dir_clr);
  80. break;
  81. case 4:
  82. /* GPI_xx; nothing to do. */
  83. break;
  84. default:
  85. return -1;
  86. }
  87. /* GPIO FUNCTION: SEE WARNING #2 */
  88. gpio_priv->function[offset] = GPIOF_INPUT;
  89. return 0;
  90. }
  91. /**
  92. * Get the value of a GPIO
  93. */
  94. static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset)
  95. {
  96. int port, rank, mask, value;
  97. struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
  98. struct gpio_regs *regs = gpio_priv->regs;
  99. port = GPIO_TO_PORT(offset);
  100. switch (port) {
  101. case 0:
  102. value = readl(&regs->p0_inp_state);
  103. break;
  104. case 1:
  105. value = readl(&regs->p1_inp_state);
  106. break;
  107. case 2:
  108. value = readl(&regs->p2_inp_state);
  109. break;
  110. case 3:
  111. /* Read GPO_xx and GPIO_xx (as output) using p3_outp_state. */
  112. value = readl(&regs->p3_outp_state);
  113. break;
  114. case 4:
  115. /* Read GPI_xx and GPIO_xx (as input) using p3_inp_state. */
  116. value = readl(&regs->p3_inp_state);
  117. break;
  118. default:
  119. return -1;
  120. }
  121. rank = GPIO_TO_RANK(offset);
  122. mask = GPIO_TO_MASK(offset);
  123. return (value & mask) >> rank;
  124. }
  125. /**
  126. * Set a GPIO
  127. */
  128. static int gpio_set(struct udevice *dev, unsigned gpio)
  129. {
  130. int port, mask;
  131. struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
  132. struct gpio_regs *regs = gpio_priv->regs;
  133. port = GPIO_TO_PORT(gpio);
  134. mask = GPIO_TO_MASK(gpio);
  135. switch (port) {
  136. case 0:
  137. writel(mask, &regs->p0_outp_set);
  138. break;
  139. case 1:
  140. writel(mask, &regs->p1_outp_set);
  141. break;
  142. case 2:
  143. writel(mask, &regs->p2_outp_set);
  144. break;
  145. case 3:
  146. writel(mask, &regs->p3_outp_set);
  147. break;
  148. case 4:
  149. /* GPI_xx; invalid. */
  150. default:
  151. return -1;
  152. }
  153. return 0;
  154. }
  155. /**
  156. * Clear a GPIO
  157. */
  158. static int gpio_clr(struct udevice *dev, unsigned gpio)
  159. {
  160. int port, mask;
  161. struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
  162. struct gpio_regs *regs = gpio_priv->regs;
  163. port = GPIO_TO_PORT(gpio);
  164. mask = GPIO_TO_MASK(gpio);
  165. switch (port) {
  166. case 0:
  167. writel(mask, &regs->p0_outp_clr);
  168. break;
  169. case 1:
  170. writel(mask, &regs->p1_outp_clr);
  171. break;
  172. case 2:
  173. writel(mask, &regs->p2_outp_clr);
  174. break;
  175. case 3:
  176. writel(mask, &regs->p3_outp_clr);
  177. break;
  178. case 4:
  179. /* GPI_xx; invalid. */
  180. default:
  181. return -1;
  182. }
  183. return 0;
  184. }
  185. /**
  186. * Set the value of a GPIO
  187. */
  188. static int lpc32xx_gpio_set_value(struct udevice *dev, unsigned offset,
  189. int value)
  190. {
  191. if (value)
  192. return gpio_set(dev, offset);
  193. else
  194. return gpio_clr(dev, offset);
  195. }
  196. /**
  197. * Configure a GPIO number 'offset' as output with given initial value.
  198. */
  199. static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset,
  200. int value)
  201. {
  202. int port, mask;
  203. struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
  204. struct gpio_regs *regs = gpio_priv->regs;
  205. port = GPIO_TO_PORT(offset);
  206. mask = GPIO_TO_MASK(offset);
  207. switch (port) {
  208. case 0:
  209. writel(mask, &regs->p0_dir_set);
  210. break;
  211. case 1:
  212. writel(mask, &regs->p1_dir_set);
  213. break;
  214. case 2:
  215. /* ports 2 and 3 share a common direction */
  216. writel(mask, &regs->p2_p3_dir_set);
  217. break;
  218. case 3:
  219. /* Setup direction only for GPIO_xx. */
  220. if ((mask >= 25) && (mask <= 30))
  221. writel(mask, &regs->p2_p3_dir_set);
  222. break;
  223. case 4:
  224. /* GPI_xx; invalid. */
  225. default:
  226. return -1;
  227. }
  228. /* GPIO FUNCTION: SEE WARNING #2 */
  229. gpio_priv->function[offset] = GPIOF_OUTPUT;
  230. return lpc32xx_gpio_set_value(dev, offset, value);
  231. }
  232. /**
  233. * GPIO functions are supposed to be computed from their current
  234. * configuration, but that's way too complicated in LPC32XX. A simpler
  235. * approach is used, where the GPIO functions are cached in an array.
  236. * When the GPIO is in use, its function is either "input" or "output"
  237. * depending on its direction, otherwise its function is "unknown".
  238. *
  239. * ** NOTE **
  240. *
  241. * THIS APPROACH WAS CHOSEN DU TO THE COMPLEX NATURE OF THE LPC32XX
  242. * GPIOS; DO NOT TAKE THIS AS AN EXAMPLE FOR NEW CODE.
  243. */
  244. static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset)
  245. {
  246. struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
  247. return gpio_priv->function[offset];
  248. }
  249. static const struct dm_gpio_ops gpio_lpc32xx_ops = {
  250. .direction_input = lpc32xx_gpio_direction_input,
  251. .direction_output = lpc32xx_gpio_direction_output,
  252. .get_value = lpc32xx_gpio_get_value,
  253. .set_value = lpc32xx_gpio_set_value,
  254. .get_function = lpc32xx_gpio_get_function,
  255. };
  256. static int lpc32xx_gpio_probe(struct udevice *dev)
  257. {
  258. struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
  259. struct gpio_dev_priv *uc_priv = dev->uclass_priv;
  260. if (dev_of_offset(dev) == -1) {
  261. /* Tell the uclass how many GPIOs we have */
  262. uc_priv->gpio_count = LPC32XX_GPIOS;
  263. }
  264. /* set base address for GPIO registers */
  265. gpio_priv->regs = (struct gpio_regs *)GPIO_BASE;
  266. /* all GPIO functions are unknown until requested */
  267. /* GPIO FUNCTION: SEE WARNING #2 */
  268. memset(gpio_priv->function, GPIOF_UNKNOWN, sizeof(gpio_priv->function));
  269. return 0;
  270. }
  271. U_BOOT_DRIVER(gpio_lpc32xx) = {
  272. .name = "gpio_lpc32xx",
  273. .id = UCLASS_GPIO,
  274. .ops = &gpio_lpc32xx_ops,
  275. .probe = lpc32xx_gpio_probe,
  276. .priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_priv),
  277. };