iproc_gpio.c 7.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Broadcom
  4. */
  5. #include <common.h>
  6. #include <errno.h>
  7. #include <asm/gpio.h>
  8. #include <asm/io.h>
  9. #include <dm.h>
  10. #include <dm/device_compat.h>
  11. #include <dm/devres.h>
  12. #include <dm/pinctrl.h>
  13. /*
  14. * There are five GPIO bank register. Each bank can configure max of 32 gpios.
  15. * BANK0 - gpios 0 to 31
  16. * BANK1 - gpios 32 to 63
  17. * BANK2 - gpios 64 to 95
  18. * BANK3 - gpios 96 to 127
  19. * BANK4 - gpios 128 to 150
  20. *
  21. * Offset difference between consecutive bank register is 0x200
  22. */
  23. #define NGPIO_PER_BANK 32
  24. #define GPIO_BANK_SIZE 0x200
  25. #define GPIO_BANK(pin) ((pin) / NGPIO_PER_BANK)
  26. #define GPIO_SHIFT(pin) ((pin) % NGPIO_PER_BANK)
  27. #define GPIO_REG(pin, reg) (GPIO_BANK_SIZE * GPIO_BANK(pin) + (reg))
  28. /* device register offset */
  29. #define DATA_IN_OFFSET 0x00
  30. #define DATA_OUT_OFFSET 0x04
  31. #define OUT_EN_OFFSET 0x08
  32. /**
  33. * struct iproc_gpio_pctrl_map - gpio and pinctrl mapping
  34. * @gpio_pin: start of gpio number in gpio-ranges
  35. * @pctrl_pin: start of pinctrl number in gpio-ranges
  36. * @npins: total number of pins in gpio-ranges
  37. * @node: list node
  38. */
  39. struct iproc_gpio_pctrl_map {
  40. u32 gpio_pin;
  41. u32 pctrl_pin;
  42. u32 npins;
  43. struct list_head node;
  44. };
  45. /**
  46. * struct iproc_gpio_pctrl_map - gpio device instance
  47. * @pinctrl_dev:pointer to pinctrl device
  48. * @gpiomap: list node having mapping between gpio and pinctrl
  49. * @base: I/O register base address of gpio device
  50. * @name: gpio device name, ex GPIO0, GPIO1
  51. * @ngpios: total number of gpios
  52. */
  53. struct iproc_gpio_platdata {
  54. struct udevice *pinctrl_dev;
  55. struct list_head gpiomap;
  56. void __iomem *base;
  57. char *name;
  58. u32 ngpios;
  59. };
  60. /**
  61. * iproc_gpio_set_bit - set or clear one bit in an iproc GPIO register.
  62. *
  63. * The bit relates to a GPIO pin.
  64. *
  65. * @plat: iproc GPIO device
  66. * @reg: register offset
  67. * @gpio: GPIO pin
  68. * @set: set or clear
  69. */
  70. static inline void iproc_gpio_set_bit(struct iproc_gpio_platdata *plat,
  71. u32 reg, u32 gpio, bool set)
  72. {
  73. u32 offset = GPIO_REG(gpio, reg);
  74. u32 shift = GPIO_SHIFT(gpio);
  75. clrsetbits_le32(plat->base + offset, BIT(shift),
  76. (set ? BIT(shift) : 0));
  77. }
  78. static inline bool iproc_gpio_get_bit(struct iproc_gpio_platdata *plat,
  79. u32 reg, u32 gpio)
  80. {
  81. u32 offset = GPIO_REG(gpio, reg);
  82. u32 shift = GPIO_SHIFT(gpio);
  83. return readl(plat->base + offset) & BIT(shift);
  84. }
  85. /**
  86. * iproc_get_gpio_pctrl_mapping() - get associated pinctrl pin from gpio pin
  87. *
  88. * @plat: iproc GPIO device
  89. * @gpio: GPIO pin
  90. */
  91. static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_platdata *plat, u32 gpio)
  92. {
  93. struct iproc_gpio_pctrl_map *range = NULL;
  94. struct list_head *pos, *tmp;
  95. u32 ret = 0;
  96. list_for_each_safe(pos, tmp, &plat->gpiomap) {
  97. range = list_entry(pos, struct iproc_gpio_pctrl_map, node);
  98. if (gpio == range->gpio_pin ||
  99. gpio < (range->gpio_pin + range->npins)) {
  100. ret = range->pctrl_pin + (gpio - range->gpio_pin);
  101. break;
  102. }
  103. }
  104. return ret;
  105. }
  106. /**
  107. * iproc_get_gpio_pctrl_mapping() - get mapping between gpio and pinctrl
  108. *
  109. * Read dt node "gpio-ranges" to get gpio and pinctrl mapping and store
  110. * in private data structure to use it later while enabling gpio.
  111. *
  112. * @dev: pointer to GPIO device
  113. * @return 0 on success and -ENOMEM on failure
  114. */
  115. static int iproc_get_gpio_pctrl_mapping(struct udevice *dev)
  116. {
  117. struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
  118. struct iproc_gpio_pctrl_map *range = NULL;
  119. struct ofnode_phandle_args args;
  120. int index = 0, ret;
  121. for (;; index++) {
  122. ret = dev_read_phandle_with_args(dev, "gpio-ranges",
  123. NULL, 3, index, &args);
  124. if (ret)
  125. break;
  126. range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
  127. if (!range)
  128. return -ENOMEM;
  129. range->gpio_pin = args.args[0];
  130. range->pctrl_pin = args.args[1];
  131. range->npins = args.args[2];
  132. list_add_tail(&range->node, &plat->gpiomap);
  133. }
  134. return 0;
  135. }
  136. static int iproc_gpio_request(struct udevice *dev, u32 gpio, const char *label)
  137. {
  138. struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
  139. u32 pctrl;
  140. /* nothing to do if there is no corresponding pinctrl device */
  141. if (!plat->pinctrl_dev)
  142. return 0;
  143. pctrl = iproc_get_pctrl_from_gpio(plat, gpio);
  144. return pinctrl_request(plat->pinctrl_dev, pctrl, 0);
  145. }
  146. static int iproc_gpio_direction_input(struct udevice *dev, u32 gpio)
  147. {
  148. struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
  149. iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, false);
  150. dev_dbg(dev, "gpio:%u set input\n", gpio);
  151. return 0;
  152. }
  153. static int iproc_gpio_direction_output(struct udevice *dev, u32 gpio, int value)
  154. {
  155. struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
  156. iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, true);
  157. iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
  158. dev_dbg(dev, "gpio:%u set output, value:%d\n", gpio, value);
  159. return 0;
  160. }
  161. static int iproc_gpio_get_value(struct udevice *dev, u32 gpio)
  162. {
  163. struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
  164. int value;
  165. value = iproc_gpio_get_bit(plat, DATA_IN_OFFSET, gpio);
  166. dev_dbg(dev, "gpio:%u get, value:%d\n", gpio, value);
  167. return value;
  168. }
  169. static int iproc_gpio_set_value(struct udevice *dev, u32 gpio, int value)
  170. {
  171. struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
  172. if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
  173. iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
  174. dev_dbg(dev, "gpio:%u set, value:%d\n", gpio, value);
  175. return 0;
  176. }
  177. static int iproc_gpio_get_function(struct udevice *dev, u32 gpio)
  178. {
  179. struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
  180. if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
  181. return GPIOF_OUTPUT;
  182. else
  183. return GPIOF_INPUT;
  184. }
  185. static int iproc_gpio_ofdata_to_platdata(struct udevice *dev)
  186. {
  187. struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
  188. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  189. int ret;
  190. char name[10];
  191. plat->base = dev_read_addr_ptr(dev);
  192. if (!plat->base) {
  193. debug("%s: Failed to get base address\n", __func__);
  194. return -EINVAL;
  195. }
  196. ret = dev_read_u32(dev, "ngpios", &plat->ngpios);
  197. if (ret < 0) {
  198. dev_err(dev, "%s: Failed to get ngpios\n", __func__);
  199. return ret;
  200. }
  201. uclass_get_device_by_phandle(UCLASS_PINCTRL, dev, "gpio-ranges",
  202. &plat->pinctrl_dev);
  203. if (ret < 0) {
  204. dev_err(dev, "%s: Failed to get pinctrl phandle\n", __func__);
  205. return ret;
  206. }
  207. INIT_LIST_HEAD(&plat->gpiomap);
  208. ret = iproc_get_gpio_pctrl_mapping(dev);
  209. if (ret < 0) {
  210. dev_err(dev, "%s: Failed to get gpio to pctrl map ret(%d)\n",
  211. __func__, ret);
  212. return ret;
  213. }
  214. snprintf(name, sizeof(name), "GPIO%d", dev->req_seq);
  215. plat->name = strdup(name);
  216. if (!plat->name)
  217. return -ENOMEM;
  218. uc_priv->gpio_count = plat->ngpios;
  219. uc_priv->bank_name = plat->name;
  220. dev_info(dev, ":bank name(%s) base %p, #gpios %d\n",
  221. plat->name, plat->base, plat->ngpios);
  222. return 0;
  223. }
  224. static const struct dm_gpio_ops iproc_gpio_ops = {
  225. .request = iproc_gpio_request,
  226. .direction_input = iproc_gpio_direction_input,
  227. .direction_output = iproc_gpio_direction_output,
  228. .get_value = iproc_gpio_get_value,
  229. .set_value = iproc_gpio_set_value,
  230. .get_function = iproc_gpio_get_function,
  231. };
  232. static const struct udevice_id iproc_gpio_ids[] = {
  233. { .compatible = "brcm,iproc-gpio" },
  234. { }
  235. };
  236. U_BOOT_DRIVER(iproc_gpio) = {
  237. .name = "iproc_gpio",
  238. .id = UCLASS_GPIO,
  239. .of_match = iproc_gpio_ids,
  240. .ops = &iproc_gpio_ops,
  241. .ofdata_to_platdata = iproc_gpio_ofdata_to_platdata,
  242. .platdata_auto_alloc_size = sizeof(struct iproc_gpio_platdata),
  243. };