intel_ich6_gpio.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors.
  4. */
  5. /*
  6. * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
  7. * through the PCI bus. Each PCI device has 256 bytes of configuration space,
  8. * consisting of a standard header and a device-specific set of registers. PCI
  9. * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
  10. * other things). Within the PCI configuration space, the GPIOBASE register
  11. * tells us where in the device's I/O region we can find more registers to
  12. * actually access the GPIOs.
  13. *
  14. * PCI bus/device/function 0:1f:0 => PCI config registers
  15. * PCI config register "GPIOBASE"
  16. * PCI I/O space + [GPIOBASE] => start of GPIO registers
  17. * GPIO registers => gpio pin function, direction, value
  18. *
  19. *
  20. * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
  21. * ICH versions have more, but the decoding the matrix that describes them is
  22. * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
  23. * but they will ONLY work for certain unspecified chipsets because the offset
  24. * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
  25. * reserved or subject to arcane restrictions.
  26. */
  27. #include <common.h>
  28. #include <dm.h>
  29. #include <errno.h>
  30. #include <fdtdec.h>
  31. #include <log.h>
  32. #include <pch.h>
  33. #include <pci.h>
  34. #include <asm/cpu.h>
  35. #include <asm/gpio.h>
  36. #include <asm/io.h>
  37. #include <asm/pci.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #define GPIO_PER_BANK 32
  40. struct ich6_bank_priv {
  41. /* These are I/O addresses */
  42. uint16_t use_sel;
  43. uint16_t io_sel;
  44. uint16_t lvl;
  45. u32 lvl_write_cache;
  46. bool use_lvl_write_cache;
  47. };
  48. #define GPIO_USESEL_OFFSET(x) (x)
  49. #define GPIO_IOSEL_OFFSET(x) (x + 4)
  50. #define GPIO_LVL_OFFSET(x) (x + 8)
  51. static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset,
  52. int value)
  53. {
  54. u32 val;
  55. if (bank->use_lvl_write_cache)
  56. val = bank->lvl_write_cache;
  57. else
  58. val = inl(bank->lvl);
  59. if (value)
  60. val |= (1UL << offset);
  61. else
  62. val &= ~(1UL << offset);
  63. outl(val, bank->lvl);
  64. if (bank->use_lvl_write_cache)
  65. bank->lvl_write_cache = val;
  66. return 0;
  67. }
  68. static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
  69. {
  70. u32 val;
  71. if (!dir) {
  72. val = inl(base);
  73. val |= (1UL << offset);
  74. outl(val, base);
  75. } else {
  76. val = inl(base);
  77. val &= ~(1UL << offset);
  78. outl(val, base);
  79. }
  80. return 0;
  81. }
  82. static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
  83. {
  84. struct ich6_bank_platdata *plat = dev_get_platdata(dev);
  85. u32 gpiobase;
  86. int offset;
  87. int ret;
  88. ret = pch_get_gpio_base(dev->parent, &gpiobase);
  89. if (ret)
  90. return ret;
  91. offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
  92. if (offset == -1) {
  93. debug("%s: Invalid register offset %d\n", __func__, offset);
  94. return -EINVAL;
  95. }
  96. plat->offset = offset;
  97. plat->base_addr = gpiobase + offset;
  98. plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  99. "bank-name", NULL);
  100. return 0;
  101. }
  102. static int ich6_gpio_probe(struct udevice *dev)
  103. {
  104. struct ich6_bank_platdata *plat = dev_get_platdata(dev);
  105. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  106. struct ich6_bank_priv *bank = dev_get_priv(dev);
  107. const void *prop;
  108. uc_priv->gpio_count = GPIO_PER_BANK;
  109. uc_priv->bank_name = plat->bank_name;
  110. bank->use_sel = plat->base_addr;
  111. bank->io_sel = plat->base_addr + 4;
  112. bank->lvl = plat->base_addr + 8;
  113. prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  114. "use-lvl-write-cache", NULL);
  115. if (prop)
  116. bank->use_lvl_write_cache = true;
  117. else
  118. bank->use_lvl_write_cache = false;
  119. bank->lvl_write_cache = 0;
  120. return 0;
  121. }
  122. static int ich6_gpio_request(struct udevice *dev, unsigned offset,
  123. const char *label)
  124. {
  125. struct ich6_bank_priv *bank = dev_get_priv(dev);
  126. u32 tmplong;
  127. /*
  128. * Make sure that the GPIO pin we want isn't already in use for some
  129. * built-in hardware function. We have to check this for every
  130. * requested pin.
  131. */
  132. tmplong = inl(bank->use_sel);
  133. if (!(tmplong & (1UL << offset))) {
  134. debug("%s: gpio %d is reserved for internal use\n", __func__,
  135. offset);
  136. return -EPERM;
  137. }
  138. return 0;
  139. }
  140. static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
  141. {
  142. struct ich6_bank_priv *bank = dev_get_priv(dev);
  143. return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
  144. }
  145. static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
  146. int value)
  147. {
  148. int ret;
  149. struct ich6_bank_priv *bank = dev_get_priv(dev);
  150. ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
  151. if (ret)
  152. return ret;
  153. return _ich6_gpio_set_value(bank, offset, value);
  154. }
  155. static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
  156. {
  157. struct ich6_bank_priv *bank = dev_get_priv(dev);
  158. u32 tmplong;
  159. int r;
  160. tmplong = inl(bank->lvl);
  161. if (bank->use_lvl_write_cache)
  162. tmplong |= bank->lvl_write_cache;
  163. r = (tmplong & (1UL << offset)) ? 1 : 0;
  164. return r;
  165. }
  166. static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
  167. int value)
  168. {
  169. struct ich6_bank_priv *bank = dev_get_priv(dev);
  170. return _ich6_gpio_set_value(bank, offset, value);
  171. }
  172. static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
  173. {
  174. struct ich6_bank_priv *bank = dev_get_priv(dev);
  175. u32 mask = 1UL << offset;
  176. if (!(inl(bank->use_sel) & mask))
  177. return GPIOF_FUNC;
  178. if (inl(bank->io_sel) & mask)
  179. return GPIOF_INPUT;
  180. else
  181. return GPIOF_OUTPUT;
  182. }
  183. static const struct dm_gpio_ops gpio_ich6_ops = {
  184. .request = ich6_gpio_request,
  185. .direction_input = ich6_gpio_direction_input,
  186. .direction_output = ich6_gpio_direction_output,
  187. .get_value = ich6_gpio_get_value,
  188. .set_value = ich6_gpio_set_value,
  189. .get_function = ich6_gpio_get_function,
  190. };
  191. static const struct udevice_id intel_ich6_gpio_ids[] = {
  192. { .compatible = "intel,ich6-gpio" },
  193. { }
  194. };
  195. U_BOOT_DRIVER(gpio_ich6) = {
  196. .name = "gpio_ich6",
  197. .id = UCLASS_GPIO,
  198. .of_match = intel_ich6_gpio_ids,
  199. .ops = &gpio_ich6_ops,
  200. .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
  201. .probe = ich6_gpio_probe,
  202. .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
  203. .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
  204. };