intel_gpio.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Google LLC
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <log.h>
  10. #include <p2sb.h>
  11. #include <pch.h>
  12. #include <pci.h>
  13. #include <syscon.h>
  14. #include <acpi/acpi_device.h>
  15. #include <asm/cpu.h>
  16. #include <asm/gpio.h>
  17. #include <asm/intel_pinctrl.h>
  18. #include <asm/intel_pinctrl_defs.h>
  19. #include <asm/io.h>
  20. #include <asm/pci.h>
  21. #include <asm/arch/gpio.h>
  22. #include <dm/acpi.h>
  23. #include <dt-bindings/gpio/x86-gpio.h>
  24. static int intel_gpio_direction_input(struct udevice *dev, uint offset)
  25. {
  26. struct udevice *pinctrl = dev_get_parent(dev);
  27. uint config_offset;
  28. config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
  29. pcr_clrsetbits32(pinctrl, config_offset,
  30. PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
  31. PAD_CFG0_RX_DISABLE,
  32. PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE);
  33. return 0;
  34. }
  35. static int intel_gpio_direction_output(struct udevice *dev, uint offset,
  36. int value)
  37. {
  38. struct udevice *pinctrl = dev_get_parent(dev);
  39. uint config_offset;
  40. config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
  41. pcr_clrsetbits32(pinctrl, config_offset,
  42. PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
  43. PAD_CFG0_TX_DISABLE | PAD_CFG0_TX_STATE,
  44. PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE |
  45. (value ? PAD_CFG0_TX_STATE : 0));
  46. return 0;
  47. }
  48. static int intel_gpio_get_value(struct udevice *dev, uint offset)
  49. {
  50. struct udevice *pinctrl = dev_get_parent(dev);
  51. uint mode, rx_tx;
  52. u32 reg;
  53. reg = intel_pinctrl_get_config_reg(pinctrl, offset);
  54. mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
  55. if (!mode) {
  56. rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
  57. if (rx_tx == PAD_CFG0_TX_DISABLE)
  58. return reg & PAD_CFG0_RX_STATE ? 1 : 0;
  59. else if (rx_tx == PAD_CFG0_RX_DISABLE)
  60. return reg & PAD_CFG0_TX_STATE ? 1 : 0;
  61. }
  62. return 0;
  63. }
  64. static int intel_gpio_set_value(struct udevice *dev, unsigned int offset,
  65. int value)
  66. {
  67. struct udevice *pinctrl = dev_get_parent(dev);
  68. uint config_offset;
  69. config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
  70. pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
  71. value ? PAD_CFG0_TX_STATE : 0);
  72. return 0;
  73. }
  74. static int intel_gpio_get_function(struct udevice *dev, uint offset)
  75. {
  76. struct udevice *pinctrl = dev_get_parent(dev);
  77. uint mode, rx_tx;
  78. u32 reg;
  79. reg = intel_pinctrl_get_config_reg(pinctrl, offset);
  80. mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
  81. if (!mode) {
  82. rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
  83. if (rx_tx == PAD_CFG0_TX_DISABLE)
  84. return GPIOF_INPUT;
  85. else if (rx_tx == PAD_CFG0_RX_DISABLE)
  86. return GPIOF_OUTPUT;
  87. }
  88. return GPIOF_FUNC;
  89. }
  90. static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
  91. struct ofnode_phandle_args *args)
  92. {
  93. struct udevice *pinctrl, *dev;
  94. int gpio, ret;
  95. /*
  96. * GPIO numbers are global in the device tree so it doesn't matter
  97. * which one is used
  98. */
  99. gpio = args->args[0];
  100. ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
  101. if (ret)
  102. return log_msg_ret("bad", ret);
  103. device_find_first_child(pinctrl, &dev);
  104. if (!dev)
  105. return log_msg_ret("no child", -ENOENT);
  106. desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
  107. desc->dev = dev;
  108. return 0;
  109. }
  110. #if CONFIG_IS_ENABLED(ACPIGEN)
  111. static int intel_gpio_get_acpi(const struct gpio_desc *desc,
  112. struct acpi_gpio *gpio)
  113. {
  114. struct udevice *pinctrl;
  115. int ret;
  116. if (!dm_gpio_is_valid(desc))
  117. return -ENOENT;
  118. pinctrl = dev_get_parent(desc->dev);
  119. memset(gpio, '\0', sizeof(*gpio));
  120. gpio->type = ACPI_GPIO_TYPE_IO;
  121. gpio->pull = ACPI_GPIO_PULL_DEFAULT;
  122. gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
  123. gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
  124. gpio->pin_count = 1;
  125. gpio->pins[0] = intel_pinctrl_get_acpi_pin(pinctrl, desc->offset);
  126. gpio->pin0_addr = intel_pinctrl_get_config_reg_addr(pinctrl,
  127. desc->offset);
  128. ret = acpi_get_path(pinctrl, gpio->resource, sizeof(gpio->resource));
  129. if (ret)
  130. return log_msg_ret("resource", ret);
  131. return 0;
  132. }
  133. #endif
  134. static int intel_gpio_probe(struct udevice *dev)
  135. {
  136. return 0;
  137. }
  138. static int intel_gpio_ofdata_to_platdata(struct udevice *dev)
  139. {
  140. struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
  141. struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
  142. const struct pad_community *comm = pinctrl_priv->comm;
  143. upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
  144. upriv->bank_name = dev->name;
  145. return 0;
  146. }
  147. static const struct dm_gpio_ops gpio_intel_ops = {
  148. .direction_input = intel_gpio_direction_input,
  149. .direction_output = intel_gpio_direction_output,
  150. .get_value = intel_gpio_get_value,
  151. .set_value = intel_gpio_set_value,
  152. .get_function = intel_gpio_get_function,
  153. .xlate = intel_gpio_xlate,
  154. #if CONFIG_IS_ENABLED(ACPIGEN)
  155. .get_acpi = intel_gpio_get_acpi,
  156. #endif
  157. };
  158. static const struct udevice_id intel_intel_gpio_ids[] = {
  159. { .compatible = "intel,gpio" },
  160. { }
  161. };
  162. U_BOOT_DRIVER(intel_gpio) = {
  163. .name = "intel_gpio",
  164. .id = UCLASS_GPIO,
  165. .of_match = intel_intel_gpio_ids,
  166. .ops = &gpio_intel_ops,
  167. .ofdata_to_platdata = intel_gpio_ofdata_to_platdata,
  168. .probe = intel_gpio_probe,
  169. };