xilinx.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  4. *
  5. * (C) Copyright 2002
  6. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  7. * Keith Outwater, keith_outwater@mvis.com
  8. */
  9. /*
  10. * Xilinx FPGA support
  11. */
  12. #include <common.h>
  13. #include <fpga.h>
  14. #include <log.h>
  15. #include <virtex2.h>
  16. #include <spartan2.h>
  17. #include <spartan3.h>
  18. #include <zynqpl.h>
  19. /* Local Static Functions */
  20. static int xilinx_validate(xilinx_desc *desc, char *fn);
  21. /* ------------------------------------------------------------------------- */
  22. int fpga_is_partial_data(int devnum, size_t img_len)
  23. {
  24. const fpga_desc * const desc = fpga_get_desc(devnum);
  25. xilinx_desc *desc_xilinx = desc->devdesc;
  26. /* Check datasize against FPGA size */
  27. if (img_len >= desc_xilinx->size)
  28. return 0;
  29. /* datasize is smaller, must be partial data */
  30. return 1;
  31. }
  32. int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
  33. bitstream_type bstype)
  34. {
  35. unsigned int length;
  36. unsigned int swapsize;
  37. unsigned char *dataptr;
  38. unsigned int i;
  39. const fpga_desc *desc;
  40. xilinx_desc *xdesc;
  41. dataptr = (unsigned char *)fpgadata;
  42. /* Find out fpga_description */
  43. desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
  44. /* Assign xilinx device description */
  45. xdesc = desc->devdesc;
  46. /* skip the first bytes of the bitsteam, their meaning is unknown */
  47. length = (*dataptr << 8) + *(dataptr + 1);
  48. dataptr += 2;
  49. dataptr += length;
  50. /* get design name (identifier, length, string) */
  51. length = (*dataptr << 8) + *(dataptr + 1);
  52. dataptr += 2;
  53. if (*dataptr++ != 0x61) {
  54. debug("%s: Design name id not recognized in bitstream\n",
  55. __func__);
  56. return FPGA_FAIL;
  57. }
  58. length = (*dataptr << 8) + *(dataptr + 1);
  59. dataptr += 2;
  60. printf(" design filename = \"%s\"\n", dataptr);
  61. dataptr += length;
  62. /* get part number (identifier, length, string) */
  63. if (*dataptr++ != 0x62) {
  64. printf("%s: Part number id not recognized in bitstream\n",
  65. __func__);
  66. return FPGA_FAIL;
  67. }
  68. length = (*dataptr << 8) + *(dataptr + 1);
  69. dataptr += 2;
  70. if (xdesc->name) {
  71. i = (ulong)strstr((char *)dataptr, xdesc->name);
  72. if (!i) {
  73. printf("%s: Wrong bitstream ID for this device\n",
  74. __func__);
  75. printf("%s: Bitstream ID %s, current device ID %d/%s\n",
  76. __func__, dataptr, devnum, xdesc->name);
  77. return FPGA_FAIL;
  78. }
  79. } else {
  80. printf("%s: Please fill correct device ID to xilinx_desc\n",
  81. __func__);
  82. }
  83. printf(" part number = \"%s\"\n", dataptr);
  84. dataptr += length;
  85. /* get date (identifier, length, string) */
  86. if (*dataptr++ != 0x63) {
  87. printf("%s: Date identifier not recognized in bitstream\n",
  88. __func__);
  89. return FPGA_FAIL;
  90. }
  91. length = (*dataptr << 8) + *(dataptr+1);
  92. dataptr += 2;
  93. printf(" date = \"%s\"\n", dataptr);
  94. dataptr += length;
  95. /* get time (identifier, length, string) */
  96. if (*dataptr++ != 0x64) {
  97. printf("%s: Time identifier not recognized in bitstream\n",
  98. __func__);
  99. return FPGA_FAIL;
  100. }
  101. length = (*dataptr << 8) + *(dataptr+1);
  102. dataptr += 2;
  103. printf(" time = \"%s\"\n", dataptr);
  104. dataptr += length;
  105. /* get fpga data length (identifier, length) */
  106. if (*dataptr++ != 0x65) {
  107. printf("%s: Data length id not recognized in bitstream\n",
  108. __func__);
  109. return FPGA_FAIL;
  110. }
  111. swapsize = ((unsigned int) *dataptr << 24) +
  112. ((unsigned int) *(dataptr + 1) << 16) +
  113. ((unsigned int) *(dataptr + 2) << 8) +
  114. ((unsigned int) *(dataptr + 3));
  115. dataptr += 4;
  116. printf(" bytes in bitstream = %d\n", swapsize);
  117. return fpga_load(devnum, dataptr, swapsize, bstype);
  118. }
  119. int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
  120. bitstream_type bstype)
  121. {
  122. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  123. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  124. return FPGA_FAIL;
  125. }
  126. if (!desc->operations || !desc->operations->load) {
  127. printf("%s: Missing load operation\n", __func__);
  128. return FPGA_FAIL;
  129. }
  130. return desc->operations->load(desc, buf, bsize, bstype);
  131. }
  132. #if defined(CONFIG_CMD_FPGA_LOADFS)
  133. int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
  134. fpga_fs_info *fpga_fsinfo)
  135. {
  136. if (!xilinx_validate(desc, (char *)__func__)) {
  137. printf("%s: Invalid device descriptor\n", __func__);
  138. return FPGA_FAIL;
  139. }
  140. if (!desc->operations || !desc->operations->loadfs) {
  141. printf("%s: Missing loadfs operation\n", __func__);
  142. return FPGA_FAIL;
  143. }
  144. return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
  145. }
  146. #endif
  147. #if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
  148. int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
  149. struct fpga_secure_info *fpga_sec_info)
  150. {
  151. if (!xilinx_validate(desc, (char *)__func__)) {
  152. printf("%s: Invalid device descriptor\n", __func__);
  153. return FPGA_FAIL;
  154. }
  155. if (!desc->operations || !desc->operations->loads) {
  156. printf("%s: Missing loads operation\n", __func__);
  157. return FPGA_FAIL;
  158. }
  159. return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
  160. }
  161. #endif
  162. int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  163. {
  164. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  165. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  166. return FPGA_FAIL;
  167. }
  168. if (!desc->operations || !desc->operations->dump) {
  169. printf("%s: Missing dump operation\n", __func__);
  170. return FPGA_FAIL;
  171. }
  172. return desc->operations->dump(desc, buf, bsize);
  173. }
  174. int xilinx_info(xilinx_desc *desc)
  175. {
  176. int ret_val = FPGA_FAIL;
  177. if (xilinx_validate (desc, (char *)__FUNCTION__)) {
  178. printf ("Family: \t");
  179. switch (desc->family) {
  180. case xilinx_spartan2:
  181. printf ("Spartan-II\n");
  182. break;
  183. case xilinx_spartan3:
  184. printf ("Spartan-III\n");
  185. break;
  186. case xilinx_virtex2:
  187. printf ("Virtex-II\n");
  188. break;
  189. case xilinx_zynq:
  190. printf("Zynq PL\n");
  191. break;
  192. case xilinx_zynqmp:
  193. printf("ZynqMP PL\n");
  194. break;
  195. case xilinx_versal:
  196. printf("Versal PL\n");
  197. break;
  198. /* Add new family types here */
  199. default:
  200. printf ("Unknown family type, %d\n", desc->family);
  201. }
  202. printf ("Interface type:\t");
  203. switch (desc->iface) {
  204. case slave_serial:
  205. printf ("Slave Serial\n");
  206. break;
  207. case master_serial: /* Not used */
  208. printf ("Master Serial\n");
  209. break;
  210. case slave_parallel:
  211. printf ("Slave Parallel\n");
  212. break;
  213. case jtag_mode: /* Not used */
  214. printf ("JTAG Mode\n");
  215. break;
  216. case slave_selectmap:
  217. printf ("Slave SelectMap Mode\n");
  218. break;
  219. case master_selectmap:
  220. printf ("Master SelectMap Mode\n");
  221. break;
  222. case devcfg:
  223. printf("Device configuration interface (Zynq)\n");
  224. break;
  225. case csu_dma:
  226. printf("csu_dma configuration interface (ZynqMP)\n");
  227. break;
  228. case cfi:
  229. printf("CFI configuration interface (Versal)\n");
  230. break;
  231. /* Add new interface types here */
  232. default:
  233. printf ("Unsupported interface type, %d\n", desc->iface);
  234. }
  235. printf("Device Size: \t%zd bytes\n"
  236. "Cookie: \t0x%x (%d)\n",
  237. desc->size, desc->cookie, desc->cookie);
  238. if (desc->name)
  239. printf("Device name: \t%s\n", desc->name);
  240. if (desc->iface_fns)
  241. printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
  242. else
  243. printf ("No Device Function Table.\n");
  244. if (desc->operations && desc->operations->info)
  245. desc->operations->info(desc);
  246. ret_val = FPGA_SUCCESS;
  247. } else {
  248. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  249. }
  250. return ret_val;
  251. }
  252. /* ------------------------------------------------------------------------- */
  253. static int xilinx_validate(xilinx_desc *desc, char *fn)
  254. {
  255. int ret_val = false;
  256. if (desc) {
  257. if ((desc->family > min_xilinx_type) &&
  258. (desc->family < max_xilinx_type)) {
  259. if ((desc->iface > min_xilinx_iface_type) &&
  260. (desc->iface < max_xilinx_iface_type)) {
  261. if (desc->size) {
  262. ret_val = true;
  263. } else
  264. printf ("%s: NULL part size\n", fn);
  265. } else
  266. printf ("%s: Invalid Interface type, %d\n",
  267. fn, desc->iface);
  268. } else
  269. printf ("%s: Invalid family type, %d\n", fn, desc->family);
  270. } else
  271. printf ("%s: NULL descriptor!\n", fn);
  272. return ret_val;
  273. }