stratixv.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <altera.h>
  7. #include <log.h>
  8. #include <spi.h>
  9. #include <asm/io.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. /* Write the RBF data to FPGA via SPI */
  13. static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
  14. unsigned long rbf_size)
  15. {
  16. struct spi_slave *slave;
  17. int ret;
  18. debug("%s (%d): data=%p size=%ld\n",
  19. __func__, __LINE__, rbf_data, rbf_size);
  20. /* FIXME: How to get the max. SPI clock and SPI mode? */
  21. slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
  22. if (!slave)
  23. return -1;
  24. if (spi_claim_bus(slave))
  25. return -1;
  26. ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
  27. SPI_XFER_BEGIN | SPI_XFER_END);
  28. spi_release_bus(slave);
  29. return ret;
  30. }
  31. /*
  32. * This is the interface used by FPGA driver.
  33. * Return 0 for sucess, non-zero for error.
  34. */
  35. int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  36. {
  37. altera_board_specific_func *pfns = desc->iface_fns;
  38. int cookie = desc->cookie;
  39. int spi_bus;
  40. int spi_dev;
  41. int ret = 0;
  42. if ((u32)rbf_data & 0x3) {
  43. puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
  44. return -EINVAL;
  45. }
  46. /* Run the pre configuration function if there is one */
  47. if (pfns->pre)
  48. (pfns->pre)(cookie);
  49. /* Establish the initial state */
  50. if (pfns->config) {
  51. /* De-assert nCONFIG */
  52. (pfns->config)(false, true, cookie);
  53. /* nConfig minimum low pulse width is 2us */
  54. udelay(200);
  55. /* Assert nCONFIG */
  56. (pfns->config)(true, true, cookie);
  57. /* nCONFIG high to first rising clock on DCLK min 1506 us */
  58. udelay(1600);
  59. }
  60. /* Write the RBF data to FPGA */
  61. if (pfns->write) {
  62. /*
  63. * Use board specific data function to write bitstream
  64. * into the FPGA
  65. */
  66. ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
  67. } else {
  68. /*
  69. * Use common SPI functions to write bitstream into the
  70. * FPGA
  71. */
  72. spi_bus = COOKIE2SPI_BUS(cookie);
  73. spi_dev = COOKIE2SPI_DEV(cookie);
  74. ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
  75. }
  76. if (ret)
  77. return ret;
  78. /* Check done pin */
  79. if (pfns->done) {
  80. ret = (pfns->done)(cookie);
  81. if (ret)
  82. printf("Error: DONE not set (ret=%d)!\n", ret);
  83. }
  84. return ret;
  85. }